Design Note 1031: Interfacing to High Performance Pipeline ADCs

Introduction

High speed ADCs use a sample and hold input structure comprising a fast CMOS switch and a sampling capacitor. When the CMOS switch closes, the sampling capacitor shares its stored charge with the preceding drive circuitry (charge kickback). As the sampling capacitor and its stored charge increase in size, more attention must be paid to the drive circuitry.

Pipeline ADCs typically have a few picofarads of sample capacitance. In contrast, the high performance 16-bit 20Msps LTC2270 high speed ADC uses a 17pF sampling capacitor. The advantage of a relatively large sampling capacitor is a significant reduction of internal kT/C noise and therefore better signal-to-noise ratio (SNR). The disadvantage is that the part becomes more difficult to drive. Every time the CMOS switch closes, the sampling capacitor kicks back significantly more charge to the driver than would a smaller sampling capacitor.

The interface filter, between the driver and ADC, demands extra attention. An inappropriate filter deteriorates SNR and SFDR. This filter must limit noise, and also adequately settle charge kickback to protect the driver and the ADC from reflections. This design note shows how to design a suitable driver and 10MHz interface filter for the LTC2270.

Driver Selection

The LTC2270 has a stellar 84.1dB SNR (46µVRMS input referred noise), in addition to 99dB SFDR at baseband. To ensure that performance of the LTC2270 is optimum, the ADC driver must be tolerant to large charge kickbacks, drive a relatively heavy load and have low wideband noise.

Common mode termination on the ADC input, necessary to maintain the low distortion of the ADC, results in a significant load for the driver. Additionally, the driver must be extremely low noise. As a point of reference, a 3nV/√Hz amplifier across a 10MHz bandwidth would deteriorate the SNR by more than 1dB. The LTC6409 is a good choice to meet these requirements. It provides drive and output swing to allow for enough common mode termination and an input referred voltage noise of 1.1nV/√Hz.

Filter Design

High frequency pipeline ADCs digitize an enormous bandwidth of information. The LTC2270 exhibits a full power bandwidth of 200MHz, enabling it to digitize 20 Nyquist zones and integrate wideband noise distortion, clocking frequencies and other radio frequency artifacts.

The interface filter limits the broadband noise from the driver, but without careful design, the filter can also deteriorate the SFDR. To obtain optimum SFDR specifications for the driver and the ADC, start with these broad guidelines:

• The ADC should see low impedance from its inputs. Since sampling is primarily a common-mode effect, this termination should be common mode.
• The driver should see relatively high impedance, especially when driving the ADC to full-scale.
• Filters with absorptive (never open or short) characteristics behave better.
• A common mode termination capacitor mitigates the effect of charge kickback on the driver and the ADC. A filter that contains common mode termination and properly settles charge kickback will optimize SFDR.

There are other interface filter design guidelines, especially concerning layout, but these considerations provide some basic direction. The filter in Figure 1 illustrates these specifications and performs well in lab. Figure 2 shows the full interface.

Lab Testing

The proper filter and termination for a particular design must be experimentally verified, as there is no single rule or equation that covers all setups. Lab tests ensure that the filter can tolerate these circuit realities, such as board parasitics. Lab tests can also prove that resistive and reactive termination can have a significant impact on system distortion.

For instance, Figure 3 shows a 2-tone test performed using the interface in Figure 2. Additionally, Figure 4 shows the distortion deterioration between absorptive termination and no-output termination. The in-band SFDR is better than 100dB and the SNR has only been deteriorated by 0.4dB. Lab results may also display unexpected excess noise or distortion. In most cases, some amount of tweaking is necessary. For instance, reducing the bandwidth may increase SNR, but often at the expense of distortion.

Here are a few practical rules to keep in mind for interface filter design:

• Keep the filter symmetric in value and layout
• Use only low distortion capacitors like COG/NPO, de-Q or use Low Q filter inductors
• Provide common-mode roll-off

Conclusion

Despite the LTC2270’s additional sample capacitance, a suitable driver and 10MHz filter provide almost no deterioration to the LTC2270’s data sheet specifications. While the LTC6409 may work with the LTC2270 to digitize higher frequencies, the filter design may not be as straightforward as replacing inductors and capacitors with scaled values. In the end, use bench testing to produce empirical evidence to prove the adequacy of any ADC interface.

作者

Tyler Hutchison

Clarence Mayott

Clarence Mayott是混合信号应用部负责人，已在凌力尔特工作十多年。

Clarence负责完整信号链演示板以及放大器和ADC产品组合的设计，帮助最终用户更轻松地评估系统。他还参与配套板设计，包括时钟和信号源板，以便评估高速ADC演示板。Clarence管理PScope的持续开发，该软件用于各种流水线和SAR ADC。

随着LTC2000的发布，Clarence又开始涉足高速DAC和波形生成以及高速ADC领域。作为应用部门负责人，他监管LTDACGen—一款新型软件工具，用于生成高速DAC复杂波形—的持续开发。

Clarence先生拥有圣塔克拉拉大学电气工程硕士学位和位于加利福尼亚州圣路易斯奥比斯波加利福尼亚州立工业大学电气工程学士学位。