AN-7645: Migrating Designs from DS2431 to DS28E54

Introduction

This application note explains the differences between DS2431 and DS28E54 to help the designer easily transition to the DS28E54 as well as explain the benefits of adding security to an existing design.

Package and Pin Compatibility

In general, the DS28E54 is a pin-compatible, drop-in replacement for the DS2431. The DS2431 comes in packages of TO-92, TSOC, TDFN-EP, SFN (6mm x 6mm x 0.9mm), SFN (3.5mm x 6.5mm x 0.75mm) and UCSPR, while the DS28E54 comes in packages of TO-92, TSOC, TDFN-EP, SFN (3.5mm x 6.5mm x 0.75mm). The DS28E54 does not have support for 6mm x 6mm x 0.9mm SFN and UCSPR package. The pin configuration remains the same in the available packages.

Operation Condition Changes

The DS2431 and DS28E54 contain some unavoidable electrical characteristic differences. This section examines the electrical parameters that may impact an existing design. A product engineer can easily examine these differences and conclude whether any of the recommended actions described in this section are required or not.

1. Programming Current

Explanation:

This parameter specifies the current that the 1-Wire EEPROM consumes to write to it. The DS2431 uses less current during programming than the DS28E54. To ensure reliable programming during the write cycle, the voltage on the 1-Wire line must not fall below the specified limit. The voltage drop across the pullup resistor is calculated as V = R_PUP x I_PROG. The voltage on the 1-Wire line V = (V_PUP - V) must not fall below DS28E54's 1.71V during EEPROM programming.

Note 15: Current drawn from IO during a SPU operation interval. The pullup circuit on IO during the SPU operation interval should be such that the voltage at IO is greater than or equal to V_SPUMIN. A low-impedance bypass of R_PUP activated during the SPU operation is the recommended way to meet this requirement.

Impact:

To ensure that the DS28E54's 1.71V minimum requirement is met, it is required to know the maximum programming current. Example, to meet the 1.71V minimum requirement in a 5V environment, the maximum pullup resistor must be R_PUP <= (5V-1.71V)/3.5mA = 940Ω.

Action:

Adjust the pullup resistor to meet the requirements for the programming current or use a low-impedance p-channel to bypass RPUP to supply the additional current. Confirm VIL levels are not violated for both host and peripheral if RPUP is lowered.

2. Recovery Time

Explanation:

This parameter specifies the minimum idle time required between time slots for the internal parasitic capacitor to fully recharge. The DS2431 recharge time is slightly faster than the DS28E54.

Impact:

If the application uses overdrive speed and the recovery time is too short, it is possible for the 1-Wire device to POR, causing the device to operate unreliably.

Action:

If using overdrive speed, ensure the minimum recovery time is met. If needed, modify the application firmware or hardware to comply with the changes.

3. Write-Zero Low Time

Explanation:

This parameter specifies the minimum logic low time required for the device to interpret a 0 bit correctly.

Impact:

The device may operate unreliably if the timing is not met. Additionally, legacy adapters such as DS9097U and DS9490 are no longer compatible with DS28E54.

Action:

Verify that the 1-Wire controller matches the write-zero low time requirements. If using a legacy adapter, replace it with a compatible adapter.

4. Power-Up Time

Explanation:

This parameter specifies the time required before communicating with 1-Wire device. Both the DS2431 and DS28E54 produce a presence pulse within 2ms.

Note 18: 1-Wire communication should not take place for at least t_OSCWUP after V_PUP reaches V_PUP (min).

Impact:

To ensure reliable 1-Wire communication, 2ms should be awaited after power up before communicating with the DS28E54. The operation is similar, but the DS2431 does not have a t_OSCWUP parameter.

Action:

Verify that 1-Wire controller allows enough time before communicating with 1-Wire device. If needed, modify the application firmware to comply with this requirement.

5. Data Retention

Explanation:

This parameter specifies the time the contents of the memory is valid in the device after the last write cycle.

Note 17: Data retention is tested in compliance with JESD47H.

Impact:

The minimum data retention is reduced to 25 years at 85°C.

Action:

Verify the data retention requirements for a specific application and the temperature conditions.

6. Write/Erase Cycles

Explanation:

This parameter specifies the number of cycles the device memory can be written and erased, before the memory becomes unreliable.

Note 16: Write-cycle endurance is tested in compliance with JESD47H.

Impact:

The minimum write/erase cycles are reduced at 25°C. This can impact the application that requires more than 100,000 write/erase cycles.

Action:

Verify the write/erase cycle requirements for a specific application.

7. Input Load Current

Explanation:

This parameter specifies the current that the 1-Wire device draws when idle.

Impact:

For the DS28E54, the maximum input load current is increased to 20µA.

Action:

Ensure the elevated current draw does not adversely affect the system, especially one with many connected devices or if battery powered. In general, there is no impact on most of the systems, and no action is required.

8. Rising-Edge Hold-Off Time

Explanation:

This parameter specifies the time the device delays before detecting a low to high transition. This acts as a glitch filter.

Note 19: The earliest recognition of a negative edge is possible at t_REH after V_TH has been previously reached.

Impact:

The DS28E54 only specifies a typical value.

Action:

The DS2431’s filtering may be longer than the DS28E54’s time, so the system should be checked in its most electrically noisy environment to ensure proper operation.

Functional Compatibility

The DS28E54 has the reverse functional compatibility with the DS2431. It provides 5 pages of the DS2431/DS28E07 compatible memory and 6 pages for SHA3-256 operations. It implements the same commands available in the DS2431 and adds commands for SHA-3 secure authentication.

DS28E54 Security Features

The DS28E54 is used to add security features to the DS2431 design, and it is compatible with FIPS 202-Compliant SHA-3 Algorithm. The DS28E54 supports a challenge size of 256 bits and uses a 256-bit secret. Each 1-Wire peripheral has a unique 64-bit ROM ID, which serves as the node address in a 1-Wire network and is a fundamental input for authentication. The function commands for the DS28E54 include general memory read/write access, as well as security functions for peripheral authentication to the controller and controller authentication to the peripheral for write access. The memory is separated into pages of 32 bytes and allows the user to set protections on memory pages. It also includes a dedicated page used for the decrement counter.

Why Add Security to your Existing Design?

Adding security to a DS2431 existing design, implements advanced physical security using SHA-3 to provide a cost-effective IP protection, clone prevention, consumable verification, and peripheral authentication.

Counterfeit Prevention

Migrating the DS28E54 to a specific design enables the host system to test a sensor or module for authenticity and act if a counterfeit is detected. This can prevent counterfeit modules from being used with the system. The counterfeit products can also use the non-secure DS2431. To avoid this, it is possible to identify if a DS2431 or a DS28E54 is connected on the system bus by issuing a command not available in the DS2431, such as Read Status (0xAA).

Verify and Calibrate Consumable Items

Using the DS28E54 decrement counter is possible to provide quality control and verify if a consumable is used before and how many times. It can also provide a secure storage for calibration data used in consumable items.

Peripheral and Host Authentication

The DS28E54 can provide authentication to a host, as well as authenticating the peripherals attached. By using a challenge-and-response authentication, the host can verify if a peripheral is authentic based on a SHA-3 HMAC response as well as the peripheral can verify if a host is authentic.

If a secure host processing system is not available, the DS28E54 is compatible with the DS2477 secure coprocessor, which can offload the host processor from running SHA-3 operations, provide bi-directional authentication and a secure storage of the system keys.

License Management

For the designs that are licensed to third parties, the DS28E54 are used to store device settings and accessed via secure authentication. Only authorized third parties could read these settings, which prevents unauthorized use of intellectual property.

Conclusion

Careful examination can provide reliable migration between the two devices. The DS28E54 represents an improvement over the DS2431 while not only retaining pin and functional compatibility with DS2431's most popular packages, but by adding a layer of security implementing SHA-3 for secure authentication to an existing design.

References

For more information, refer to the DS28E54, DS2431, and DS2477 data sheet.