Single-Chip Digital Stereo Subsystem

The AD1859 offers the industry's most functionally complete 16/18-bit stereo digital audio playback subsystem on a single chip. It converts serial digital input data to filtered, buffered, low-distortion, gain-controlled stereo analog output. Its asynchronous master clock, a digital phase-locked loop (DPLL), allows it to accept data from a variety of sources, with clock rates from 28 kHz to 52 kHz (using an external 27-MHz crystal), rejecting sample-clock jitter and greatly simplifying interfacing.

It is ideal for many applications, including digital cable TV and direct broadcast satellite set-top decoder boxes, video CD players, CD-I players, high-definition televisions, digital audio broadcast receivers, digital audio workstations, multimedia computers, and all forms of CD and digital tape players.

The monolithic AD1859 comprises (Figure 1) a variable-rate oversampling digital interpolation filter, an innovative multibit sigma-delta [Σ-Δ] modulator with dither, a jitter-tolerant digital-to-analog converter (DAC), switched-capacitor and continuous-time analog filters, and analog output drive circuitry as well as an on-chip dc voltage reference housed in a 28-lead SOIC or SSOP package. The on-chip volume controls (a system cost saving) include a stereo attenuator and mute, programmed entirely through an SPI†-compatible serial control port.

SPI is a registered trademark of Motorola, Inc.

Figure 1
Figure 1

A typical application where the AD1859 offers especial advantages, MPEG audio, calls out a requirement for three different sample rates: 32-, 44.1-, and 48 kHz. With a typical sigma-delta audio DAC, the designer would have to provide an external clock circuit to synthesize the "master clock" associated with each of these three sample frequencies. With the AD1859 the first audio DAC to have an asynchronous master clock this task is simplified. All that is needed is a 27-MHz clock (furnished externally or generated on-chip using an external 27-MHz crystal); the AD1859's phase-locked loop automatically adapts to different incoming sample rates a major system cost saving. The DPLL will lock to any new sample rate (applied to the Left-Right clock pin) within 100 to 200ms; jitter components more than 15Hz above and below the sample frequency are rejected at 6dB per octave (e.g., jitter at 150Hz above or below the sample rate is reduced by 20dB).

Guaranteed performance characteristics include minimum dynamic range of 88dB with an A-weight filter (85.7dB without filter), and maximum total harmonic distortion & noise (THD+N) of -84dB (0.0063%) over the audio band, 20 Hz to 20 kHz. Figure 2 is a typical plot of THD+N vs. frequency at -0.5-dBFS amplitude. Figure 3 is an FFT of a -90-dB, 1-kHz tone, accompanied by a time-domain plot, demonstrating the freedom from harmonics, spurs, and quantization effects at this low level, typical of analog systems but hard to achieve digitally.

Figure 2
Figure 2

Another feature uniquely available with the AD1859 is an innovative multibit sigma-delta modulator (see sidebar), that helps to reject clock jitter a system audibility advantage and reduces out-of-band energy, a system cost saving.

Figure 3
Figure 3

Interface to the AD1859 is simple via a flexible serial data input port that allows for glueless interconnection to a variety of ADCs, DSPs, AES/EBU receivers, and sample-rate converters. The versatile serial data input port can be configured for left-justified, I2S-justified, right-justified, and DSP serial port compatible modes. The chip accepts 16 or 18-bit audio data in MSB-first, twos-complement format. The AD1859 supports continuously variable sample rates and with essentially linear (to within ±0.1%) phase response. De-emphasis is optionally available at the analog output stage, achieving improved, sample-rate invariant, noise reduction with the addition of just a few external components. (Figure 4)

Figure 4
Figure 4

A power-down mode (48mW vs. 330mW) minimizes power consumption when the device is inactive. The entire stereo digital audio playback subsystem operates from a single +5-V supply over the temperature range -40°C to +105°C; it is packaged in 28-pin SOIC and SSOP.

Keys to the AD1859's Performance

The AD1859 offers superb fidelity and low-level linearity, greatly reduces circuit complexity, can be interfaced easily to DSPs (digital signal processors) and ADCs (analog-to-digital converters), and cuts the power consumption and cost of digital audio playback systems.

It has two key differentiating features from conventional devices. First is its unique DPLL (digital phase-locked loop) clock manager. This is an asynchronous sample-rate manager that automatically adjusts to incoming sample frequencies and allows the AD1859 to be clocked by a different frequency from its own master clock. It is based on patented asynchronous sample-rate conversion technology developed at Analog Devices (Analog Dialogue 28-1, 1994, pp. 9-11). Until now, no other audio DAC has had this capability. Other audio DACs (digital-to-analog converters) require a well-tuned, high-frequency master clock that runs at 256 or 384 times the intended audio sample rate. The generation and management of this high-frequency synchronous clock is burdensome to the board-level designer.

An external asynchronous clock oscillator may be used to furnish the AD1859's master clock; however, the AD1859 includes an on-chip oscillator, so the designer need only provide an inexpensive quartz crystal or ceramic resonator as the external time base. The AD1859's on-board DPLL will lock to any incoming sample rate between 1/512 and 1/1024 of its master clock frequency in about 100 ms. Jitter on the crystal time base or MCLK input is rejected (by virtue of an on-chip switched-capacitor filter), as well as jitter on the incoming LRCLK input to a level unprecedented in audio DACs.

The second differentiating feature of the AD1859 is its patented multibit sigma-delta modulator, which results in dramatically less out-of-band noise energy than competitive ICs. Lower out-of-band noise energy reduces the need for post-DAC filtering, so that all the necessary post-DAC filtering (except for optional analog de-emphasis) is integrated on chip. Another attribute of the multibit Σ-Δ modulator is its high immunity to digital substrate noise, further improving audio signal integrity.

What is a multibit sigma-delta modulator? In an elementary approach, typical sigma-delta modulators have two levels of quantization, and DACs must average pulsewidth-modulated full-scale square waves; but in the case of the AD1859, 17 levels of quantization are used, and the input to the averaging filter can be thought of as the much easier task of smoothing the 1/16th-full-scale elements of a 17-level staircase. In addition, the AD1859 samples the input signal at 128 times the input sample rate, double the conventional rate. The additional quantization levels and higher oversampling ratio means that the output spectrum contains dramatically lower levels of out-of-band noise energy; permitting a much simpler post-DAC reconstruction filter. Its reduced transition-band steepness and attenuation requirements result in lower phase distortion and improved fidelity.

Is there a downside? The problem that conventionally limits the performance of multibit Σ-Δ converters is the nonlinearity of the passive circuit elements used to sum the quantization levels. The designers have invented a revolutionary architecture that overcomes the problem1.

Other interesting features of the chip include the use of a dither with a triangular probability distribution function to further reduce quantization noise; and on-chip low-pass filtering consisting of a 2nd-order switched-capacitor filter, followed by a first-order analog continuous-time filter. In addition to filtering out noise, it reduces the effects of any residual master-clock jitter.

The AD1859 was designed in Wilmington, MA, by Bob Adams, Tom Kwan, and Bob Libert, of our Computer Products Division.


1See "A stereo multi-bit Σ-Δ DAC with asynchronous master-clock interface", by Tom Kwan, Bob Adams, and Bob Libert, 1996 IEEE International Solid-State Circuits Conference Record.



Pete Predella