1. Data Sheet Errata

Documentation Errata for ADSP-CM41x Mixed-Signal Control Processor with ARM Cortex-M4/ARM Cortex-M0 and 16-bit ADCs Hardware Reference

Chapter: 24 / Page 84

Doc ID: DOC-1763

Change

For the PWM_CHANCFG Configuration registers, the timer options are:

  • PWMAH \ AL – Timer 0 & Timer 1
  • PWMBH \ BL – Timer 0 & Timer 2
  • PWMCH \ CL – Timer 0 & Timer 3
  • PWMDH \ DL – Timer 0 & Timer 4

In the Table

For PWM_CHANCFG.REFTMRD, the bit description should be:

The PWM_CHANCFG.REFTMRD bit selects whether the PWM uses PWMTMR0 or PWMTMR4 as the reference timer for Channel D operation.

The enumerations description should be:

0 = PWMTMR0 is Channel D reference

1 = PWMTMR4 is Channel D reference


For PWM_CHANCFG.REFTMRC, the bit description should be:

The PWM_CHANCFG.REFTMRC bit selects whether the PWM uses PWMTMR0 or PWMTMR3 as the reference timer for Channel C operation.

The enumerations description should be:

0 = PWMTMR0 is Channel C reference

1 = PWMTMR3 is Channel C reference


For PWM_CHANCFG.REFTMRB, the bit description should be:

The PWM_CHANCFG.REFTMRB bit selects whether the PWM uses PWMTMR0 or PWMTMR2 as the reference timer for Channel B operation.

The enumerations description should be:

0 = PWMTMR0 is Channel B reference

1 = PWMTMR2 is Channel B reference


Last Update Date: 2019-01-08