ADSP-BF60x PORT 349-Ball CSP_BGA GP I/O Multiplexing

Doc ID: DOC-1760

Change

For the PWM_CHANCFG Configuration registers, the timer options are:

• PWMAH \ AL – Timer 0 & Timer 1
• PWMBH \ BL – Timer 0 & Timer 2
• PWMCH \ CL – Timer 0 & Timer 3
• PWMDH \ DL – Timer 0 & Timer 4

In the Table:

For PWM_CHANCFG.REFTMRD, the bit description should be:

The PWM_CHANCFG.REFTMRD bit selects whether the PWM uses PWMTMR0 or PWMTMR4 as the reference timer for Channel D operation.

The enumerations description should be:

0 = PWMTMR0 is Channel D reference

1 = PWMTMR4 is Channel D reference

For PWM_CHANCFG.REFTMRC, the bit description should be:

The PWM_CHANCFG.REFTMRC bit selects whether the PWM uses PWMTMR0 or PWMTMR3 as the reference timer for Channel C operation.

The enumerations description should be:

0 = PWMTMR0 is Channel C reference

1 = PWMTMR3 is Channel C reference

For PWM_CHANCFG.REFTMRB, the bit description should be:

The PWM_CHANCFG.REFTMRB bit selects whether the PWM uses PWMTMR0 or PWMTMR2 as the reference timer for Channel B operation.

The enumerations description should be:

0 = PWMTMR0 is Channel B reference

1 = PWMTMR2 is Channel B reference

Doc ID: DOC-1405

Change

There is a bit description missing in table 22-75, USB_PHY_CTL Register Fields. This is bit 4 (DIS) which has the following description.

DIS, Disable PHY

0 - USB PHY and 5V protection on USB signals enabled.
1 - USB PHY and 5V protection on USB signals disabled. Disabling the PHY and 5V protection results in reduced hibernate current.

CAUTION- With 5V protection disabled the absolute max voltage on USB signals is reduced. See the data sheet for details.

Doc ID: DOC-1465

Change

In Table 23-27, Destination Address Filtering, the column labeled HMC contains the DAIF settings, and the column labeled DAIF contains the HMC settings. Using incorrect settings can cause address filtering failures.

Doc ID: DOC-1418

Change

In the description of the Back Off Limit (EMAC_MACCFG.BL) bit, "4,096 bit times for 1000 Mbps" should be removed because the BF60x EMAC supports only 10/100Mbps operation.

Doc ID: DOC-1478

Change

The title of Table 30-21 is incorrect. The correct title is YCbCr 4:2:2 16-Bit Type 1 (CrYCbY) with 10 to 16 Bits per PIXCLK (not UCbCr).

Doc ID: DOC-1483

Change

On page 30-35, in the section "OPFn Data Packing" (second paragraph, first sentence), the text should change from:

The PVP_OPFn_CTL.OSIZE=0 setting instructs the OPFn block to accept a full 32-bit word from the data source.

Change to:

The PVP_OPFn_CTL.ISIZE=0 setting instructs the OPFn block to accept a full 32-bit word from the data source.

Doc ID: DOC-1485

Change

The statement "The CNVn block supports down scaling by dropping output pixels in both directions. The PVP_CNVn_SCALE bits are used to set the horizontal downscale factor, and the PVP_CNVn_SCALE.VSCL bits are used to set the vertical downscale factor." contains an error. The horizontal downscale factor is set using PVP_CNVn_SCALE.HSCL bits, not PVP_CNVn_SCALE bits.

Doc ID: DOC-1444

Change

In Table 30-47, the description of Continuous Frame mode incorrectly states: Processing Blocks do not auto-disable. New Configuration must not set PVP_xxx_ CFG.START bit of any block again.

The correct information is: Only IPFn blocks auto-disable, other processing blocks do not. A new configuration needs to reset START bit of IPFn, but must not set the START bit of the other blocks. Ideally, writes to PVP_xxx_CFG registers of PVP blocks other than IPFn are avoided altogether.

Note: This behavior is the same as for Back-to-Back mode.

Doc ID: DOC-1439

Change

In figure 30-70 (BSL Example), the figure incorrectly shows the THC1 block status header located in the block status list before the THC0 block status header and the THC0 status words.

The correct location of the THC1 block status header in the block status list is after the THC0 block status header and the THC0 status words.

Doc ID: DOC-1477

Change

In Frame Sync Polarity and Sampling Edge, the title and leftmost column of Table 31-8 are incorrect. The corrected table is as follows:

Table 31-8: Clock Polarity Selections and Receive/Transmit Pin States

Bit Setting	Receive		Transmit
	Sample Data	Sample/Drive Syncs	Drive Data	Sample/Drive Syncs
POLC = b#00	Falling edge	Falling edge	Rising edge	Rising edge
POLC = b#01	Falling edge	Rising edge	Rising edge	Falling edge
POLC = b#10	Rising edge	Falling edge	Falling edge	Rising edge
POLC = b#11	Rising edge	Rising edge	Falling edge	Falling edge

Doc ID: DOC-1406

Change

The following formula for calculating the EPPI clock is incorrect:
PPI_CLK = (SCLK) / (2 * (EPPI_CLKDIV + 1))

The correct formula for calculating the EPPI clock is:
PPI_CLK = SCLK/(EPPI_CLKDIV + 1)

Doc ID: DOC-1443

Change

The following equation is incorrect:

PPI_CLK = ( SCLK ) / ( 2 * ( EPPI_CLKDIV + 1 ) )

The correct equation is:

fPCLK = fSCLK / ( EPPI_CLKIV + 1 )

where:

• fPCLK is the frequency of the internally generated EPPI clock.
• fSCLK is the frequency of SCLK.
• EPPI_CLKDIV is the value programmed for clock division in the EPPI_CLKDIV register.

Doc ID: DOC-1469

Change

Figure 35-7 and Table 35-7 describe bit 3 in the SDU_STAT register as toggling Secure mode. This information is incorrect. Bit 3 is reserved in ADSP-BF60x processors.

Last Update Date: 2018-05-07