1. Data Sheet Errata

Documentation Errata

Chapter: / Page 24

Doc ID: DOC-1787

Change

In Table 11, ADSP-SC57x/ADSP-2157x Detailed Signal Descriptions, the direction of the C1_FLG[n] and C2_FLG[n] pins is incorrect.

The correct direction for both pins is InOut.

Chapter: / Page 57

Doc ID: DOC-1780

Change

In the second row of Table 26, TWI_VSEL Selections and VDD_EXT/VBUSTWI, the TWI_VSEL selection should be TWI111, not TWI100.

Table 26 should also include the following footnote:

TWI_VSEL is the TWI voltage select field in the PADS_PCFG0 register. See the ADSP-SC57x/ADSP-2157x SHARC+ Processor Hardware Reference.


Last Update Date: 2019-01-22