Documentation Errata for ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference (Rev 1.0)
Doc ID: DOC-1922
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TMU Calibration
Calibration setting are comprised of gain and offset settings. These settings must be programmed into the corresponding device registers before the temperature is read from the TMU temperature value register. The calibration setting ensures that the reported temperature approximates the actual die temperature (within the error specified in the data sheet). The specified accuracy of the reported temperature cannot be met if gain and offset settings are not used.
The TMU configuration software programs gain and offset values as part of the TMU initialization process. The gain value is programmed in the TMU_GAIN.VALUE field. The offset value is programmed in the TMU_OFFSET.VALUE bit field.
The TMU Calibration Settings table provides the calibration setting for the processor. After these registers are programmed, the rest of the TMU initialization can take place. This includes setting up the fault and alert limits and then enabling the TMU.
| Bit Field | Programmed Value |
|---|---|
| TMU_GAIN.VALUE | 0xE7 |
| TMU_OFFSET.VALUE | 0x5C0 |
NOTE::Refer to the product data sheet for the expected TMU accuracy achieved using the settings.
NOTE: The calibration settings provide expected TMU performance at temperatures above room temperature. The accuracy is not guaranteed for temperatures below room temperature.
Doc ID: DOC-1788
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The SWU_CTLx.LCMPEN bit is not applicable for the ADSP-SC58x/2158x processors.
Doc ID: DOC-1794
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PROBLEM: The CGU_PLLCTL bit descriptions need clarification. The CGU_PLLCTL bits are W1C (write one to action) which implies that software must write '1' to each of the conditions at a time. However, to verify that the action is completed and successful, it has to verify the corresponding bits in the CGU_STAT register (PLLEN and PLLBP bits).
SOLUTION: Check the corresponding bits in the CGU_STAT register to verify that the action is complete. The updated descriptions are shown below.
| Bit No. | Bit Name | Bit Description |
|---|---|---|
| 3 | PLLEN | Setting (=1) the CGU_PLLCTL.PLLEN bit enables the PLL. Check the CGU_STAT.PLLEN bit to verify that the action is complete. |
| 2 | PLLDIS | Setting (=1) the CGU_PLLCTL.PLLDIS bit disables the PLL. Check the CGU_STAT.PLLEN bit to verify that the action is complete. |
| 1 | PLLBPCL | Setting (=1) the CGU_PLLCTL.PLLBPCL bit takes the PLL out of bypass mode. Check the CGU_STAT.PLLBP bit to verify that the action is complete. |
| 0 | PLLBPST | Setting (=1) the CGU_PLLCTL.PLLBPST bit bypasses the PLL and all the clocks run on CLKIN. Check the CGU_STAT.PLLBP bit to verify that the action is complete. |
Doc ID: DOC-1745
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Step 6 in the System Interrupt Flow procedure is incorrect.
Current:
The SEC compares the SEC_CPND[n](B) register value to the SEC_CACT[n](A) register value. If the SEC_CACT[n] (A) register value is a higher priority, continue.
Change to:
The SEC compares the SEC_CPND[n](B) register value to the SEC_CACT[n](A) register value. If the SEC_CPND[n](B) register value is a higher priority, continue.
Doc ID: DOC-1962
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Swapping of Data Bits
To simplify routing, entire byte lanes can be swapped, but it should be ensured that all DQ , DQS, and DM signals are substituted with each other (for example, DQ (7-0) with DMC_UDM). Within a byte lane, data bits can also be swapped.
Doc ID: DOC-1965
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PROBLEM:In the "DMC Initialization Flow" chart, the write to DMCx_DLLCTL register with value 0x948 operation should be done before setting the DMC_CTL.INIT bit. Currently, the flow chart suggests to program this register after DMCx_STAT.INITDONE bit is set.
CORRECTION:In the " DMC Initialization Flow" chart, the rectangle with text " PROGRAM THE DMCx_CTL.DLLCTL BIT FIELD = 0x948 (DATACYC=9, DLLCALRDCNT=72)" should be before/above the rectangle with the text "PROGRAM THE DMCx_CTL REGISTER WITH INIT BIT SET TO START THE DMC INITIALIZATION SEQUENCE". Insert the step "Program the DMCx_.DLLCTL register with the value 0x948 (DATACYC=9, DLLCALRDCNT=72)" between step no. 5 and 6.
Doc ID: DOC-1756
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Doc ID: DOC-1964
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The DMC_CAL_PADCTL0.CALSTRT bit is not self-clearing. The description of the bit should be: Start New Calibration.
Doc ID: DOC-1815
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Fix typo in EPPI topic
In the following line in step 1 of the "Configuring Transfers in GP 2 FS Mode" topic, GP 0 should be changed to GP2.
INCORRECT: Configure the EPPI to operate in GP 0 FS mode by setting EPPI_CTL.XFRTYPE bit =b#11 and the EPPI_CTL.FSCFG bit =b#10.
CORRECT: Configure the EPPI to operate in GP 2 FS mode by setting EPPI_CTL.XFRTYPE bit =b#11 and the EPPI_CTL.FSCFG bit =b#10.
Doc ID: DOC-1761
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For the PWM_CHANCFG Configuration registers, the timer options are:
- PWMAH \ AL – Timer 0 & Timer 1
- PWMBH \ BL – Timer 0 & Timer 2
- PWMCH \ CL – Timer 0 & Timer 3
- PWMDH \ DL – Timer 0 & Timer 4
In Table 18-7:
For PWM_CHANCFG.REFTMRD, the bit description should be:
The PWM_CHANCFG.REFTMRD bit selects whether the PWM uses PWMTMR0 or PWMTMR4 as the reference timer for Channel D operation.
The enumerations description should be:
0 = PWMTMR0 is Channel D reference
1 = PWMTMR4 is Channel D reference
For PWM_CHANCFG.REFTMRC, the bit description should be:
The PWM_CHANCFG.REFTMRC bit selects whether the PWM uses PWMTMR0 or PWMTMR3 as the reference timer for Channel C operation.
The enumerations description should be:
0 = PWMTMR0 is Channel C reference
1 = PWMTMR3 is Channel C reference
For PWM_CHANCFG.REFTMRB, the bit description should be:
The PWM_CHANCFG.REFTMRB bit selects whether the PWM uses PWMTMR0 or PWMTMR2 as the reference timer for Channel B operation.
The enumerations description should be:
0 = PWMTMR0 is Channel B reference
1 = PWMTMR2 is Channel B reference
Doc ID: DOC-1837
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PROBLEM:The TWI_MSTRSTAT.BUFRDERR bit description is unclear.
SOLUTION:The TWI_MSTRSTAT.BUFRDERR bit description is as follows:
The TWI_MSTRSTAT.BUFRDERR bit indicates whether the current requester transfer was aborted due to a transmit buffer read error. The error occurs when the buffer is empty and data is required by the transmit shift register. This bit is W1C.
0 - The current master transmit has not detected a buffer read error.
1 - The current master transfer was aborted due to a transmit buffer read error. At the time data was required by the transmit shift register the buffer was empty. This bit is cleared by writing a one to its bit location.
Doc ID: DOC-1773
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Ignore the note in the Cross Mode Connections topic on Page 9:
Doc ID: DOC-1963
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NOTE:
In TDM mode, the ASRC drives at the rising edge and samples at the falling edge of serial clock. In all other modes, serial clock rising edge is the sampling edge, and the falling edge is the driving edge.
Doc ID: DOC-1825
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Typos in ASRC Functional Description topic:
INCORRECT: (two occurances): the sample rate converter interpolates the serial input data at a rate of 220; a 64-tap FIR filter with 220 polyphases
CORRECT: the sample rate converter interpolates the serial input data at a rate of 220 .
CORRECT: a 64-tap FIR filter with 220 polyphases
Doc ID: DOC-1819
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PROBLEM: Incorrect decimation rate is shown in the Digital Filter Group Delay subtopic.
CORRECTION: The decimation rate is calculated using the following formula RAM word: depth = (512 - 16) ÷ 64 taps = 7.75.
Doc ID: DOC-1804
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In the table "SPI Master Boot BCODE Descriptions", the SPI Clock references are SCLK1.
Doc ID: DOC-1973
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There is a mismatch between the DAI/SRU MMR Register Addresses table (Reset Values column) in the manual versus the actual reset values.
CORRECTION:The reset values are:
| Register Name | Reset Value |
|---|---|
| DAI0_CLK2 | 0x3DEF7BDE |
| DAI0_CLK3 | 0x3DEF7BDE |
| DAI0_CLK4 | 0x3DEF7BDE |
| DAI0_FS2 | 0x3DEF7BDE | DAI1_CLK2 | 0x3DEF7BDE |
| DAI1_CLK3 | 0x3DEF7BDE |
| DAI1_CLK4 | 0x3DEF7BDE |
| DAI1_FS2 | 0x3DEF7BDE |
Last Update Date: 2025-01-09