Magnifying Glass Icon close icon

You searched for “RapidNet-IP”

Filters

Filter Icon

Filters

Expand or Collapse Filter Icon
Expand or Collapse Filter Icon
Result Type
  • 97
  • 17
  • 1,643
  • 9,197
  • 3,710
  • 11
  • 8
Expand or Collapse Filter Icon
Groups, Forums & Libraries
  • 65
  • 275
  • 106
  • 245
  • 100
  • 75
  • 71
  • 104
Expand or Collapse Filter Icon
Author
  • 71
  • 1,819
  • 38
  • 305
  • 45
  • 43
  • 66
  • 63
Expand or Collapse Filter Icon
Tag
  • 1,253
  • 1,244
  • 648
  • 611
  • 401
  • 328
  • 303
  • 298

Results on Analog.com

0
External Link Icon Right Arrow Icon External Link Icon External Link Icon Tag
We're sorry, but we couldn't find any results for your search. Please try again with a different search term and/or changing your filter criteria.
  • <<
  • <
  • 1
  • >
  • >>

Results on EngineerZone

14,683
    Clear All Filters Icon

    1. AXI_ad9361 IP BLOCK Register Address Map

      Forum Thread
      Answered
      FPGA Reference Designs
      25 April, 2025
      I am looking at the AXI_AD9361 Register Map and I can see the addresses for ADC and DAC Common in 4 byte increments start at and . Now if I go to DAC Common and look at the REG_RSTN which is DAC Interface Control & Status, it states the address …
      Datasheet/Specsplutosdrfpga designno-Os_ad9361axi_ad9361pluto

    2. MATLAB Generated IP (DUT) integrated in reference design for streaming out data

      Forum Thread
      Answered
      FPGA Reference Designs
      17 April, 2025
      ADI team, I want to process the digital samples using HDL reference design and then analyse these in MATLAB. My question is do ADI provide some example (HDL Coder or MATLAB) where I can generate complete reference design from HDL coder having integrated DUT IP responsible for pushing samples to …
      ADRV9361-Z7035 / ARDV1-CRR-BOBadrv9361-z7035softwaread9361 z7035ad9361matlabWideband Transceiver ICRF Integrated Transceivers

    3. Customize AXI-ADC9361 IP for Versal AI Edge device (AMD SoC)

      Forum Thread
      Answered
      FPGA Reference Designs
      07 April, 2025
      … meta-adi/blob/main/meta-adi-xilinx/README.md While adapting the reference design for our Versal SoC, we observed that the AXI_AD9361 Custom IP does not support the Versal AI Edge XCVE2302 Device. Could you please suggest a workaround or modifications to enable AXI_AD9361 IP support for …
      softwaread9361Wideband Transceiver ICRF Integrated Transceivers

    4. PYNQ-Z2: Issues with PMOD AD1 and FFT IP Implementation

      Forum Thread
      Answered
      FPGA Reference Designs
      02 April, 2025
      Hello. Currently, I am using Vivado 2023.1 and working with the PYNQ-Z2 board. My ultimate goal is to use the PMOD AD1 to sense voltage and perform frequency detection using an FFT IP. To explain in detail, I connect the output voltage of a buck converter to …
      adchardwarepynq z2ffthwverilogvivadopmodpmod ad1fpga

    5. Change parameters of custom IP core without regenerating bitstream

      Forum Thread
      Answered
      FPGA Reference Designs
      18 March, 2025
      Hello! In this question I asked about custom IP core Continuous stream of processed data to PC host for ZC706+ADRV9009 (EVAL-TPG-ZYNQ3) .I implemented my own IP core and now I want to change its parameters without regenerating bitstream and rewriting BOOT.bin. My idea is using python …
      analogdevicesinc HDL2023_R2softwareadrv9009Wideband Transceiver ICADRV9009+ZC706(EVAL-TPG-ZYNQ3)RF Integrated Transceivers

    6. zcu102 adrv9009 IPs not work on zcu11eg

      Forum Thread
      Answered
      FPGA Reference Designs
      14 March, 2025
      … I review the memory map and find the memory of the IPs ， ， ，are all zeroes. If I used the orignal zcu9eg(ZCU102) + adrv9009 , the app worked fine and the memory are not all zeroes. I have no idea how to make the IPs work on zcu11eg as well as zcu9eg?
      hardwarezcu102adrv9009Wideband Transceiver ICRF Integrated Transceivers

    7. ADRV9361Z7035 Reference Design is not working with my IP

      Forum Thread
      Answered
      FPGA Reference Designs
      24 February, 2025
      Hello everyone! I wrote an IP for demodulating signals that modulated with QPSK modulation. I used it on fmcomms2 project on ZCU102 and I successfully processed signal. And now, I am trying to run same IP on ADRV9361Z7035-SOM (LVDS Mode) + ADRV1CRR-BOB by using releated HDL project. I am …
      hardwaread9361ADRV936xWideband Transceiver ICsignalRF Integrated Transceivers

    8. Missing VLNV for AD3552r IP Cell

      Forum Thread
      Answered
      FPGA Reference Designs
      18 February, 2025
      … cell -type ip -name axi_ad3552r_0 . ERROR: [Common 17-39] 'create_bd_cell' failed due to earlier errors. while executing "create_bd_cell -type ip -vlnv [get_ipdefs -all -filter "VLNV =~ *:${i_ip}:* && design_tool_contexts =~ *IPI* && UPGRADE_VERSIONS == \"\""] ${i_name}" (procedure "ad_ip_instance" line 3 …
      AD3552RUbuntu 20.4MATLAB R2023bsoftwareHigh Speed D/A Converters =30MSPSVivado 2023.1Fast Precision D/A ConvertersPrecision Toolbox

    9. HDL Code Help - AD CN0585 IP in Vivado

      Forum Thread
      Answered
      FPGA Reference Designs
      05 February, 2025
      … the CN0585 uses two AD3552rs) but am unsure if this is due to another error. I also tried to follow the page on getting ADI IP Cores in Vivado such that I can select the CN0585 as a reference design in Simulink/HDL Coder but am not allowed to select …
      AD3552Rhdl reference designsoftwareCN0585High Speed D/A Converters =30MSPSFast Precision D/A Converters

    10. Differences in Altera vs Xilinx adrv9001 FPGA IP? (2022_r2_p1)

      Forum Thread
      Answered
      FPGA Reference Designs
      27 November, 2024
      I was examining FPGA code for the adrv9001 FPGA Receiver IP and saw that there were differences in the way the implementation was done for a Zynq vs AlteraSoC FPGA. In the Xilinx Implementation, a Serdes IP is instantiated and used. It looks to me like only double-data-rate …
      hardwareWideband Transceiver ICRF Integrated Transceivers