ADISIMCLK™ DESIGN AND EVALUATION SOFTWARE

ADIsimCLK

Introducing ADIsimCLK Version 1.2
Updated July 2007

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Once the zip file has been stored locally, it can be extracted and run by clicking on "setup.exe". Version 1.2 is the current up-to-date version.

Please note: Any old versions should be uninstalled before installing the latest version.

ADIsimCLK is the design tool developed specifically for Analog Devices' range of ultra-low jitter clock distribution and clock generation products. Whether your application is in wireless infrastructure, instrumentation, networking, broadband, ATE or other areas demanding predictable clock performance, ADIsimCLK will enable you to rapidly develop, evaluate and optimize your design.

With the release of version 1.2, models are now available for the AD9516-x, AD9517-x and AD9518-x families of multi-output clock generators with integrated VCOs. In addition to standard ADIsimCLK options, the AD9516/17/18 models offer a new PLL lock detect mode: digital lock detect driving a current source, passed through an analog filter. All models in ADIsimCLK version 1.2 benefit from tool enhancements which include: user-friendly VCO/VCXO/TCXO library editor, expanded options for clock distribution mode configuration, improved phase noise plots, new tabular display for phase noise at user selectable offset frequencies, and a fast 32-bit installation program. Users of the AD9510 and AD9511 will also notice a new configuration in which a distribution channel may be placed in the PLL feedback path.

ADIsimCLK is a highly successful tool for predicting phase noise and jitter for ADI clock products. Features include:

  • jitter performance - broadband and SONET specifications
  • phase noise performance
  • phase noise impact - ACI/ACR, EVM, phase jitter etc.
  • jitter impact on ADC performance - SNR, ENOB
  • accurate timing analysis (logic analyzer display)

ADIsimCLK models PLL frequency synthesizers + external VCOs, as well as integrated PLL/VCOs. Analysis includes:

  • phase noise analysis including reference, VCO, loop filter and phase detector contributions
  • non-linear transient analysis - for accurate determination of lock time.

ADIsimCLK is extremely user friendly and easy to use. The ADIsimCLK wizard enables the designer to observe detailed performance data for a 'simulated' clock distribution design within minutes. Optimization of the clock circuit can be accomplished in this interactive environment with spreadsheet-like simplicity and interactivity. Contrary to the traditional methods where to design, build and then measure parameters takes days, ADIsimCLK enables the user to change the circuit design and observe immediate performance changes.

In summary, ADIsimCLK allows the designer to work at a higher level and directly modify parameters such as the loop bandwidth, divide ratios, phase offsets, output frequencies, and the effects of the changes on performance are shown instantly (and without burning fingers with a soldering iron!). With traditional design techniques, the evaluation of new devices requires construction, measurement and hand optimization of a prototype, which is a significant barrier to change and is often a key reason for the continual use of 'old' clock distribution chips.

ADIsimCLK comes with links to online device data for the Analog Devices range of clock products. We encourage you to visit www.analog.com/clock-timing regularly to obtain information on new releases and recent product information. The Analog Devices website may be reached at any time from the help menu.

Download Now: The ADIsimCLK™ Software can be downloaded for free.

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