Volume 35, Number 6, November-December, 2001
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Design a Direct 6-GHz Local Oscillator with a New, Wideband, Integer-N, PLL Synthesizer
Figure 1. Functional block diagram of the ADF4106
The ADF4106 frequency synthesizer (Figure 1) can be used to implement local oscillators (LOs) in the up- and down-conversion sections of wireless receivers and transmitters. It consists of a low-noise digital phase-frequency detector (PFD), a precision charge pump, a programmable reference divider, programmable A and B counters and a dual-modulus prescaler (P/P+1). The A (6-bit) and B (13-bit) counters, in conjunction with the dual-modulus prescaler (P/P+1), implement an N-divider (N = BP+A). In addition, the 14-bit reference (R) counter, allows selectable REFIN frequencies at the PFD input. A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and voltage-controlled oscillator (VCO). Its very high bandwidth means that frequency doublers can be eliminated in many high-frequency systems, simplifying system architecture and lowering cost.
Figure 2. Standard PLL architecture
The standard PLL system architecture, used by the ADF4106and its predecessor, the ADF4113is shown in Figure 2. Since the maximum operating frequency of the ADF4113 is about 4 GHz, higher frequencies require the use of a frequency doublerwhich usually calls for an extra RF amplifier to produce an adequate level for the doubler. Use of the ADF4106 eliminates the frequency doubler and its associated circuitry, achieving a much simpler and more power-efficient LO. For example, the design shown in Figure 3 generates RF output frequencies, with 1-MHz channel separation, from 5.4 GHz up to 6.0 GHz. The phase noise measured at the upper end was -83 dBc/Hz.
Figure 3. The ADF4106 used to implement a 6.0-GHz local oscillator.
Because the input impedance of the ADF4106 at this high operating frequency is very close to 50 ohms, a 50-ohm terminating resistor at the RF input is not needed for maximum power transfer efficiency. When operating at lower frequencies, the s-parameters in the data sheet give the impedance values needed for matching.
The ADF4106, in conjunction with a wide-bandwidth divider, can improve the phase noise and lock time of a standard local oscillator circuit at frequencies below 2.0 GHz.
A typical wireless system might be generating frequencies in 200-kHz increments from 1450 MHz to 1500 MHz. Using an integer-N architecture to do this, a phase/frequency-detector reference frequency of 200 kHz is needed, and the N value would vary from 7250 (1450 MHz) to 7500 (1500 MHz).
Using the ADF4106 for best performance would give a phase noise figure of 88 dBc/Hz. Typical reference spurs in such a system would be 88 dBc at 200 kHz and 90 dBc at 400 kHz. Implementing a loop bandwidth of 20 kHz, typical lock time to 10 degrees of phase error would be 250 µs.
Figure 4a. Architecture for improved lock time, phase noise and reference spurs.
However, the wideband operation possible with the ADF4106 allows an alternative architecture to be considered, shown in Figure 4a. In this configuration, the core PLL is operated at a multiple of the final desired output frequency. In the example given above, the final desired frequency range is 1450 MHz to 1500 MHz. A multiple within the device's frequency range is 5800 MHz to 6000 MHz (4 times the desired output band). In the proposed scheme, shown in Figure 4a, FPFD operates at 800 kHz, the FVCO band is 5800 MHz to 6000 MHz, and the final system LO output is obtained by dividing FVCO by 4.
FOUT = (FPFD × N)/X
Some consequences of using this architecture are outlined below.
Phase-noise reduction [See discussion below]
Figure 4b. Comparing the output spectrum at FVCO and FOUT of Figure 4a.
So, using the architecture of Figure 4a with X = 4, and generating an FOUT of 1450 MHz to 1500 MHz with 200-kHz spacing, the frequency spurs will exist at integer multiples of 800 kHz, the PFD frequency, at levels below 90 dBc. Note, although the step frequency is 200 kHz, the lowest frequency spur is at 800 kHz.
Shorter lock time
The actual implementation of Figure 4a is shown in Figure 5.
Figure 5. Using the ADF4106 with an output divider to generate a 1.5-GHz local oscillator.
To summarize, the circuit of Figure 5 provides the following performance:
The price of this improved performance is the extra cost of the output divider and the extra power consumption of the system as a whole (the HMC typically adds 68 mA to the ADF4106's 13-mA current requirement). So improved performance must be a critical requirement for going with this architecture. The extra board space needed for implementation is minimal, since the HMC comes in an 8-lead SOIC package.
Figure 6. ADF4106 sensitivity vs. frequency.
Figure 7. Basic phase-locked-loop model.
The circuit of Figure 7 will be used as the circuit model for the discussion of phase noise.
Total phase noise in a phase-locked loop (dB) can be expressed as follows:
PNTOTAL = PNSYNTH + 20 logN + 10 logFPFD
Figure 8. ADF4106 phase noise vs. PFD frequency.
With a given measured total noise, synthesizer noise can be inferred as:
PN SYNTH = PN TOTAL 20 logN 10 logFPFD
This provides a figure of merit for the PLL Synthesizer circuit itself, irrespective of the noise contributed by PLL N value and PFD frequency, since these would be the same for any similar circuit being compared. For the ADF4106, this figure comes out to 219 dBc/Hza 3-dB improvement on the ADF4113, which had been the best available integer-N synthesizer in terms of phase noise.
With this phase-noise figure of merit, an engineer can work out the total PLL phase noise for any given PFD frequency and RF output frequency. For example, consider generation of a local oscillator signal with frequencies from 1700 MHz to 1800 MHz and channel spacing of 200 kHz. Using equation (2), the close-in phase noise using the ADF4106 as the PLL synthesizer is
Figure 8 shows that the ADF4106 obeys the 10 logFPFD "rule" (PFD phase noise substantially linear with log frequency) fairly consistently all the way to 30 MHz. Some integer-N devices begin to degrade rapidly once the PFD frequency goes above 1 MHz.
Note that the 219 dBc/Hz figure of merit is obtained by extrapolating Figure 8 back to 1 Hz. The graph can be used to quickly identify the performance possible in a given PLL setup once the N value is known. For example, 200 kHz on the graph corresponds to phase noise of -166 dBc/Hz. Adding 20 logN (79 dBc) gives PLL phase noise of -87 dBc/Hz.