Integrated Solutions
for CCD Signal Processing
by Erik Barnes
The charge-coupled device (CCD) is the image sensor of choice for most consumer imaging systems. The CCD's output signal requires a unique, largely analog, signal-processing chain. At first, processing was implemented with standard linear components: op-amps, A/D and D/A converters, analog multipliers, and analog switches. As time passed, advances in semiconductor design and technology have made it possible to combine these in a more fully integrated approach to CCD signal processing. Today, all of the signal processing steps required--from the output of the CCD through the digital output of the A/D converter--can be accomplished with a single integrated circuit. Integrated solutions for CCD imaging applications from Analog Devices retain the performance of traditional designs but provide substantial savings in cost, power, and size.
Processing the CCD Signal
To understand what the integrated signal processing components have to offer, consider the typical CCD output waveform shown in Figure 1. The output stage of the CCD converts the charge of each pixel (picture element) to a voltage via the sense capacitor, CS. At the start of each pixel period, the voltage on CS is reset to the reference level, causing a reset feedthrough glitch to occur. The amount of light sensed by each pixel is measured by the difference between the reference and data voltage levels. Accurately recovering and digitizing the CCD signal requires several operations, including correlated double sampling and dc restoration (clamping), gain, offset, and A/D conversion.
Figure 1. CCD output stage.
Correlated double sampling (CDS) serves two important purposes: it calculates the difference between the reference and data levels of the CCD signal, and it reduces some of the noise components in the CCD signal. Conceptually, the CDS is a differential-in-time amplifier: it takes separate samples of the input signal and outputs the difference between them. Figure 2 shows a simple implementation of CDS using two sample-and-hold Amplifiers (SHAs) and a difference amplifier, one of many possible topologies.
Figure 2. Correlated double sampling. SHA1 samples the reference level, SHA2 the data level. The difference amplifier subtracts the samples, for a measure of the light intensity, reducing common-mode noise.
By taking two samples of the CCD signal and subtracting them, any noise source that is correlated to the two samples will be removed. A slowly varying noise source that is not correlated will be reduced in magnitude. Noise introduced in the output stage of the CCD shown in Figure 1 consists primarily of kT/C noise from the charge-sensing node, and 1/f and white noise from the output amplifier. The kT/C noise from the reset switch's ON-resistance is sampled on the Sense node, where it remains until the next pixel. It will be present during both the reference and data levels, so it is correlated within one pixel period and will be removed by the CDS. The CDS will also attenuate the 1/f noise from the output amplifier, because the frequency response of the CDS falls off with decreasing frequency. Low frequency noise introduced prior to the CDS from power supplies and by temperature drifts will also be attenuated by the CDS. But wideband noise introduced by the CCD will not be reduced by the CDS.
A typical CCD signal has a dc offset of anywhere from 3 to 9 volts or more. DC offsets of this magnitude are generally not compatible with CMOS signal processing ICs, because most scanner and high end camera systems use 5-V supplies for the signal processors, while camcorders and digital cameras use supplies as low as 2.7 volts. On-chip ac-coupling using an input "dc-restoring" clamp accomplishes the necessary dc level shift, with the addition of an external coupling capacitor.
The CCD's dark current causes a difference between the reference and data levels of the CCD signal, typically ranging from 10 to 80 mV. If left uncorrected, this offset will reduce system dynamic range, particularly after gain is applied. Analog signal processing corrects the average level of the offset, retaining dynamic range. With the major part of the offset thus removed in the analog domain, the digital image processing circuitry can perform fine offset adjustment on a pixel-to-pixel basis to correct for dark-current variations.
A programmable-gain amplifier (PGA) is needed to match the CCD signal's maximum amplitude with the full-scale voltage of the A/D converter. Different CCDs for scanner and digital camera applications can have peak spans ranging from 100 mV up to 3 or 4 volts. Most CMOS A/D converters have full-scale voltage spans of 1 to 5 volts. If the CCD signal only spans 25% of the ADC's full-scale range, 2 bits of dynamic range will be lost. The PGA will amplify the CCD signal to the appropriate amplitude, allowing the ADC's full dynamic range to be used.
The A/D converter converts the conditioned analog signal into a digital representation, which is then processed by external application-specific digital circuitry. The speed and resolution required by the A/D converter are based on the pixel rate and resolution of the application. A CCD with a maximum dynamic range of 55-60 dB would require a 10-bit ADC, while one with a dynamic range of 65-70 dB would require a 12-bit ADC. Additional resolution may be needed to allow headroom for the digital image processing. For example, digital upscaling by 6 dB reduces the dynamic range of the ADC by one bit, because only half of the A/D converter's input voltage range can be used.
Integrated Solutions from ADI
Analog Devices offers several analog front-end (AFE) integrated circuits for the scanner, digital still camera, and camcorder markets; they comprise all of the signal processing steps described above. Advances in process technology and circuit topologies have made this level of integration possible in foundry CMOS without sacrificing performance. Not long ago more-costly and power-hungry BiCMOS or bipolar technology would have been required. By combining successful ADC architectures with high-performance CMOS analog circuitry, it is possible to design complete low-cost CCD signal-processing ICs.
| Part Number | AD9807 | AD9816 | AD9805 | AD9803* | AD9802 | AD9801 |
| Number of Channels | 3 | 3 | 3 | 1 | 1 | 1 |
| Resolution, bits | 12 | 12 | 10 | 10 | 10 | 10 |
| Sampling Rate, MHz | 6 | 6 | 6 | 21 | 18 | 18 |
| Differential nonlinearity, LSBs | 0.75 max | 1.0 max | 0.5 max | 0.5 typ | 0.5 typ | 0.5 typ |
| No Missing Codes | Guaranteed | Guaranteed | Guaranteed | Guaranteed | Guaranteed | Guaranteed |
| Output Noise, rms (LSBs) | 0.3 | 0.5 | 0.1 | 0.85 | 0.85 | 0.85 |
| Internal voltage reference | Yes | Yes | Yes | Yes | Yes | Yes |
| Supply Voltage, V | +5 | +5 | +5 | +3 | +3 | +3 |
| Price, USD (1000s) | $25 | $9.50 | $9.50 | ** | $5.95 | $8.50 |
For scanner applications, the AD9807 and AD9805 (see Table) were introduced in late 1996. These devices feature three input channels for processing color linear CCDs, with input clamping, CDS, offset control, PGA, and a 12- or 10-bit ADC. Additional operating modes allow direct connection with contact image sensors (CIS), another type of image sensor that is gaining popularity. The latest product in this series is the AD9816 (Figure 3). This second-generation product functions like the AD9807, but it is housed in a smaller package and costs less.
Figure 3. The AD9816 features 3-channel simultaneous sampling, individual per-channel gain and offset adjustment, internal voltage reference, and a 6-MHz, 12-bit A/D converter. The on-board registers are programmed using a 3-wire serial interface.
For digital still camera (DSC) designs, the AD9801 was introduced in early 1997. Though it includes the same basic functions as the AD9807 family, it is tailored for use with area CCD arrays. A single-channel, 18-MHz architecture is used, with a 30-dB programmable gain amplifier, black level clamp loop, and 10-bit ADC. The input range is smaller, to accommodate the lower output voltages of area CCDs, and the programmable gain range is wider in order to be compatible with the broad range of lighting conditions in which a camera is used (scanners operate under more uniform lighting conditions). Battery operation demands lower power, so the AD9801 operates from a single 3-volt supply.
The AD9802, introduced in the fall of 1997, is intended to be used for both DSC and camcorder designs. Shown in Figure 4, the AD9802 has the features of the AD9801, and also includes a multiplexed direct input to the 10-bit ADC. A direct ADC input is required in camcorder applications, to digitize analog video signals from a tape or external VCR. The AD9803, now being sampled (at this writing), adds a serial digital interface for programming the internal registers--and features a higher sampling rate.
Performance Considerations
Two important characteristics of especial interest in imaging applications are noise and nonlinearity.
Noise in the AFE consists of wideband noise from all of the analog circuitry, wideband noise from the ADC, and quantization noise from the ADC. Stand-alone A/D converters usually specify a signal-to-noise ratio (SNR) or signal-to-noise-and-distortion (SINAD), but these types of measurements are not entirely useful in imaging applications. Converter SINAD is tested with a sine-wave input, and includes the effects of distortion of the analog signal, converter distortion due to integral and differential nonlinearity (INL and DNL), quantization noise, and thermal noise. In some cases, to reduce the contribution of thermal noise, multiple data records are averaged.
The distortion numbers are not of interest in imaging applications because CCD signals are not sinusoidal in nature, and the front-end of the ADC samples the CCD signal only during a relatively slow-moving portion of the waveform. Instead of using a traditional converter SNR measurement, CCD system designers consider the contributions from wideband noise, quantization noise, and DNL errors. Wideband noise can be measured using a "grounded-input histogram" test, in which the inputs to the device are grounded, and a histogram is taken of the output data. The standard deviation of the histogram will give the rms noise level of the device (not including the ADC quantization noise). A low-noise AFE can have a thermal noise level comparable to or less than the rms quantization noise of its on-board ADC.
AFE noise is important because of its impact on the system's dynamic range. Dynamic range is determined by comparing the maximum signal that can be processed to the minimum signal level that can be resolved in the system. Noise from the CCD and from the AFE (which includes the analog signal processing and A/D converter) will contribute to overall system noise level. The CCD random noise is usually specified by the CCD manufacturer as "noise floor" or "random noise" in mV or electrons rms; the kT/C and 1/f noise contributions will be reduced by the CDS. Fixed pattern noise due to variations in the dark current of each pixel can be very objectionable in images and should be included in the noise calculation if it is not reduced through calibration techniques. Noise will also be introduced by the amplifier used to buffer the CCD's output signal, though this can be minimized by amplifier choice and circuit techniques. The noise contribution from the AFE can be found on the product's data sheet, or measured using the grounded input histogram test. The ADC's resolution will determine the quantization noise level, which is calculated by dividing the weight of one LSB by square root of 12. Adding all the noise sources in a given bandwidth (referred to the same point in the signal chain) by root-sum-of-squares gives:
This equation can be used in approximating the achievable dynamic range, to see if the AFE being considered is a good match for the CCD. If the largest noise source is three times the next largest, it will be dominant. Understanding which noise sources are dominant will help in the selection of an appropriate AFE.
The AFE's linearity will also affect system performance. The nonlinearities of a real ADC can cause artifacts in the digitized image. Differential nonlinearity (DNL) is very important, because the human visual system is good at detecting edges or discontinuities in an image. DNL is the variation in code width for the ADC, with poor DNL causing uneven gradations or "steps" in adjacent luminosity levels. A true 10-bit system demands DNL of better than 1 LSB at the 10-bit level (0.5 LSB is preferable) to avoid degradation of image quality. DNL that is poor enough to cause missing codes can cause image artifacts in the digital processing. Integral nonlinearity (INL) is also important, but a given amount is less perceptible than a comparable amount of DNL. The human visual system is less adept at distinguishing gradual nonlinearity which is spread out over the entire grey-scale range. However, large INL can contribute to errors in the color processing algorithms of a particular system, resulting in color-related artifacts in the image.
Although the integrated approach does not have the advantage of allowing each separate processing stage to be evaluated, the AFE can be thoroughly evaluated under the operating conditions of a specific application. Evaluation boards, conveniently available for the AD980x family, simplify this step of the design.
Integration road map: Increased scope of on-chip integration for decreased size and cost is becoming a way of life in systems-on-a chip development. Now that good analog performance is possible with standard CMOS processes, it should become feasible to integrate some or all of the back-end digital processing of the imaging system onto a single chip to meet the needs of a specific application. Indeed, Analog Devices is currently producing an ASIC to meet the needs of a major scanner manufacturer for a chip that successfully integrates the AFE, digital image processing, SRAM, timing generation, CPU, and SCSI/EPP interfaces on a single chip. At this level of complexity, power and ground management on the chip is critical to minimize coupling of digital noise into the analog circuitry. Because of the large driver currents required, the solution to the problem of including the SCSI interface on-chip has been an especially challenging exercise.