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10-Bit Quad DACs for Single-Supply 3.0 V to 5.5 V Operation

Serial AD7804 & parallel AD7805 are double-buffered, have rail-to-rail output capability, plus Standby and Power-Down modes

The monolithic AD7804 and AD7805* comprise four 10-bit voltage-output digital-to-analog converters. The AD7804 (Figure 1) has a 3-wire serial digital interface, and is housed in a 16-pin DIP or SO.The AD7805 can load 10 bits in parallel-or in two bytes (8 + 2) on an 8-bit bus; it is packaged in a 28-pin DIP, SO, or SSOP. The devices operate from a 3.3-V (+-10%) to 5 V (+-10%) supply, i.e., from 3 V to 5.5 V, with an output circuit that can swing from rail to rail.


Figure 1. AD7804 functional block diagram.

The all-CMOS AD7804 and AD7805 conserve power. Besides having low dissipation (66 mW max) in normal operation, they are rated for 1.38 mW max in System Standby (with only the reference operating)-and 8.25 µW max (over temperature) in Power-Down. In addition, the four channels can be switched individually into Standby when not in use. Each channel has a Channel-Control register to control its functions; and a System Control register controls all four DACs simultaneously.

These devices have flexible voltage referencing. A 1.23-volt internally generated reference is available at REFOUT. Under control of the channel register, the reference input for each DAC (V(BIAS)) is multiplexed between the internal reference source, a REFIN terminal (for an external reference), and one-half the supply voltage (V(DD/)2). The voltage chosen, V(BIAS), provides the offset "zero" required for bipolar signals in single-supply circuitry; and the DACs are scaled for an output span of 1.875 V(BIAS). The table shows significant points along the transfer function for twos-complement coding.

Digital Input MSB . . LSB Analog Output

01111 11111 V(BIAS) (1 + 1.875[511/1024]) 01111 11110 V(BIAS) (1 + 1.875[510/1024]) 00000 00001 V(BIAS) (1 + 1.875[1/1024]) 00000 00000 V(BIAS) (1) 11111 11111 V(BIAS) (1 - 1.875[1/1024]) 10000 00001 V(BIAS) (1 - 1.875[511/1024]) 10000 00000 V(BIAS) (1 - 1.875[512/1024])

The AD7804 and AD7805 have an additional facility for independently adjusting the offset of each output (i.e., locating the output value corresponding toV(BIAS) at an arbitrarily set level). It is an 8-bit sub-DAC (shown in Figure 1 as a variable additive source in each output circuit)-with a sensitivity of 1/16 that of the main DAC.That is, each LSB change of the sub-DAC adds or subtracts V(BIAS)/4096, with a range of about +-3% V(BIAS). Settings for the sub-DACs are data inputs under the control of each Channel-Control register.

The DACs are double-buffered; this makes it possible to load the registers, one at a time, then simultaneously update all DAC outputs asynchronously. The DAC outputs may be cleared all at once by the System Register or individually by the Channel Control registers. The 3-wire serial interface allows direct interfacing to SPI, QSPI, and Microwire standards.

Brief specifications for B grades include +-3 LSB max relative accuracy error, +-35-mV offset and full-scale gain error, 4 µs max settling time to 1%, 0.002%/% power-supply rejection, 2.5 V/µs slew rate, and 1 nV-s glitch impulse. The specified operating temperature range is -40 to +85°C. Prices (1000s) for theAD7804 and AD7805 are $5.75 and $6.25, respectively.

APPLICATIONS

The low power requirements, as well as the low cost and small size of the AD7804 (and to a slightly lesser degree, the AD7805) make them suitable wherever multiple 10-bit (or upgraded 8-bit) DACs are needed.Typical areas include voltage setpoint control, trim potentiometer replacement, automatic calibration, and other instrumentation and test functions.The serialAD7804 can be easily isolated in situations where noise,safety requirements,or distances must be dealt with. Figure 2 shows an opto-isolated interface, where the clock, frame sync, and serial data inputs are isolated by optocouplers. Each DAC is automatically updated following the 16th serial clock of a write pulse.


Figure 2. Serial DAC in an opto-isolated interface configuration.

These DACs were designed by Hans Tucholski, in Limerick, Ireland.