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Ask The Applications Engineer - 2
by James Bryant
WHEN IT COMES TO TRIMMING . . .
A. Dont!- unless you must. Good alternatives include (a) using headache-free devices, components, and circuits that meet the specs without trimming; (b) taking advantage of digital technology in system applications to make trim corrections in software. Savings provided on occasion by trim potentiometers, in conjunction with loosely specd devices, can turn out to be illusory when you consider the effects of circuit design, temperature, vibration, and life on performance and stability- as well as additional paperwork and complexity trimming entails.Q. Nevertheless, how do I trim the offset and gain errors in analog circuitry?
A. In the correct order and with the correct inputs. If you consider the transfer characteristic of the circuit being trimmed the method to use is generally straightforward.
The simplified ideal transfer characteristic of a linear analog circuit (such as an amplifier, ADC or DAC) is given by the equation:
where OP is output, IP is input, and K is a scale factor (Note that this simplification hides an enormous number of issues: quantization error in an ADC; dimensionality of K if the input and output are in different forms [e.g. voltage in / current out]; intentional offsets; and many others.)
In a real (non-ideal) circuit, offset and gain errors, OS (referred to the input) and DK, respectively, also appear in the equation, which becomes:
OP = (K x IP) + [(K x OS) + (K x IP) + (K x OS)] (3)
Equations (2) and (3) are incomplete in that they assume only one offset- at the input- but this is the most-common case. Systems with separate input and output offsets will be considered later.
From (3) we see that it not possible to trim gain directly when an unknown offset is present. Offset must be trimmed first. With IP set at 0, the offset trim is adjusted until OP is also 0. Gain may then be trimmed: with an input near to full scale (FS), the gain trim is adjusted to make the output obey equation (1).Q. But what about bipolar ADCs and DACs?
A. Many ADCs and DACs may be switched between unipolar and bipolar operation; such devices, wherever possible, should have their offset and gain trimmed in the unipolar mode. Where it is not possible, or where the converter is to operate only in the bipolar mode, other considerations apply.
A bipolar converter may be considered as a unipolar converter with a large offset (to be precise, an offset of 1 MSB- one-half of full-scale range). Depending on the architecture used, this bipolar offset (BOS) may or may not be affected by the gain trim. If it is so affected, equation (1) becomes:
In this case offset is trimmed at analog zero, after which gain is trimmed near FS- positive or negative, but usually positive. This is normally the method used for DACs where the bipolar offset is within the DAC.
If the bipolar offset is not affected by the gain trim:
Here offset is trimmed at FS negative and gain is trimmed at (or very near to- see below) FS positive. This method is used for most ADCs and for DACs where bipolar offset is obtained by the use of op amps and resistors external to the DAC.
Naturally, the method suggested on the data sheet should always be followed, but where a data sheet is unobtainable, in general, offset should be trimmed at analog zero for DACs and FS negative for ADCs- and near FS positive for both.
Q. Why do you keep saying near to full scale?
A. Amplifiers and DACs may be trimmed at zero and full scale. In the case of a DAC, all-1s- the largest digital input possible- should produce an output 1 LSB below full scale, where full scale is considered as some constant times the reference; this follows since the output of a DAC is the normalized product of the reference and the digital input.
ADCs are not trimmed at zero and FS. The output of an ideal ADC is quantized, and the first output transition (from 00 . . . 00 to 00 . . . 01) takes place 1/2 LSB above the nominal value of all 0s. Thereafter transitions take place every 1-LSB increase in analog input until the final transition takes place 1 1/2 LSB below FS. A non-ideal ADC is trimmed by setting its input to the nominal value of a desired transition and then adjusting until the ADC output flickers between the two values equally.
The offset of an ADC is therefore trimmed with an input corresponding to the first transition (i.e., 1/2 LSB above zero or above FS negative- which is near zero or near FS negative); and the gain is then trimmed at the last transition (i.e. 1 1/2 LSB below FS positive- which is near FS positive). This procedure results in an interaction between the gain and offset errors during offset trim but it should be too slight to be significant.
Q. Are there any other anomalies resulting in a need to trim near, rather than at full scale?
A. Synchronous voltage-to-frequency converters (SVFCs) are liable to injection locking phenomena when their output frequency is harmonically related to their clock frequency, i.e., when their output is very close to 1/2, 1/3 or 1/4 of clock frequency. FS for an SVFC is 1/2 clock frequency. The presence of a trim tool can exacerbate the problem. It is therefore advisable to trim the gain of an SVFC at around 95% of FS.
Q. What about circuits requiring both input and output offset trim?
A. Circuits such as instrumentation and isolation amplifiers often have two stages of dc gain, and the gain of the input stages can be variable. Thus a two stage amplifier, with an input offset, IOS, an output offset, OOS, a first stage gain of K, and a unity-gain output stage, has (for zero input) an output, OP, of:
From (6) it is evident that if the gain is constant we need only adjust either IOS or OOS to null the total offset (although if the input uses a long-tailed pair of bipolar transistors we will get a better offset temperature coefficient if we trim both- for FET long-tailed pairs this is not necessarily the case). If the first stage gain is to be varied, both offsets must be trimmed.
This is done by an iterative procedure. With zero input, and gain set to maximum, the input offset is adjusted until the output is also zero. The gain is then reduced to its minimum value and the output offset adjusted until the output is zero again. The two steps are repeated until no further adjustment is necessary. Gain trimming should not be done until both IOS and OOS are pulled; the actual values of the high and low gains used in offset trim are unimportant.
Q. What circuitry should I use for gain and offset trims?
A. Many amplifiers (and a few converters) have terminals for trimming gain and offset. Many more do not.
Offset trim is normally performed with a potentiometer connected between two assigned terminals, and its wiper is connected (sometimes via a resistor) to one of the supplies. The correct connections and component values will be given on the device data sheet. One of the commonest differences between op-amps is the value of offset correction potentiometer and which supply it should be connected to.
Where separate terminals are not provided for offset trim, an offset-adjusting constant can usually be added to the input signal. Two basic possibilities are shown in Figures 1a and 1b. Where the correction is being made to a system where a differential input op amp is used as an inverter (the commonest case) the method of la is best to correct for device offsets- but not system offsets. In the single-ended connection, method 1b will work for system offsets but should be avoided where possible for small device offsets, because it often requires a very large value of summing resistance, compared to the signal-input resistances, in order to (i) avoid loading the summing point excessively, (ii) scale the correction voltage properly and produce enough attenuation to minimize the effects of differential supply-voltage drifts. It is often helpful to use resistances between the supplies and the potentiometer to increase trim resolution and reduce dissipation.
a. Voltage applied to non-inverting input.
b. Current summed at inverting input.
Where gain trim is provided for in a circuit, it will generally consist of a variable resistor. Details of its value and connection will appear on the data sheet of the device. Where gain trim is not required, this resistor may be replaced by a fixed resistor having half the resistance of the maximum value of the recommended trim potentiometer.
Where gain trim is not provided it is not always achievable externally without an additional variable-gain stage. For example, consider a DAC using a ladder network. If the ladder network is used in the current mode (Figure 2a), the input impedance at the reference terminal does not vary with digital code, and the gain of the DAC may be trimmed with a small variable resistor in series with either the reference input or the feedback resistor. However, if the DAC is used in the voltage mode (Fig 2b), then the reference input impedance is code dependent, and gain may only be trimmed by varying the reference voltage- which is not always possible- or the gain of the buffer amplifier.
The possibility of trimming gain in circuits not furnished with gain-trim circuitry, therefore, will depend on individual cases; each must be assessed on its own merits.
a. CMOS DAC connected for current steering. Input impedance is constant.