CN0241: High-Side Current Sensing with Input Overvoltage Protection

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回路の説明

回路の機能とその利点
  • +/- 32 V input over voltage protection
  • Operates from single 5 V supply
  • High side sensing rejects ground noise
  • Low power, unidirectional current monitor system
使用されている製品
    アプリケーション: 
  • 電子試験&測定
  • 電源システム
  • メーター&エネルギー計測
設計支援用データ
設計支援用データ
  • Schematic
  • Bill of Materials
  • Gerber Files
  • PADS Files
  • Assembly Drawing
Download Design Files (2897 kB)
評価ボード
"Z"が付いている製品は、RoHS準拠品です。
この実用回路を評価するには、以下の評価ボードを用いて動作確認をすることをお薦めします。
  • EVAL-CFTL-6V-PWRZ ($ 16.60) Wall Power Supply for Eval Board
  • EVAL-CN0241-SDPZ ($ 65.00) High-Side Current Sensing with Input Overvoltage Protection
  • EVAL-SDP-CB1Z ($ 99.00) EVAL Control Board
在庫確認&購入
接続オプション
This circuit supports 3rd party connectivity.

CIRCUIT FUNCTION AND BENEFITS

High-side current monitors are likely to encounter overvoltage conditions from transients or when the monitoring circuits are connected, disconnected, or powered down. This circuit, shown in Figure 1, uses the overvoltage protected ADA4096-2 op amp connected as a difference amplifier to monitor the high-side current. The ADA4096-2 has input overvoltage protection, without phase reversal or latch-up, for voltages of 32 V higher than and lower than the supply rails.

The circuit is powered by the ADP3336 adjustable low dropout 500 mA linear regulator, which can also be used to supply power to other parts of the system, if desired. Its input voltage can range from 5.2 V to 12 V when set for a 5 V output. To save power, the current sensing circuit can be powered down by removing power to the ADP3336; however, the power source, such as a solar panel, can still operate.

Figure 1. High-Side Current Sensing with Input Overvoltage Protection (Simplified Schematic: All Connections and Decoupling Not Shown)

This applies voltage to the inputs of the unpowered ADA4096-2; however, no latch-up or damage occurs for input voltages up to 32 V. If slower throughput rates are required, the AD7920 can also be powered down between samples. The AD7920 draws a maximum of 5 μW when powered down and 15 mW when powered up. The ADA4096-2 requires only 120 μA under operational conditions. When operating at 5 V, this is only 0.6 mW. The ADP3336 draws only 1 μA in the shutdown mode.

Figure 2. ADA4096-2 Simplfied Schemactic

CIRCUIT DESCRIPTION

The circuit is a classic high-side current sensing circuit topology with a single sense resistor. The other four resistors (dual 1 kΩ/20 kΩ divider) are in a thin film network (for ratio matching) and are used to set the difference amplifier gain. This will amplify the difference between the two voltages seen across the sense resistor and reject the common-mode voltage:

VOUT = (VA – VB) (20 kΩ/1 kΩ)

Figure 2 shows a simplified schematic of the ADA4096-2. The input stage comprises two differential pairs (Q1 to Q4 and Q5 to Q8) operating in parallel. When the input common-mode voltage approaches VCC - 1.5 V, Q1 to Q4 shut down as I1 reaches its minimum voltage compliance. Conversely, when the input common-mode voltage approaches VEE + 1.5 V, Q5 to Q8 shut down as I2 reaches its minimum voltage compliance. This topology allows for maximum input dynamic range because the amplifier can function with its inputs at 200 mV outside the rail (at room temperature).

As with any rail-to-rail input amplifier, VOS mismatch between the two input pairs determines the CMRR of the amplifier. If the input common-mode voltage range is kept within 1.5 V of each rail, transitions between the input pairs are avoided, thus improving the CMRR by approximately 10 dB.

The ADA4096-2 inputs are protected from input voltage excursions up to 32 V outside each rail. This feature is of particular importance in applications with power supply sequencing issues that could cause the signal source to be active before the supplies to the amplifier are applied.

Figure 3 shows the input current limiting capability of the ADA4096-2 provided by low RDSON internal series FETs (green curves) compared to using a 5 kΩ external series resistor with an unprotected op amp (red curves).

Figure 3. Input Current Limiting Capability

Figure 3 was generated with the ADA4096-2 in a unity-gain buffer configuration with the supplies connected to GND (or ±15 V) and the positive input swept until it exceeds the supplies by 32 V. In general, input current is limited to 1 mA during positive overvoltage conditions and 200 µA during negative undervoltage conditions. For example, at an overvoltage of 20 V, the ADA4096-2 input current is limited to 1 mA, providing a current limit equivalent to a series 20 kΩ resistor. Figure 3 also shows that the current limiting circuitry is active whether the amplifier is powered or not.

Note that Figure 3 represents input protection under abnormal conditions only. The correct amplifier operation input voltage range (IVR) is specified in Table 2 to Table 4 of the ADA4096-2 data sheet.

The AD7920 is a 12-bit, high speed, low power, successive approximation ADC. The part operates from a single 2.35 V to 5.25 V power supply and features throughput rates up to 250 kSPS. The part contains a low noise, wide bandwidth track-and- hold amplifier that can handle input frequencies in excess of 13 MHz.

The conversion process and data acquisition are controlled using CS and the serial clock, SCLK, allowing the devices to interface with microprocessors or DSPs. The input signal is sampled on the falling edge of CS, and the conversion is initiated at this point. There are no pipeline delays associated with the part.

The AD7920 uses advanced design techniques to achieve very low power dissipation at high throughput rates as described below.

To enter power-down mode, the conversion process must be interrupted by bringing CS high anywhere after the second falling edge of SCLK, and before the tenth falling edge of SCLK. Once CS is brought high in this window of SCLKs, the part enters power down mode, the conversion that was initiated by the falling edge of CS is terminated, and SDATA goes back into three-state. If CS is brought high before the second SCLK falling edge, the part remains in normal mode and does not power down. This avoids accidental power down due to glitches on the CS line.

To exit this mode of operation and power up the AD7920 again, a dummy conversion is performed. On the falling edge of CS, the device begins to power up, and continues to power up as long as CS is held low until after the falling edge of the tenth SCLK. The device is fully powered up once 16 SCLKs have elapsed, and valid data results from the next conversion.

If CS is brought high before the tenth SCLK falling edge, the AD7920 goes back into power-down mode again. This avoids accidental power up due to glitches on the CS line or an inadvertent burst of eight SCLK cycles while CS is low. Although the device can begin to power up on the falling edge of CS, it powers down again on the rising edge of CS, as long as it occurs before the tenth SCLK falling edge.

Further details regarding the timing can be found in the AD7920 data sheet.

TEST RESULTS

An important measure of the performance of the circuit is the amount of noise in the final output voltage measurement.

Figure 4 shows a histogram of 10,000 measurement samples. This data was taken with the CN-0241 Evaluation Board connected to the EVAL-SDP-CB1Z System Demonstration Platform (SDP-B) evaluation board. Details of the setup are described in the Circuit Evaluation and Test section of this circuit note.

The power supply was set to 3.0 V, and 10,000 samples of data were acquired at the maximum rate of 250 kSPS without having turned the output of the LDO off. Figure 4 shows the results of this acquisition. The peak-to-peak noise is approximately 2 LSBs, corresponding to about 0.3 LSB rms.

Figure 4. Histogram of Codes for 10,000 Samples before Power Down

The SD shutdown pin connected to the ADP3336 was then asserted LOW in software causing the output of the LDO to turn off. After a time of approximately 1 minute, the shutdown pin on the ADP3336 was then asserted HIGH, turning the output back on, and the same number of data samples were acquired. Figure 5 shows the results of this acquisition.

Figure 5. Histogram of Codes for 10,000 Samples after Power Down

This shows that the output of the ADA4096-2 did not latch during power down when the input was held high.

A complete design support package for this circuit note can be found at www.analog.com/CN0241-DesignSupport.

COMMON VARIATIONS

The circuit is proven to work with good stability and accuracy. This board is also compatible with the System Demonstration Platform SDP-S Controller Board (EVAL-SDP-CS1Z).

A slight modification to the circuit shown in Figure 1 allows monitoring the current for input supply voltages up to +30 V. Rather than connect the +V pin of the ADA4096-2 to the +5 V from the ADP3336, connect it directly to the input supply being monitored. In this configuration, the ADA4096-2 is powered directly from the input supply.

CIRCUIT EVALUATION AND TEST

GETTING STARTED

Load the evaluation software by placing the CN0241 Evaluation Software disc in the CD drive of the PC. Using "My Computer," locate the drive that contains the evaluation software.

FUNCTIONAL BLOCK DIAGRAM

See Figure 1 of this circuit note for the circuit block diagram and the file “EVAL-CN0241-SDPZ-SCH-RevA.pdf ” for the circuit schematics. This file is contained in the CN0241 Design Support Package.

SETUP

Connect the 120-pin connector on the EVAL-CN0241-SDPZ circuit board to the connector marked “CON A” on the EVAL-SDP-CB1Z controller (SDP-B) board. Nylon hardware should be used to firmly secure the two boards, using the holes provided at the ends of the 120-pin connectors. With power to the supply off, connect a +6 V power supply to the pins marked “+6 V” and “GND” on the board. If available, a +6 V "wall wart" can be connected to the barrel connector on the board and used in place of the +6 V power supply. Connect the USB cable supplied with the SDP-B board to the USB port on the PC. Note: Do not connect the USB cable to the mini USB connector on the SDP-B board at this time.

Turn the 5 V/2.5 A dc supply on when data is ready to be acquired. Adjust the voltage output accordingly to output the amount of current you wish to measure.

Figure 6 shows a screenshot of the CN0241 SDP evaluation software interface, and Figure 7 shows a screenshot of the EVAL-CN0241-SDPZ evaluation board. Information regarding the SDP-B board can be found in the SDP-B User Guide.

TEST

Apply power to the +6 V supply (or “wall wart”) connected to the EVAL-CN0241-SDPZ circuit board. Launch the evaluation software and connect the USB cable from the PC to the USB mini-connector on the SDP-B board.

Once USB communications are established, the SDP-B board can now be used to send, receive, and capture serial data from the EVAL-CN0241-SDPZ board.

Turn the 5 V/2.5 A dc supply on when data is ready to be acquired. Adjust the voltage output accordingly to output the amount of current you wish to measure.

Figure 6 shows a screenshot of the CN0241 SDP evaluation software interface, and Figure 7 shows a screenshot of the EVAL-CN0241-SDPZevaluation board. Information regarding the SDP-B board can be found in the .

Figure 7. EVAL-CN0241-SDPZ Evaluation Board Connected to the SDP Board

この回路に使用されている製品&サンプル:

製品 概要 サンプルが入手可能な製品
AD7920 12ビットA/Dコンバータ、250kSPS、6ピンSC70パッケージ AD7920BKSZ-500RL7 AD7920AKSZ-500RL7 AD7920BRMZ
ADA4096-2 オペアンプ、デュアル、マイクロパワー、30V電源、過電圧入力保護、入 / 出力レールtoレール ADA4096-2ARMZ ADA4096-2WARMZ-R7
ADP3336 レギュレータ、低ドロップアウト、小型、出力可変、500mA、anyCAP® ADP3336ARMZ-REEL7
評価ボード
この実用回路を評価するには、以下の評価ボードを用いて動作確認をすることをお薦めします。
モデル 概要 価格 RoHS 在庫確認/
購入/サンプル
EVAL-CFTL-6V-PWRZ Wall Power Supply for Eval Board $ 16.60 Yes
EVAL-CN0241-SDPZ High-Side Current Sensing with Input Overvoltage Protection $ 65.00 Yes
EVAL-SDP-CB1Z EVAL Control Board $ 99.00 Yes
ここに表示されている価格は、1個あたりの価格です。米国内における販売価格(FOB)で表示されておりますので、予算のためにのみご使用いただけます。 また、その価格は変更されることがあります。米国以外のお客様への価格は、輸送費、各国の税金、手数料、為替レートにより決定されます。価格・納期等の詳細情報については、弊社正規販売代理店または担当営業にお問い合わせください。なお、 評価用ボードおよび評価用キットの表示価格は1個構成としての価格です。
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