The AD9837 is a low power, programmable waveform generator capable of producing sine, triangular, and square wave outputs. Waveform generation is required in various types of sensing, actuation, and time domain reflectometry (TDR) applications. The output frequency and phase are software programmable, allowing easy tuning. The frequency registers are 28 bits: with a 16 MHz clock rate, resolution of 0.06 Hz can be achieved; with a 5 MHz clock rate, the AD9837 can be tuned to 0.02 Hz resolution.
The AD9837 is written to via a 3-wire serial interface. This serial interface operates at clock rates up to 40 MHz and is compatible with DSP and microcontroller standards. The device operates with a power supply from 2.3 V to 5.5 V.
The AD9837 has a power-down (SLEEP) function. Sections of the device that are not being used can be powered down to minimize the current consumption of the part. For example, the DAC can be powered down when a clock output is being generated.
The AD9837 is available in a 10-lead LFCSP_WD package.
|Title||Content Type||File Type|
|AD9837: Low Power, 8.5 mW, 2.3 V to 5.5 V, Programmable Waveform Generator Data Sheet (Rev A, 12/2012) (PDF, 968 kB)||Data Sheets|
|AN-1248: SPI Interface (pdf, 155 kB)||Application Notes|
|AN-1044: Programming the AD5932 for Frequency Sweep and Single Frequency Outputs (pdf, 94 kB)||Application Notes|
|AN-1070: Programming the AD9833/AD9834 (pdf, 127 kB)||Application Notes|
A Technical Tutorial on Digital Signal Synthesis
(pdf, 901 kB)
Copyright © 1999 Analog Devices, Inc.
Fundamentals of Frequency Synthesis, Part 2: Direct Digital Synthesis (DDS)
This month we conclude our two-part series on frequency synthesis, with an introduction to Direct Digital Synthesis. We will give a basic review of how a direct digital synthesis system works, touching on the inner workings of the DDS engine at a relatively high level. We will also discuss the tradeoffs between PLL and DDS technology as a base choice for frequency synthesis needs.
Performance Clocks: Demystifying Jitter
Join us as we delve into the realm of sub-picosecond jitter clocks. The relationship between jitter and phase noise will be explored in detail and methods for measuring sub-picosecond jitter and ultra low phase noise will be presented and discussed.
|UG-269: Evaluating the AD9837 Low Power, 8.5 mW, 2.3 V to 5.5 V, Programmable Waveform Generator (pdf, 691 kB)||User Guides|
|Direct Digital Synthesis ICs Deliver Power and Size Savings (25 Apr 2011)||Press Releases||HTML|
|RAQs index||Rarely Asked Questions||HTML|
|Glossary of EE Terms||Glossary||HTML|
|Title||Content Type||File Type|
|AD9837 FMC-SDP Interposer & Evaluation Board / Xilinx KC705 Reference Design||FPGA HDL||HTML|
|BeMicro FPGA Project for AD9837 with Nios driver||FPGA HDL||HTML|
|AD9837 - Microcontroller No-OS Driver||Device Drivers||HTML|
|AD9834 IIO Direct Digital Synthesis Linux Driver||Device Drivers||HTML|
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