Design & Integration Files
- Bill of Materials
- Gerber Files
- PADS Files
- Assembly Drawings
Part Numbers with "Z" indicate RoHS Compliance. Boards checked are needed to evaluate this circuit
- EVAL-AD7176-2SDZ ($50.00) Precision 24-Bit, 250 kSPS Single-Supply Sigma-Delta ADC System for Industrial Signal Levels
- EVAL-SDP-CB1Z ($99.00) Eval Control Board
Software such as C code and/or FPGA code, used to communicate with component's digital interface.
Features & Benefits
- 24-bit, 250kSPS ADC System
- Industrial Signal Levels
- Single Supply
Circuit Function & Benefits
This circuit solves the problem of acquiring and digitizing the standard industrial signal levels of ±5 V, ±10 V, and 0 V to 10 V
with precision ADCs having low supply voltages by using an
innovative differential amplifier with internal laser trimmed
resistors to perform the attenuation and level shifting. Applications
for the circuit include process controls (PLC/DCS modules), medical, and scientific multichannel instrumentation and chromatography.
The linearity of the combined AD8475 and AD7176-2 is maintained when the input signal (using a gain of 0.4×) is within a ±10 V single-ended or differential input range, as shown in the limits of the measured INL in Figure 4 where the measurement endpoints are −10 V and +10 V. In this scenario, the output of the AD8475 swings between 0.5 V and 4.5 V.
By applying the desired common-mode voltage to the VOCM pin, the common-mode output is set. In the Figure 1 circuit, the common-mode voltage is set by applying the 2.5 V REFOUT voltage from the AD7176-2 ADC to the VOCM pin of the AD8475.
The AD8475 provides the attenuation and level shifting to drive the sampling capacitor input of the AD7176-2 and consumes only 3.2 mA.
The output of the AD8475 amplifier is connected to an RC filter network that provides differential and common-mode noise filtering and that supplies the dynamic charge required by the AD7176-2 input sampling capacitors. The network also isolates the amplifier output from any kickback from the dynamic switched capacitor input. The common-mode bandwidth (RIN, C1) is 59 MHz. The differential-mode bandwidth (2 × RIN, 0.5C1 + C3) is 9.8 MHz
The AD8475 can also be set up to accept single-ended signals. Ground the −IN 0.4× input and apply the single-ended signal to the +IN 0.4× input.
The AD7176-2 24-bit, Σ-Δ ADC samples the output of the AD8475 and converts it to a digital result. The rate of conversion and the digital filter characteristic are adjustable for output data rates from 5 SPS to 250 kSPS.
The AD7176-2 is configurable for two fully differential inputs or four pseudo-differential inputs. The ADC allows up to a 50 kSPS channel scan rate. The AD7176-2 noise-free bit performance is 17.2 bits at 250 kSPS, 20.8 bits at 1 kSPS, and 21.7 bits at 50 SPS.
Figure 2 shows the effective rms noise of the total system with the inputs grounded. At a data rate of 250 kSPS, the effective rms noise is approximately 30 μV rms. When keeping in mind that the linearity of the circuit is best with a ±10 V input at full scale, the full-scale input for the calculation was set to 20 V p-p.
The effective resolution in bits, referred to a full-scale input range of 20 V, can be calculated as
Figure 3 shows the effective resolution in bits rms as a function of output data rate, measured with a shorted input.
Effective resolution can be converted to a noise-free code resolution by first converting the rms noise to approximate peak-to-peak noise by multiplying the rms noise by the factor of 6.6. This is approximately 2.7 bits that then must be subtracted from the effective resolution to get the noise-free code resolution. For the example calculated, 19.3 bits of effective resolution is equal to 16.6 bits of noise-free code resolution. This compares to the AD7176-2 specification of 17.2 noise free bits at a 250 kSPS output data rate with an unbuffered shorted input. Approximately 0.3 bits of this difference results from the fact that only ±10 V was used as the full-scale range vs. the ±12.5 V maximum.
Figure 4 shows the integral nonlinearity of the system expressed in ppm of the full-scale range (FSR) using the endpoint method.
Although the circuit is designed primarily to take dc inputs, low frequency ac inputs can also be converted. The distortion performance varies with the analog input amplitude. Figure 5 and Figure 6 show the performance with a −1 dBFS and −6 dBFS, 1 kHz sine wave, respectively. The sine wave input is applied directly to the AD8475 from the Audio Precision 2700 series audio source.
Excellent printed circuit board (PCB) layout, grounding, and decoupling techniques are mandatory for achieving optimum performance in high resolution systems. For details, see Tutorial MT-031, Tutorial MT-101, the AD8475 data sheet, and the AD7176-2 data sheet. Complete schematics and layout of the printed circuit board can be found in the CN-0310 Design Support Package.
Circuit Evaluation & Test
The following equipment is required:
- The EVAL-AD7176-2SDZ evaluation board and software
- The System Demonstration Platform (EVAL-SDP-CB1Z)
- A precision dc voltage source
- The Audio Precision 2700 Series (ac inputs)
- A PC (Windows 32-bit or 64-bit)
- A 7 V to 9 V dc supply or wall wart
The AD7176-2 evaluation kit includes self-installing software on a CD. The software is compatible with Windows® XP (SP2), Windows Vista, and Windows 7 (32 bit or 64 bit). If the setup file does not automatically run, run the setup.exe file from the CD.
Install the evaluation software before connecting the evaluation board and SDP board to the USB port of the PC to ensure that the evaluation system is correctly recognized when connected to the PC.
After installation from the CD is complete, connect the EVAL-SDP-CB1Z (via either Connector A or Connector B) to the EVAL-AD7176-2SDZ and then connect the EVAL-SDP-CB1Z to the USB port of the PC using the supplied cable.
When the evaluation system is detected, proceed through any dialog boxes that appear. This completes the installation.
Refer to the UG-478 user guide for complete details of using the software and running the tests.
A functional block diagram of the test setup is shown in Figure 7.
The following minor hardware changes are required to test the circuit in Figure 1:
- Signals are input to the AD8475 from the A2 and A3 inputs on the J8 terminal block.
- Change the SL9 and SL10 solder links to Position C routing the signals from A2 and A3 of J8 to the AD8475 inputs.
- Populate R64 and R74 with 10 Ω, 0603 resistors to connect the AD8475 outputs to the AIN2 and AIN3 pins of the AD7176-2.
- Remove the R110 and R120 resistors on the underside of the board (as shown in the UG-478 user guide).
|AD8475||Precision, Selectable Gain, Fully Differential Funnel Amplifier||
|AD7176-2||24-Bit, 250 kSPS Sigma Delta ADC with 20 µs Settling||
|ADR445||Ultralow Noise, LDO XFET® 5.0V Voltage Reference w/Current Sink and Source||