The AD9554 is a low loop bandwidth clock translator that provides jitter cleanup and synchronization for many systems, including synchronous optical networks (SONET/SDH). The AD9554 generates an output clock synchronized to up to four external input references. The digital PLL (DPLL) allows for reduction of input time jitter or phase noise associated with the external references. The digitally controlled loop and holdover circuitry of the AD9554 continuously generates a low jitter output clock even when all reference inputs have failed.
The AD9554 operates over an industrial temperature range of −40°C to +85°C. If a single or dual DPLL version of this devices is needed, refer to the AD9557 or AD9559, respectively.
|Title||Content Type||File Type|
|AD9554: Quad PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator Data Sheet (Rev A, 08/2014) (pdf, 1639 kB)||Data Sheets|
|Analog Devices Introduces Industry’s Lowest Power Quad-Channel, Jitter Attenuating, Clock Translator (20 May 2014)||Press Releases||HTML|
|Glossary of EE Terms||Glossary||HTML|
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