IMS 2026
IMS 2026
MCEC, Boston, MA
June 7 - 12
Booth #23035
Unlocking Physical Intelligence
Analog Devices looks forward to connecting with the RF and microwave community at IMS 2026. At our booth, visitors can explore how ADI is unlocking physical intelligence across increasingly complex RF environments, helping teams move faster from concept to deployment with confidence.
Across a broad set of live demonstrations, attendees will learn more about wideband direct RF sampling, phased array beamforming, spectrum sensing, precision clocking, signal conditioning, low noise power, and more. Together, these capabilities show how tightly integrated signal chains capture and translate complex real world signals into actionable insight.
ADI solutions are designed for system level integration, helping engineers push performance, efficiency, and scalability further. They address critical challenges, from maintaining phase coherence in dense multi channel systems to enabling frequency agility in dynamic spectrum environments, while laying the groundwork for emerging 6G concepts like integrated sensing and communication.
Visit Analog Devices at Booth 23035 to engage with our team, see physical signals brought to life, and learn how ADI’s platform based approach is unlocking physical intelligence.
Hear From Our Experts
Keynotes
Jeff Massman
Chief Systems Architect, Phased Arrays
Session Title: Integrated Sensing and Communications (ISAC) Technologies and Applications
Keynote Title: Ubiquitous Apertures at the AI-Driven Frontier of Phased-Array Systems for Integrated Sensing and Communications
Date: Tuesday, June 9
Time: 1:30 – 1:50 pm
Location: 253ABC
This keynote bridges the gap between ISAC (integrated sensing and communications) concepts and fieldable engineering practice. We distill system-level design patterns and measurement-driven lessons from building and validating modern phased-array RF front-ends, spanning transceiver partitioning through radiated verification. The discussion is organized around three pillars: (i) scalable synchronization of clocks and local oscillators that enable coherent array growth without violating SWaP constraints; (ii) calibration architectures that remain stable across scan angle, wide instantaneous bandwidth, polarization, and temperature, explicitly accounting for embedded-element behavior; and (iii) over-the-air measurement workflows that connect radiated metrics, such as beam patterns, EVM where applicable, and ACPR/out-of-band emissions, back to actionable engineering decisions. A central theme is the responsible use of AI/ML, using physics-informed and measurement-constrained tools to close the loop on calibration stability and anomaly detection while remaining interpretable and testable. We conclude with open research problems that must be solved to scale verification, maintain performance across dynamic environments, and ensure ubiquitous apertures are reliable, verifiable, and trusted at scale.
Sukh Deo
Director, RF Design Engineering
Session Title: The Future is Directed: Innovations in Phased Array Systems and Subsystems
Keynote Title: Beamforming Technology Advancements for Phased Array Radar Systems
Date: Tuesday, June 9
Time: 1:30 - 1:50 pm
Location: 156AB
Phased Array Radar Systems are evolving to address key system requirements of range and resolution, while enhancing beam configurability and reducing Size, Weight, Power and Cost (SWaP-C). Physical size, weight and power dissipation of phased array electronics is an important consideration. For example, at 12 GHz, λ/2 antenna lattice spacing is mere 12.5mm, which puts a severe constraint on the size and power dissipation of the electronic components that must fit on a flat panel antenna board designed with such lattice spacing. At Ku-band, this issue becomes even more exacerbated. Advancements in Si based beamforming and SOI switch technologies coupled with small form factor GaN power amplifiers and advanced packaging technologies are enabling high performance, flat-panel Phased Array Antenna designs at S, C, X and Ku bands. This talk will examine key IC technologies that are enabling advancements in Flat-panel Phased Array Antenna Systems for dual-use military and commercial applications, such as air surveillance, air traffic control, weather monitoring and imaging. Flat-panel antennas are space efficient and allow modular tile design approach, which reduces development time and cost by offering easy prototyping and scalability. However, they require high level of IC integration and innovation in packaging and thermal management solutions. This talk will provide an overview of these technologies.
RF Bootcamp
Bryan Goldstein
ADI Corporate VP, Aerospace, Defense and Communications
RF Bootcamp
RFMW Application Focus: Tx/Rx Communication and Phased-Array
Date: Monday, June 8
Time: 8:00 am - 5:20 pm
Location: Room 259AB
This session will cover a multi-channel Tx/Rx RFMW Communications System design and how RFMW and digital domains are merging to allow advanced design and characterization techniques. We will follow the development of a microwave Transmit/Receive system, as well as the requirements and architectures for phased-arrays, from simulation to trade-offs to test, calibration and production. We will show how the system-level performance and environmental requirements drive the electrical and mechanical design specifications, packaging approach and materials selection. We will demonstrate modeling/simulation approaches from the device to the system level for both electrical and mechanical aspects and we will describe bread-boarding strategies to affirm simulation models and to minimize risk. Lastly, we will demonstrate production test strategies and methodologies to guarantee performance compliance of the deliverable product.
IMS Executive Forum
Bryan Goldstein,
ADI Corporate VP, Aerospace, Defense and Communications
Microelectronics Product Development for Aerospace & Defense on Commercial Timelines
Date: Wednesday, June 10
Time: 4:00 - 5:00 pm
Location: MicroApps Theater, IMS Exhibit Hall
Moderator: Timothy Hancock, Director of Microelectronics, Raytheon Advanced Technology
Panelists:
- Bryan Goldstein, ADI Corporate VP, Aerospace, Defense and Communications
- Eric Makara, Director of Trusted & Assured Microelectronics, OUSW(R&E)
- Ishan Sandhu, TI Director, Sales & Applications
- Minal Sawant, AMD Sr. Director, Aerospace & Defense Vertical Market
- James Chew, VP for Intel Government Technologies
This panel of executives from the semiconductor industry will discuss the challenges of developing for the Aerospace & Defense Market segment that has historically been limited to a few large prime contractors with long development cycles and Government customers with limited technology insertion points for large programs of record. This paradigm is shifting with the traditional defense industrial base becoming more agile along with new VC-backed defense firms that are responding to the customers’ desire to move faster, sometimes with relaxed requirements.
Workshops
Explore the Flexibility in Apollo MxFE™ to Maximize the Spectrum Equalization Performance
Date: Tuesday, June 9
Time: 1:30 - 3:10 pm
Location: Room 152
Speakers:
- Michelle Tan, Principal Engineer, Product Software Applications
- Siddhartha Das, Systems Applications Engineer
- Robert Dandaraw, Principal Engineer, Product Marketing
- Peter Delos, Senior Principal Engineer, Systems Design
Join us this workshop to learn creative methods to maximize the spectrum equalization performance for Apollo MxFE™ by exploring the flexibility in its DSP architecture. The methods include a two-stage filtering using both PFILT and CFIR and leveraging CFIR sparse mode to expand effective taps from 16 to a maximum of 128. Simulation results along with a live demo of ADXBAND16EBZ - a Quad Apollo system development board will demonstrate the significant improvements in equalization performance, highlighting how Apollo’s flexible DSP architecture enables higher system-level capability across EW, Radar, ISR, and Instrumentation applications.
Date: Tuesday, June 9
Time: 1:30 - 3:10 pm
Location: Room 154
Speakers:
- Jordan Besnoff, Staff Engineer, Systems Integration Engineeering
- Dan Mantoni, Director of Simulation and Modeling
The evolution of wireless systems toward higher frequencies, together with the integration of joint RF sensing and communications, drives unprecedented demands on phased array performance. Next-generation architectures must deliver exceptional transmitter linearity and receiver sensitivity across multi-gigahertz bandwidths and large antenna arrays. We explore advanced measurement and behavioral modeling techniques, linking hardware prototypes with digital twins to accelerate the exploration of architectures and the development of wideband adaptive analog and digital algorithms, emphasizing the balance between modeling accuracy and computational efficiency. Demonstrations highlight design trade-offs and performance optimization strategies relevant to both 5G/6G communication links and AESA radar systems.
Date: Tuesday, June 9
Time: 3:40 - 5:20 pm
Location: Room 152
Speakers:
- Brad Hall, Principal Engineer, Systems Integration
- Alp Oguz, Principal Engineer, Mixed Signal Design
- Selim Abdelrahman, Senior Manager, Analog/RF Design Engineer
- Ekrem Oran, Senior Principal Engineer, RF Design Engineer
- Jon Hall, Principal Product Marketing Engineer
This workshop explores the design of a high-performance signal chain spanning DC to 55 GHz. Attendees will examine key topics such as Digitization, Wideband up/down conversion, Tunable filtering, and Amplification. Key components will be highlighted showing unique features and process tradeoffs. Topics include architecture tradeoffs, frequency planning, high-speed data conversion, and system-level optimization for dynamic range and latency. Practical insights into design approach, calibration, and signal integrity will be shared. Ideal for RF and DSP engineers, this session equips participants with the knowledge to architect scalable signal chains for radar, 5G/6G, satellite, and instrumentation applications.
Date: Wednesday, June 10
Time: 8:00 - 9:40 am
Location: Room 152
Speakers:
- Siddhartha Das, Systems Applications Enginee
- Sam Ringwood, Systems Engineer
This workshop showcases the development of a phased array system for direction-of-arrival (DoA) estimation and beamforming, leveraging the Analog Devices Quad-Apollo ADXBAND16EBZ platform integrating with MATLAB. Participants will explore MATLAB-based hardware interfacing, array simulation for initial algorithm development (MUSIC and MVDR), and hardware-in-the-loop approaches to test algorithms in a controlled environment while contending with difficulties that come when working with real hardware. The workshop culminates in an over-the-air demonstration using a 16-element uniform rectangular array connected to the Quad-Apollo, highlighting array processing techniques with real signals. Attendees will gain practical insights into bridging algorithm design, simulation, and hardware implementation.
Keeping up with the Wireless G’s: Role of Software Defined Radios and Standard Interfaces
Date: Wednesday, June 10
Time: 10:10 - 11:50 am
Location: Room 154
Speakers:
- Hossein Yektaii, Wireless System Architect
- Nehal Parikh, Principal Engineer, Product Applications
- Kevin Gard, Principal IC Design Engineer
This workshop explores the evolution of wireless standards from 2G to 6G, highlighting the economic impact on network operators, equipment vendors, and semiconductor providers. We examine how software-defined radios (SDRs) have adapted to each generation and the role of standard interfaces in enabling scalable, efficient development. The session concludes with a real-world example from Analog Devices, showcasing an SDR transceiver integrated with signal processing and physical layer functionality aligned with the open radio access network (O-RAN) standard.
Date: Wednesday, June 10
Time: 1:30 - 3:10 pm
Location: Room 152
Speakers:
- Amr Elsherief, Senior Manager, Design Evaluation Engineering
- Kasey Chatzopoulos, Senior Manager, Product Applications
- Taz Thahirally, Staff Applications Engineer
As demand grows for high-frequency, high-bandwidth wireless connectivity, system designers face challenges balancing performance, power efficiency, and thermal management. This workshop explores Analog Devices’ mmWave technology evolution—from discrete RF components to integrated reference designs—highlighting solutions across generations of analog beamforming, frequency conversion, and frequency generation. Attendees will learn how ADI’s system-level innovations enable higher linear output power while maintaining strict power limits, reducing thermal complexity. Through technical discussions, design examples, and benchmarks, the session demonstrates how ADI’s scalable mmWave solutions accelerate development and meet the demands of next-generation wireless infrastructure including 5G FR2, FWA, and satellite communications.
The Dynamic Duo – Software Defined Radio (SDR) & Software Defined Modem (SDM)
Date: Wednesday, June 10
Time: 1:30 - 3:10 pm
Location: Room 154
Speakers:
- Matthew Hazel, Sr. Product Marketing Engineer, Multi-Market Transceivers
- Conrad Collins, Sr. Product Applications Engineer, Narrowband Transceivers
- Manusri Viswanathan, Embedded Software Engineer
- Henryk Mironczuk, Senior Manager, Product Applications, ADEF & Communications
Join our diverse team of engineers and discover how ADI’s first ever Software Defined Modem, integrated into the Nevis Narrowband Transceiver, is enabling smaller, lighter, and lower power radios than ever before while still delivering state of the art RF performance. This workshop combines theory with real-world performance data and real-time demonstrations to illustrate how users can leverage Nevis to advance the state of the art in their own radio designs. As a practical example, ADI will present how the combination of an SDR & SDM is being leveraged to create a new generation of Land Mobile Radios.
Microapps Theater, IMS Exhibit Hall
Hossein Yektaii
Wireless System Architect
Software Defined Radio (SDR) on a Chip - From Ethernet to RF with an Integrated Processor Sub-System
Date: Wednesday, June 10
Time: 9:45 - 10:00 am
The latest generation of ADI monolithically integrated software defined radio chip is introduced in this MicroApp. This 6th generation device builds on 15 years, and 5 generations of ADI integrated transceiver SoCs. It contains 4 transmitters, and 4 receiver chains along with a rich set of radio signal processing features. The latest addition to this generation is the low-PHY functionality supporting 4G and 5G wireless standards, 2x25Gbps Ethernet based fronthaul interface in accordance with ORAN standard, and a processor sub-system eliminating the need for an external FPGA.
Bryan Goldstein,
ADI Corporate VP, Aerospace, Defense and Communications
RF Entrepreneurship in the Age of AI, New Space, and New Defense
Date: Wednesday, June 10
Time: 11:10 - 11:55 am
Moderator: Chris Marki, CEO, Marki Microwave
AI-driven systems, venture-backed defense startups, proliferated LEO constellations, and the maturation of wireless are reshaping the economics and architecture of RF systems. This panel explores how these forces will create new opportunities — and potentially disrupt incumbents — across components, subsystems, and design tools. Where will the next generation of RF startups emerge, and what moats will matter?
Ian Beavers
Staff Aerospace, Defense and Communications System Platform Engineer
Multi-Chip Synchronization of RF Channels
Date: Thursday, June 11
Time: 10:19 - 10:34 am
How can you synchronize a plethora of RF sub-system tiles that could be meters or even tens of meters away from each other? Learn how to synchronize a large, RF phased array system by nulling out path delay differences. Learn how the RF alignment of multiple ADCs and DACs from different sub-systems can each be controlled from a master synchronizer solution from the top of a fan-out tree structure. The alignment solution can accommodate changes in temperature gradient by monitoring the timing skew delta and adjusting synchronization based on the user's pre-defined system limits.
Padraig McDaid
Principal Marketing Manager
ZIF Based SDR Transceiver as a New Solution for Test, Measurement and Radar
Date: Thursday, June 11
Time: 1:43 - 1:58 pm
There is an ever-increasing need for improved RF performance, lower power consumption and increased digital integration in test, instrumentation, and radar applications. In this session, we will dive into the suitability of 3 new ZIF based SDR Transceivers to support these needs - ranging from 2 to 8 channels, up to 400MHz BW, up to 7.125GHz tuning range, and with DPD - CFR integrated. We will walk through each of these device architectures, discuss the differences of a ZIF based approach versus the classic Direct RF approach, and outline best design approaches to maximize the performance of these new products.
Technical Sessions
Kevin Gard
Principal IC Design Engineer
Industry Innovations in Transceivers and Beamformers for Communication and Radar
Title: Ethernet to RF: Single Chip ORAN 4TX/4RX 5G Radio Unit Base Station Transceiver
Date: Monday, June 8
Time: 8:00 - 8:20 am
Location: Room 252AB
This paper presents the first RF-to-Ethernet Open Radio Access Network (ORAN) split 7.2A radio unit (RU) base station system-on-a-chip (SOC). In 16nm FinFET CMOS, the 4-TX, 4-RX transceiver provides 660 MHz large-signal BW and 800 MHz DPD synthesis BW, across LO frequencies from 400 MHz to 7.1 GHz. It supports full-band multicarrier (MC) operation in all TDD/FDD 3GPP bands for NR FR1, LTE, and NB-IoT radios. The SoC includes 2×10Gb/s or 2×25Gb/s Ethernet interface, four receivers, four transmitters, and a digital pre-distortion (DPD) feedback receiver (FBRX). Four PLLs provide digital/data converter clocks, Ethernet clocks and two RF LO signals. Digital interpolation, decimation, AGC, TX Power control, and calibrations are managed by an ARM M4 dual core processor and internal controllers. An ARM A55 quad core processor running Linux provides radio unit (RU) control. Total SOC power dissipation for dual band FDD 4TX/4RX/FBRX 800 MHz synthesis BW is 24.1W.
Christoph Steinbrecher
Principal Design Engineer
Industry Innovations in Transceivers and Beamformers for Communication and Radar
Title: A SiGe TXSIP for E-Band Point-to-Point Systems from 71 to 86 GHz with >32 dBm Output Power
Date: Monday, June 8
Time: 9:00 - 9:20 am
Location: Room 252AB
This paper presents an all-Silicon system-in-package transmitter covering the entire E-Band spectrum from 71 to 86 GHz for point-to-point microwave links. It integrates an upconverter (UPC), variable gain amplifier (VGA) and two power amplifiers (PA) which are flip-chip mounted in a low-cost 19 mm x 20 mm LGA package with a WR12 waveguide interface. The integrated PAs combine 64 individual amplifier channels and achieve a PSAT greater than 32 dBm. The TXSIP meets 5G NR EVM limits up to output powers of 29, 28 and 26 dBm for 1 GSym/s 4-QAM, 16-QAM and 64-QAM signals, respectively.
Broadband RF Front-End Components for Next Generation Wireless Systems
Title: A Fully Differential DC-Capable RF SPDT Switch in SOI
Date: Tuesday, June 9
Time: 11:10 - 11:30 am
Location: Room 252AB
Speakers:
- Ilker Kalyoncu, Principal RFIC Design Engineer
- Huseyin Kayahan, Senior Manager, Analog Design Engineering
This paper introduces the first fully differential SOI SPDT switch with true dc switching capability combined with broadband RF performance. The design operates from dc to 12 GHz while sustaining ±8 V common-mode voltage and handling 31 dBm differential RF power. A series–shunt topology with four stacked transistors per branch is combined with distributed dc tracking loops that bootstrap gate/body resistors up to 20 MHz, overcoming the low-frequency power-handling vs switching-speed trade-off. A start-up scheme enables ±12 V supply operation in a 3.3 V process. Measured results demonstrate sub-1 dB insertion loss and excellent linearity (>34 dBm IP1dB and ~60 dBm IP3), enabling robust switching of high-speed differential links and instrumentation paths requiring mixed dc and RF capability.
Preview Our Demos
Preview Our Aerospace Demos
Sub-Second Readiness: From Power-On to Mission-Ready
Fast bring-up delivers a critical advantage when seconds matter. Witness how a direct-RF front end reaches mission-ready operation in under one second. Optimized configuration flows enable rapid responsiveness without sacrificing performance.
Wideband Spectrum Sensing with Signal Agility
Spectrum conditions rarely stand still. This solution shows how multiple narrowband signals can be detected, processed, and retuned within a single wideband channel. Attendees can explore how this capability enables agile, power‑efficient spectrum monitoring platforms.
4-Channel GNSS with Deterministic Phase Alignment
Coherent GNSS reception across channels is critical in contested environments. Learn how for AD9310 4-channel GNSS receiver a system-level calibration establishes deterministic phase alignment across multi-channel receiver paths without dedicated internal multi-chip sync hardware, enabling coherent operation to support null steering (CRPA) and resistance to jamming and spoofing.
Experiencing 6G Integrated Sensing & Communication with Dragonfly
Step into the future of multifunction wireless systems, where integrated sensing and communication unifies connectivity with object detection and tracking. This interactive system walkthrough spans architectures from discrete RF components to integrated reference designs. High-speed beam switching enables rapid scanning suited for real-time sensing applications.
Adaptive Beamforming in Action: Real-Time Jammer Nulling & SNR Lift
Over-the-air audio links become dramatically more robust when spatial processing is applied in real time. Adaptive beamforming demonstrates measurable SNR improvement while actively placing nulls on interfering sources. This platform demonstration previews scalable phased-array techniques built for multi-element growth, enabling users to deploy more robust, flexible, and interference aware RF solutions.
X-Band Digital Beamforming Platform using High-Density Direct RF Sampling
Digital beamforming becomes more accessible when channel density and RF sampling align in a practical platform. This demonstration highlights direct RF sampling in X-band with phase-aligned multi-channel transmit and receive operation. The approach reduces the number of RF conversion stages while accelerating beamforming evaluation.
Next-Gen High-Speed ADC Performance with On-Chip DSP Acceleration
High dynamic range and power efficiency take center stage in this high‑speed data conversion demo. Designed for precision critical applications, the converter delivers exceptional dynamic range and distortion metrics across bandwidths up to 1 GHz. Wideband, low‑noise performance is paired with on‑chip digital signal processing for filtering, down‑conversion, and decimation, streamlining architectures and reducing reliance on external processing.
2–18 GHz Signal Conditioning for Direct-Sampling Receivers
Wideband direct sampling benefits from a carefully engineered RF front end. Explore a complete 2–18 GHz signal conditioning chain optimized for dynamic range and low noise figure, targeting high-performance wideband receiver applications. Visitors can learn how amplification, attenuation, filtering, and switching work together to support direct sampling receivers.
Deterministic Phased-Array Communications with Seamless Frequency Hopping
Dynamic spectrum environments demand both agility and coherence. This phased-array platform demonstration maintains deterministic phase alignment while rapidly hopping carrier frequency. Visitors can observe how phase coherence is preserved across frequency changes to enable resilient, interference-aware beamforming links.
Clocking Breakthroughs: Fast-Hop Synchronization and Ultra-Low Jitter
Timing is everything in advanced RF systems, and frequency agility is only valuable when synchronization remains deterministic. This 2 part demonstration will showcase rapid frequency hopping while maintaining tight phase alignment across devices, as well as next-generation clocking with exceptionally low RMS jitter for demanding systems.
Seamless DC–18 GHz Coverage with Dual-Clock Direct RF
Modern signal environments demand continuous spectral visibility without gaps. Explore how uninterrupted wideband visibility changes the way signals are captured and analyzed. This demo shows how dual, independent sampling clocks eliminate Nyquist gaps and enable seamless DC to 18 GHz coverage in a single architecture. The result is full-band insight in a compact direct-RF mixed-signal front end that simplifies architecture and speeds evaluation.
AI-Enhanced Radio Efficiency at the Physical Edge
Performance gains don’t have to come at the cost of power. AI-assisted signal processing improves linearization while enabling energy efficiency gains. Integrated energy-saving modes demonstrate measurable power reduction. Together, these capabilities highlight smarter, more efficient wireless infrastructure.
Quad-Cell Phased-Array Reference Designs for Rapid Evaluation
Phased-array evaluation accelerates when hardware and control interfaces are streamlined. These quad-cell reference designs integrate the beamformer and transmit/receive modules with simplified connectivity. Learn how these solutions enable fast characterization and quicker software bring-up.
Power-Efficient RF with Built-In Modem Intelligence
What if modem intelligence lived directly inside the RF platform? This demo explores a power efficient architecture combining flexible RF operation with embedded processing. Attendees can learn how local data handling and waveform adaptability reduce system complexity and enable smarter radios.
High-Density RF Digitizer SoM in a VNX+ Small Form Factor
High channel counts and tight SWaP targets don’t have to trade off performance. This compact digitizer system-on-module delivers active transmit and receive across a wide RF tuning range, supporting spectrum sensing and beamforming-ready architectures. Attendees can learn how the VNX+ form factor streamlines integration for cost-sensitive, space-constrained platforms.
Preview Our Industrial Demos
Apollo Power Simplified: Direct from Silent Switcher® 3
How small can power solutions go without sacrificing RF performance? This side by side comparison shows how silent switching preserves phase noise and SNR while reducing solution size. Attendees can see firsthand how compact power design supports denser RF platforms.
Fast, Precise Power-Rail Measurements for High-Speed Test
Power behavior is often the hidden variable in high speed systems. As interface speeds climb, supply monitoring must keep pace. This reference approach pairs high-precision measurement with high-speed capture to observe rail behavior accurately. Visitors can see how early insight into power integrity accelerates validation and debug.
Preview Our Instrumentation Demos
Multi-Channel Synchronization for FR3 mMIMO Test
As Massive MIMO test channel densities rise, phase coherence becomes essential. See how multiple 6–18 GHz RF signal chains are synchronized to within picoseconds for repeatable, high-fidelity measurements. Attendees will discover how integrated LO generation, clocking, and power management reduces complexity for next-generation wireless test systems.
Signal Integrity & TDR Analysis with Multiport VNA
High-speed digital links require both frequency- and time-domain insight. This demonstration showcases signal integrity and TDR measurements for modern serial links, such as those used in AI data centers, supported by ADI's VNA signal chains. Multiport analysis enables faster diagnosis of cables, connectors, and backplanes.
Preview Our Multi Market Power Demos
Find the Quietest Rail: Power Noise & Rejection Visualized
Power integrity is easiest to trust when you can see it in real time. Attendees can probe multiple power rails and directly compare noise performance across regulator types. This demo highlights how different approaches meet the needs of noise-critical and non-critical power domains.
Low Noise, High Efficiency µModule® Regulators with Silent Switcher®
Noise-sensitive systems often pay a penalty in size and complexity due to post-filtering, but cleaner power doesn’t have to mean larger solutions. ADI’s µModule® regulators with patented Silent Switcher® technology deliver low EMI and low noise performance, helping designers reduce or eliminate additional filtering. The result is a cleaner power rail in a smaller footprint.