# |
NAME |
DIR |
[LSB:MSB] |
SIG |
ATTRIBUTES |
axi_gpio_0
|
axi_gpio_0_GPIO_IO_I_pin |
I |
0:7 |
axi_gpio_0_GPIO_IO_I |
|
axi_gpio_0
|
axi_gpio_0_GPIO_IO_O_pin |
O |
0:7 |
axi_gpio_0_GPIO_IO_O |
|
axi_gpio_0
|
axi_gpio_0_GPIO_IO_T_pin |
O |
0:7 |
axi_gpio_0_GPIO_IO_T |
|
axi_gpio_1
|
axi_gpio_1_GPIO_IO_I_pin |
I |
0:7 |
axi_gpio_1_GPIO_IO_I |
|
axi_gpio_1
|
axi_gpio_1_GPIO_IO_O_pin |
O |
0:7 |
axi_gpio_1_GPIO_IO_O |
|
axi_gpio_1
|
axi_gpio_1_GPIO_IO_T_pin |
O |
0:7 |
axi_gpio_1_GPIO_IO_T |
|
axi_gpio_2
|
axi_gpio_2_GPIO_IO_I_pin |
I |
0:7 |
axi_gpio_2_GPIO_IO_I |
|
axi_gpio_2
|
axi_gpio_2_GPIO_IO_O_pin |
O |
0:7 |
axi_gpio_2_GPIO_IO_O |
|
axi_gpio_2
|
axi_gpio_2_GPIO_IO_T_pin |
O |
0:7 |
axi_gpio_2_GPIO_IO_T |
|
axi_gpio_3
|
axi_gpio_3_GPIO_IO_I_pin |
I |
0:7 |
axi_gpio_3_GPIO_IO_I |
|
axi_gpio_3
|
axi_gpio_3_GPIO_IO_O_pin |
O |
0:7 |
axi_gpio_3_GPIO_IO_O |
|
axi_gpio_3
|
axi_gpio_3_GPIO_IO_T_pin |
O |
0:7 |
axi_gpio_3_GPIO_IO_T |
|
axi_gpio_led
|
axi_gpio_led_GPIO_IO_O_pin |
O |
0:7 |
axi_gpio_led_GPIO_IO_O |
|
axi_gpio_oled
|
axi_gpio_oled_GPIO_IO_O_pin |
O |
0:7 |
axi_gpio_4_GPIO_IO_O |
|
axi_gpio_pmodPortMux
|
axi_gpio_pmodPortMux_GPIO_IO_O_pin |
O |
0:7 |
axi_gpio_pmodPortMux_GPIO_IO_O |
|
axi_iic_0
|
axi_iic_0_Scl_I_pin |
I |
1 |
axi_iic_0_Scl_I |
|
axi_iic_0
|
axi_iic_0_Sda_I_pin |
I |
1 |
axi_iic_0_Sda_I |
|
axi_iic_0
|
axi_iic_0_Scl_O_pin |
O |
1 |
axi_iic_0_Scl_O |
|
axi_iic_0
|
axi_iic_0_Scl_T_pin |
O |
1 |
axi_iic_0_Scl_T |
|
axi_iic_0
|
axi_iic_0_Sda_O_pin |
O |
1 |
axi_iic_0_Sda_O |
|
axi_iic_0
|
axi_iic_0_Sda_T_pin |
O |
1 |
axi_iic_0_Sda_T |
|
axi_iic_1
|
axi_iic_1_Scl_I_pin |
I |
1 |
axi_iic_1_Scl_I |
|
axi_iic_1
|
axi_iic_1_Sda_I_pin |
I |
1 |
axi_iic_1_Sda_I |
|
axi_iic_1
|
axi_iic_1_Scl_O_pin |
O |
1 |
axi_iic_1_Scl_O |
|
axi_iic_1
|
axi_iic_1_Scl_T_pin |
O |
1 |
axi_iic_1_Scl_T |
|
axi_iic_1
|
axi_iic_1_Sda_O_pin |
O |
1 |
axi_iic_1_Sda_O |
|
axi_iic_1
|
axi_iic_1_Sda_T_pin |
O |
1 |
axi_iic_1_Sda_T |
|
axi_iic_2
|
axi_iic_2_Scl_I_pin |
I |
1 |
axi_iic_2_Scl_I |
|
axi_iic_2
|
axi_iic_2_Sda_I_pin |
I |
1 |
axi_iic_2_Sda_I |
|
axi_iic_2
|
axi_iic_2_Scl_O_pin |
O |
1 |
axi_iic_2_Scl_O |
|
axi_iic_2
|
axi_iic_2_Scl_T_pin |
O |
1 |
axi_iic_2_Scl_T |
|
axi_iic_2
|
axi_iic_2_Sda_O_pin |
O |
1 |
axi_iic_2_Sda_O |
|
axi_iic_2
|
axi_iic_2_Sda_T_pin |
O |
1 |
axi_iic_2_Sda_T |
|
axi_iic_3
|
axi_iic_3_Scl_I_pin |
I |
1 |
axi_iic_3_Scl_I |
|
axi_iic_3
|
axi_iic_3_Sda_I_pin |
I |
1 |
axi_iic_3_Sda_I |
|
axi_iic_3
|
axi_iic_3_Scl_O_pin |
O |
1 |
axi_iic_3_Scl_O |
|
axi_iic_3
|
axi_iic_3_Scl_T_pin |
O |
1 |
axi_iic_3_Scl_T |
|
axi_iic_3
|
axi_iic_3_Sda_O_pin |
O |
1 |
axi_iic_3_Sda_O |
|
axi_iic_3
|
axi_iic_3_Sda_T_pin |
O |
1 |
axi_iic_3_Sda_T |
|
axi_spi_0
|
axi_spi_0_MISO_I_pin |
I |
1 |
axi_spi_0_MISO_I |
|
axi_spi_0
|
axi_spi_0_MOSI_O_pin |
O |
1 |
axi_spi_0_MOSI_O |
|
axi_spi_0
|
axi_spi_0_SCK_O_pin |
O |
1 |
axi_spi_0_SCK_O |
|
axi_spi_0
|
axi_spi_0_SS_O_pin |
O |
0:1 |
axi_spi_0_SS_O |
|
axi_spi_1
|
axi_spi_1_MISO_I_pin |
I |
1 |
axi_spi_1_MISO_I |
|
axi_spi_1
|
axi_spi_1_MOSI_O_pin |
O |
1 |
axi_spi_1_MOSI_O |
|
axi_spi_1
|
axi_spi_1_SCK_O_pin |
O |
1 |
axi_spi_1_SCK_O |
|
axi_spi_1
|
axi_spi_1_SS_O_pin |
O |
0:0 |
axi_spi_1_SS_O |
|
axi_spi_2
|
axi_spi_2_MISO_I_pin |
I |
1 |
axi_spi_2_MISO_I |
|
axi_spi_2
|
axi_spi_2_MOSI_O_pin |
O |
1 |
axi_spi_2_MOSI_O |
|
axi_spi_2
|
axi_spi_2_SCK_O_pin |
O |
1 |
axi_spi_2_SCK_O |
|
axi_spi_2
|
axi_spi_2_SS_O_pin |
O |
0:0 |
axi_spi_2_SS_O |
|
axi_spi_3
|
axi_spi_3_MISO_I_pin |
I |
1 |
axi_spi_3_MISO_I |
|
axi_spi_3
|
axi_spi_3_MOSI_O_pin |
O |
1 |
axi_spi_3_MOSI_O |
|
axi_spi_3
|
axi_spi_3_SCK_O_pin |
O |
1 |
axi_spi_3_SCK_O |
|
axi_spi_3
|
axi_spi_3_SS_O_pin |
O |
0:0 |
axi_spi_3_SS_O |
|
axi_uartlite_0
|
axi_uartlite_0_RX_pin |
I |
1 |
axi_uartlite_0_RX |
|
axi_uartlite_0
|
axi_uartlite_0_TX_pin |
O |
1 |
axi_uartlite_0_TX |
|
axi_uartlite_1
|
axi_uartlite_1_RX_pin |
I |
1 |
axi_uartlite_1_RX |
|
axi_uartlite_1
|
axi_uartlite_1_TX_pin |
O |
1 |
axi_uartlite_1_TX |
|
axi_uartlite_2
|
axi_uartlite_2_RX_pin |
I |
1 |
axi_uartlite_2_RX |
|
axi_uartlite_2
|
axi_uartlite_2_TX_pin |
O |
1 |
axi_uartlite_2_TX |
|
axi_uartlite_3
|
axi_uartlite_3_RX_pin |
I |
1 |
axi_uartlite_3_RX |
|
axi_uartlite_3
|
axi_uartlite_3_TX_pin |
O |
1 |
axi_uartlite_3_TX |
|
processing_system7_0
|
processing_system7_0_PS_CLK_pin |
I |
1 |
processing_system7_0_PS_CLK |
CLK |
processing_system7_0
|
processing_system7_0_PS_PORB_pin |
I |
1 |
processing_system7_0_PS_PORB |
|
processing_system7_0
|
processing_system7_0_PS_SRSTB_pin |
I |
1 |
processing_system7_0_PS_SRSTB |
|
processing_system7_0
|
processing_system7_0_DDR_Addr |
IO |
0:14 |
processing_system7_0_DDR_Addr |
|
processing_system7_0
|
processing_system7_0_DDR_BankAddr |
IO |
0:2 |
processing_system7_0_DDR_BankAddr |
|
processing_system7_0
|
processing_system7_0_DDR_CAS_n |
IO |
1 |
processing_system7_0_DDR_CAS_n |
|
processing_system7_0
|
processing_system7_0_DDR_CKE |
IO |
1 |
processing_system7_0_DDR_CKE |
|
processing_system7_0
|
processing_system7_0_DDR_CS_n |
IO |
1 |
processing_system7_0_DDR_CS_n |
|
processing_system7_0
|
processing_system7_0_DDR_Clk |
IO |
1 |
processing_system7_0_DDR_Clk |
CLK |
processing_system7_0
|
processing_system7_0_DDR_Clk_n |
IO |
1 |
processing_system7_0_DDR_Clk_n |
CLK |
processing_system7_0
|
processing_system7_0_DDR_DM |
IO |
0:3 |
processing_system7_0_DDR_DM |
|
processing_system7_0
|
processing_system7_0_DDR_DQ |
IO |
0:31 |
processing_system7_0_DDR_DQ |
|
processing_system7_0
|
processing_system7_0_DDR_DQS |
IO |
0:3 |
processing_system7_0_DDR_DQS |
|
processing_system7_0
|
processing_system7_0_DDR_DQS_n |
IO |
0:3 |
processing_system7_0_DDR_DQS_n |
|
processing_system7_0
|
processing_system7_0_DDR_DRSTB |
IO |
1 |
processing_system7_0_DDR_DRSTB |
RESET |
processing_system7_0
|
processing_system7_0_DDR_ODT |
IO |
1 |
processing_system7_0_DDR_ODT |
|
processing_system7_0
|
processing_system7_0_DDR_RAS_n |
IO |
1 |
processing_system7_0_DDR_RAS_n |
|
processing_system7_0
|
processing_system7_0_DDR_VRN |
IO |
1 |
processing_system7_0_DDR_VRN |
|
processing_system7_0
|
processing_system7_0_DDR_VRP |
IO |
1 |
processing_system7_0_DDR_VRP |
|
processing_system7_0
|
processing_system7_0_MIO |
IO |
0:53 |
processing_system7_0_MIO |
|
processing_system7_0
|
processing_system7_0_DDR_WEB_pin |
O |
1 |
processing_system7_0_DDR_WEB |
|
Unconnected
|
RESET |
I |
1 |
RESET |
RESET |