Carmel (MAXREFDES18#) Code Documentation  V01.00
High Accuracy Analog Current/Voltage Output
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platform.c
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1 /*
2  * Copyright (c) 2010-2011 Xilinx, Inc. All rights reserved.
3  *
4  * Xilinx, Inc.
5  * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
6  * COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
7  * ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
8  * STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
9  * IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
10  * FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
11  * XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
12  * THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
13  * ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
14  * FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
15  * AND FITNESS FOR A PARTICULAR PURPOSE.
16  *
17  */
18 
19 #include "xparameters.h"
20 #include "xil_cache.h"
21 
22 #include "platform_config.h"
23 
24 #ifdef STDOUT_IS_16550
25 #include "xuartns550_l.h"
26 #endif
27 
28 #define UART_BAUD 9600
29 
30 void
32 {
33 #ifdef __PPC__
34  Xil_ICacheEnableRegion(CACHEABLE_REGION_MASK);
35  Xil_DCacheEnableRegion(CACHEABLE_REGION_MASK);
36 #elif __MICROBLAZE__
37 #ifdef XPAR_MICROBLAZE_USE_ICACHE
38  Xil_ICacheEnable();
39 #endif
40 #ifdef XPAR_MICROBLAZE_USE_DCACHE
41  Xil_DCacheEnable();
42 #endif
43 #endif
44 }
45 
46 void
48 {
49  Xil_DCacheDisable();
50  Xil_ICacheDisable();
51 }
52 
53 void
55 {
56 #ifdef STDOUT_IS_16550
57  XUartNs550_SetBaud(STDOUT_BASEADDR, XPAR_XUARTNS550_CLOCK_HZ, UART_BAUD);
58  XUartNs550_SetLineControlReg(STDOUT_BASEADDR, XUN_LCR_8_DATA_BITS);
59 #endif
60 }
61 
62 void
64 {
65  enable_caches();
66  init_uart();
67 }
68 
69 void
71 {
73 }