top Project Status (08/12/2012 - 19:21:32)
Project File: top.xise Parser Errors: No Errors
Module Name: top Implementation State: Programming File Generated
Target Device: xc7z020-2clg484
  • Errors:
 
Product Version:ISE 14.2
  • Warnings:
 
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
XPS Reports [-]
Report NameGenerated ErrorsWarningsInfos
Platgen Log FileFri Aug 23 12:51:47 2013054 Warnings (48 new)8 Infos (0 new)
Simgen Log File    
BitInit Log FileFri Aug 23 13:01:17 2013023 Warnings (23 new)4 Infos (0 new)
System Log File    
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 3,169 106,400 2%  
    Number used as Flip Flops 3,161      
    Number used as Latches 8      
    Number used as Latch-thrus 0      
    Number used as AND/OR logics 0      
Number of Slice LUTs 4,462 53,200 8%  
    Number used as logic 4,172 53,200 7%  
        Number using O6 output only 3,493      
        Number using O5 output only 12      
        Number using O5 and O6 667      
        Number used as ROM 0      
    Number used as Memory 224 17,400 1%  
        Number used as Dual Port RAM 0      
        Number used as Single Port RAM 0      
        Number used as Shift Register 224      
            Number using O6 output only 176      
            Number using O5 output only 0      
            Number using O5 and O6 48      
    Number used exclusively as route-thrus 66      
        Number with same-slice register load 39      
        Number with same-slice carry load 20      
        Number with other load 7      
Number of occupied Slices 1,885 13,300 14%  
Number of LUT Flip Flop pairs used 5,026      
    Number with an unused Flip Flop 2,096 5,026 41%  
    Number with an unused LUT 564 5,026 11%  
    Number of fully used LUT-FF pairs 2,366 5,026 47%  
    Number of unique control sets 338      
    Number of slice register sites lost
        to control set restrictions
1,183 106,400 1%  
Number of bonded IOBs 47 200 23%  
    Number of LOCed IOBs 47 47 100%  
Number of bonded IOPAD 130 130 100%  
    IOB Flip Flops 4      
Number of RAMB36E1/FIFO36E1s 0 140 0%  
Number of RAMB18E1/FIFO18E1s 0 280 0%  
Number of BUFG/BUFGCTRLs 1 32 3%  
    Number used as BUFGs 1      
    Number used as BUFGCTRLs 0      
Number of IDELAYE2/IDELAYE2_FINEDELAYs 0 200 0%  
Number of ILOGICE2/ILOGICE3/ISERDESE2s 4 200 2%  
    Number used as ILOGICE2s 4      
Number used as    ILOGICE3s 0      
    Number used as ISERDESE2s 0      
Number of ODELAYE2/ODELAYE2_FINEDELAYs 0      
Number of OLOGICE2/OLOGICE3/OSERDESE2s 8 200 4%  
    Number used as OLOGICE2s 8      
    Number used as OLOGICE3s 0      
    Number used as OSERDESE2s 0      
Number of PHASER_IN/PHASER_IN_PHYs 0 16 0%  
Number of PHASER_OUT/PHASER_OUT_PHYs 0 16 0%  
Number of BSCANs 0 4 0%  
Number of BUFHCEs 0 72 0%  
Number of BUFRs 0 16 0%  
Number of CAPTUREs 0 1 0%  
Number of DNA_PORTs 0 1 0%  
Number of DSP48E1s 0 220 0%  
Number of EFUSE_USRs 0 1 0%  
Number of FRAME_ECCs 0 1 0%  
Number of ICAPs 0 2 0%  
Number of IDELAYCTRLs 0 4 0%  
Number of IN_FIFOs 0 16 0%  
Number of MMCME2_ADVs 0 4 0%  
Number of OUT_FIFOs 0 16 0%  
Number of PHASER_REFs 0 4 0%  
Number of PHY_CONTROLs 0 4 0%  
Number of PLLE2_ADVs 0 4 0%  
Number of PS7s 1 1 100%  
Number of STARTUPs 0 1 0%  
Number of XADCs 0 1 0%  
Average Fanout of Non-Clock Nets 4.04      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentFri Aug 23 12:54:30 2013048 Warnings (0 new)597 Infos (580 new)
Translation ReportCurrentFri Aug 23 12:55:38 20130143 Warnings (0 new)3 Infos (0 new)
Map ReportCurrentFri Aug 23 12:57:37 2013   
Place and Route ReportCurrentFri Aug 23 12:58:48 201303 Warnings (0 new)1 Info (0 new)
Power Report     
Post-PAR Static Timing ReportCurrentFri Aug 23 12:59:21 2013003 Infos (0 new)
Bitgen ReportCurrentFri Aug 23 13:00:50 201301 Warning (0 new)1 Info (0 new)
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentFri Aug 23 13:00:51 2013
WebTalk Log FileCurrentFri Aug 23 13:01:04 2013

Date Generated: 08/27/2013 - 17:41:24