top Project Status | |||
Project File: | top.xise | Parser Errors: | No Errors |
Module Name: | top | Implementation State: | New |
Target Device: | xc6slx9-2csg324 |
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Product Version: | ISE 14.2 |
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Design Goal: | Balanced |
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Design Strategy: | Xilinx Default (unlocked) |
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Environment: | System Settings |
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XPS Reports | [-] | ||||
Report Name | Generated | Errors | Warnings | Infos | |
Platgen Log File | Tue Aug 27 17:07:56 2013 | 0 | 0 | 28 Infos (28 new) | |
Simgen Log File | |||||
BitInit Log File | Tue Aug 27 18:06:18 2013 | 0 | 0 | 11 Infos (11 new) | |
System Log File |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | ||||||
Translation Report | ||||||
Map Report | ||||||
Place and Route Report | ||||||
Power Report | ||||||
Post-PAR Static Timing Report | ||||||
Bitgen Report |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
WebTalk Report | Current | Tue Aug 27 18:05:47 2013 | |
WebTalk Log File | Current | Tue Aug 27 18:05:59 2013 |