Printable Version
Overview
Resources Used
1   Processing System
2   AXI Interconnect
1   AXI to AXI Connector
7   AXI General Purpose IO
4   AXI IIC Interface
4   AXI SPI Interface
4   AXI UART (Lite)
Specifics
Generated Fri Aug 23 13:03:26 2013
EDK Version 14.2
Device Family zynq
Device xc7z020clg484-2

Block Diagram TOP

BlockDiagram
External Ports TOP

These are the external ports defined in the MHS file.
Attributes Key
The attributes are obtained from the SIGIS and IOB_STATE parameters set on the PORT in the MHS file
CLK  indicates Clock ports, (SIGIS = CLK) 
INTR  indicates Interrupt ports,(SIGIS = INTR) 
RESET  indicates Reset ports, (SIGIS = RST) 
BUF or REG  Indicates ports that instantiate or infer IOB primitives, (IOB_STATE = BUF or REG) 
# NAME DIR [LSB:MSB] SIG ATTRIBUTES
axi_gpio_0 axi_gpio_0_GPIO_IO_I_pin I 0:7 axi_gpio_0_GPIO_IO_I
axi_gpio_0 axi_gpio_0_GPIO_IO_O_pin O 0:7 axi_gpio_0_GPIO_IO_O
axi_gpio_0 axi_gpio_0_GPIO_IO_T_pin O 0:7 axi_gpio_0_GPIO_IO_T
axi_gpio_1 axi_gpio_1_GPIO_IO_I_pin I 0:7 axi_gpio_1_GPIO_IO_I
axi_gpio_1 axi_gpio_1_GPIO_IO_O_pin O 0:7 axi_gpio_1_GPIO_IO_O
axi_gpio_1 axi_gpio_1_GPIO_IO_T_pin O 0:7 axi_gpio_1_GPIO_IO_T
axi_gpio_2 axi_gpio_2_GPIO_IO_I_pin I 0:7 axi_gpio_2_GPIO_IO_I
axi_gpio_2 axi_gpio_2_GPIO_IO_O_pin O 0:7 axi_gpio_2_GPIO_IO_O
axi_gpio_2 axi_gpio_2_GPIO_IO_T_pin O 0:7 axi_gpio_2_GPIO_IO_T
axi_gpio_3 axi_gpio_3_GPIO_IO_I_pin I 0:7 axi_gpio_3_GPIO_IO_I
axi_gpio_3 axi_gpio_3_GPIO_IO_O_pin O 0:7 axi_gpio_3_GPIO_IO_O
axi_gpio_3 axi_gpio_3_GPIO_IO_T_pin O 0:7 axi_gpio_3_GPIO_IO_T
axi_gpio_led axi_gpio_led_GPIO_IO_O_pin O 0:7 axi_gpio_led_GPIO_IO_O
axi_gpio_oled axi_gpio_oled_GPIO_IO_O_pin O 0:7 axi_gpio_4_GPIO_IO_O
axi_gpio_pmodPortMux axi_gpio_pmodPortMux_GPIO_IO_O_pin O 0:7 axi_gpio_pmodPortMux_GPIO_IO_O
axi_iic_0 axi_iic_0_Scl_I_pin I 1 axi_iic_0_Scl_I
axi_iic_0 axi_iic_0_Sda_I_pin I 1 axi_iic_0_Sda_I
axi_iic_0 axi_iic_0_Scl_O_pin O 1 axi_iic_0_Scl_O
axi_iic_0 axi_iic_0_Scl_T_pin O 1 axi_iic_0_Scl_T
axi_iic_0 axi_iic_0_Sda_O_pin O 1 axi_iic_0_Sda_O
axi_iic_0 axi_iic_0_Sda_T_pin O 1 axi_iic_0_Sda_T
axi_iic_1 axi_iic_1_Scl_I_pin I 1 axi_iic_1_Scl_I
axi_iic_1 axi_iic_1_Sda_I_pin I 1 axi_iic_1_Sda_I
axi_iic_1 axi_iic_1_Scl_O_pin O 1 axi_iic_1_Scl_O
axi_iic_1 axi_iic_1_Scl_T_pin O 1 axi_iic_1_Scl_T
axi_iic_1 axi_iic_1_Sda_O_pin O 1 axi_iic_1_Sda_O
axi_iic_1 axi_iic_1_Sda_T_pin O 1 axi_iic_1_Sda_T
axi_iic_2 axi_iic_2_Scl_I_pin I 1 axi_iic_2_Scl_I
axi_iic_2 axi_iic_2_Sda_I_pin I 1 axi_iic_2_Sda_I
axi_iic_2 axi_iic_2_Scl_O_pin O 1 axi_iic_2_Scl_O
axi_iic_2 axi_iic_2_Scl_T_pin O 1 axi_iic_2_Scl_T
axi_iic_2 axi_iic_2_Sda_O_pin O 1 axi_iic_2_Sda_O
axi_iic_2 axi_iic_2_Sda_T_pin O 1 axi_iic_2_Sda_T
axi_iic_3 axi_iic_3_Scl_I_pin I 1 axi_iic_3_Scl_I
axi_iic_3 axi_iic_3_Sda_I_pin I 1 axi_iic_3_Sda_I
axi_iic_3 axi_iic_3_Scl_O_pin O 1 axi_iic_3_Scl_O
axi_iic_3 axi_iic_3_Scl_T_pin O 1 axi_iic_3_Scl_T
axi_iic_3 axi_iic_3_Sda_O_pin O 1 axi_iic_3_Sda_O
axi_iic_3 axi_iic_3_Sda_T_pin O 1 axi_iic_3_Sda_T
axi_spi_0 axi_spi_0_MISO_I_pin I 1 axi_spi_0_MISO_I
axi_spi_0 axi_spi_0_MOSI_O_pin O 1 axi_spi_0_MOSI_O
axi_spi_0 axi_spi_0_SCK_O_pin O 1 axi_spi_0_SCK_O
axi_spi_0 axi_spi_0_SS_O_pin O 0:1 axi_spi_0_SS_O
axi_spi_1 axi_spi_1_MISO_I_pin I 1 axi_spi_1_MISO_I
axi_spi_1 axi_spi_1_MOSI_O_pin O 1 axi_spi_1_MOSI_O
axi_spi_1 axi_spi_1_SCK_O_pin O 1 axi_spi_1_SCK_O
axi_spi_1 axi_spi_1_SS_O_pin O 0:0 axi_spi_1_SS_O
axi_spi_2 axi_spi_2_MISO_I_pin I 1 axi_spi_2_MISO_I
axi_spi_2 axi_spi_2_MOSI_O_pin O 1 axi_spi_2_MOSI_O
axi_spi_2 axi_spi_2_SCK_O_pin O 1 axi_spi_2_SCK_O
axi_spi_2 axi_spi_2_SS_O_pin O 0:0 axi_spi_2_SS_O
axi_spi_3 axi_spi_3_MISO_I_pin I 1 axi_spi_3_MISO_I
axi_spi_3 axi_spi_3_MOSI_O_pin O 1 axi_spi_3_MOSI_O
axi_spi_3 axi_spi_3_SCK_O_pin O 1 axi_spi_3_SCK_O
axi_spi_3 axi_spi_3_SS_O_pin O 0:0 axi_spi_3_SS_O
axi_uartlite_0 axi_uartlite_0_RX_pin I 1 axi_uartlite_0_RX
axi_uartlite_0 axi_uartlite_0_TX_pin O 1 axi_uartlite_0_TX
axi_uartlite_1 axi_uartlite_1_RX_pin I 1 axi_uartlite_1_RX
axi_uartlite_1 axi_uartlite_1_TX_pin O 1 axi_uartlite_1_TX
axi_uartlite_2 axi_uartlite_2_RX_pin I 1 axi_uartlite_2_RX
axi_uartlite_2 axi_uartlite_2_TX_pin O 1 axi_uartlite_2_TX
axi_uartlite_3 axi_uartlite_3_RX_pin I 1 axi_uartlite_3_RX
axi_uartlite_3 axi_uartlite_3_TX_pin O 1 axi_uartlite_3_TX
processing_system7_0 processing_system7_0_PS_CLK_pin I 1 processing_system7_0_PS_CLK  CLK 
processing_system7_0 processing_system7_0_PS_PORB_pin I 1 processing_system7_0_PS_PORB
processing_system7_0 processing_system7_0_PS_SRSTB_pin I 1 processing_system7_0_PS_SRSTB
processing_system7_0 processing_system7_0_DDR_Addr IO 0:14 processing_system7_0_DDR_Addr
processing_system7_0 processing_system7_0_DDR_BankAddr IO 0:2 processing_system7_0_DDR_BankAddr
processing_system7_0 processing_system7_0_DDR_CAS_n IO 1 processing_system7_0_DDR_CAS_n
processing_system7_0 processing_system7_0_DDR_CKE IO 1 processing_system7_0_DDR_CKE
processing_system7_0 processing_system7_0_DDR_CS_n IO 1 processing_system7_0_DDR_CS_n
processing_system7_0 processing_system7_0_DDR_Clk IO 1 processing_system7_0_DDR_Clk  CLK 
processing_system7_0 processing_system7_0_DDR_Clk_n IO 1 processing_system7_0_DDR_Clk_n  CLK 
processing_system7_0 processing_system7_0_DDR_DM IO 0:3 processing_system7_0_DDR_DM
processing_system7_0 processing_system7_0_DDR_DQ IO 0:31 processing_system7_0_DDR_DQ
processing_system7_0 processing_system7_0_DDR_DQS IO 0:3 processing_system7_0_DDR_DQS
processing_system7_0 processing_system7_0_DDR_DQS_n IO 0:3 processing_system7_0_DDR_DQS_n
processing_system7_0 processing_system7_0_DDR_DRSTB IO 1 processing_system7_0_DDR_DRSTB  RESET 
processing_system7_0 processing_system7_0_DDR_ODT IO 1 processing_system7_0_DDR_ODT
processing_system7_0 processing_system7_0_DDR_RAS_n IO 1 processing_system7_0_DDR_RAS_n
processing_system7_0 processing_system7_0_DDR_VRN IO 1 processing_system7_0_DDR_VRN
processing_system7_0 processing_system7_0_DDR_VRP IO 1 processing_system7_0_DDR_VRP
processing_system7_0 processing_system7_0_MIO IO 0:53 processing_system7_0_MIO
processing_system7_0 processing_system7_0_DDR_WEB_pin O 1 processing_system7_0_DDR_WEB
Unconnected RESET I 1 RESET  RESET 


Processors TOP

processing_system7_0   Processing System
Processing System wrapper for Series 7

IP Specs
Core Version
processing_system7 4.00.a


processing_system7_0 IP Image
PORT LIST
These are the ports listed in the MHS file.
# NAME DIR [LSB:MSB] SIGNAL
0 MIO IO 1 processing_system7_0_MIO
1 PS_SRSTB I 1 processing_system7_0_PS_SRSTB
2 PS_CLK I 1 processing_system7_0_PS_CLK
3 PS_PORB I 1 processing_system7_0_PS_PORB
4 DDR_Clk IO 1 processing_system7_0_DDR_Clk
5 DDR_Clk_n IO 1 processing_system7_0_DDR_Clk_n
6 DDR_CKE IO 1 processing_system7_0_DDR_CKE
7 DDR_CS_n IO 1 processing_system7_0_DDR_CS_n
8 DDR_RAS_n IO 1 processing_system7_0_DDR_RAS_n
9 DDR_CAS_n IO 1 processing_system7_0_DDR_CAS_n
10 DDR_WEB O 1 processing_system7_0_DDR_WEB
11 DDR_BankAddr IO 1 processing_system7_0_DDR_BankAddr
12 DDR_Addr IO 1 processing_system7_0_DDR_Addr
13 DDR_ODT IO 1 processing_system7_0_DDR_ODT
14 DDR_DRSTB IO 1 processing_system7_0_DDR_DRSTB
15 DDR_DQ IO 1 processing_system7_0_DDR_DQ
16 DDR_DM IO 1 processing_system7_0_DDR_DM
17 DDR_DQS IO 1 processing_system7_0_DDR_DQS
18 DDR_DQS_n IO 1 processing_system7_0_DDR_DQS_n
19 DDR_VRN IO 1 processing_system7_0_DDR_VRN
20 DDR_VRP IO 1 processing_system7_0_DDR_VRP
21 FCLK_CLK0 O 1 processing_system7_0_FCLK_CLK0
22 FCLK_RESET0_N O 1 processing_system7_0_FCLK_RESET0_N
23 M_AXI_GP0_ACLK I 1 processing_system7_0_FCLK_CLK0
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
M_AXI_GP0 MASTER AXI axi_interconnect_1 16 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_EN_EMIO_CAN0 0
C_EN_EMIO_CAN1 0
C_EN_EMIO_ENET0 0
C_EN_EMIO_ENET1 0
C_EN_EMIO_GPIO 0
C_EN_EMIO_I2C0 0
C_EN_EMIO_I2C1 0
C_EN_EMIO_PJTAG 0
C_EN_EMIO_SDIO0 0
C_EN_EMIO_CD_SDIO0 0
C_EN_EMIO_WP_SDIO0 0
C_EN_EMIO_SDIO1 0
C_EN_EMIO_CD_SDIO1 0
C_EN_EMIO_WP_SDIO1 0
C_EN_EMIO_SPI0 0
C_EN_EMIO_SPI1 0
C_EN_EMIO_UART0 0
C_EN_EMIO_UART1 0
C_EN_EMIO_MODEM_UART0 0
C_EN_EMIO_MODEM_UART1 0
C_EN_EMIO_TTC0 0
C_EN_EMIO_TTC1 0
C_EN_EMIO_WDT 0
C_EN_EMIO_TRACE 0
C_USE_M_AXI_GP0 1
C_USE_M_AXI_GP1 0
C_USE_S_AXI_GP0 0
C_USE_S_AXI_GP1 0
C_USE_S_AXI_ACP 0
C_USE_S_AXI_HP0 0
C_USE_S_AXI_HP1 0
C_USE_S_AXI_HP2 0
C_USE_S_AXI_HP3 0
C_S_AXI_GP0_ENABLE_LOWOCM_DDR 0
C_S_AXI_GP1_ENABLE_LOWOCM_DDR 0
C_S_AXI_ACP_ENABLE_HIGHOCM 0
C_S_AXI_HP0_ENABLE_HIGHOCM 0
C_S_AXI_HP1_ENABLE_HIGHOCM 0
C_S_AXI_HP2_ENABLE_HIGHOCM 0
C_S_AXI_HP3_ENABLE_HIGHOCM 0
C_USE_DMA0 0
C_USE_DMA1 0
C_USE_DMA2 0
C_USE_DMA3 0
C_USE_TRACE 0
C_USE_CROSS_TRIGGER 0
C_USE_CR_FABRIC 1
C_USE_AXI_FABRIC_IDLE 0
C_USE_DDR_BYPASS 0
C_USE_FABRIC_INTERRUPT 1
C_USE_PROC_EVENT_BUS 0
C_EN_EMIO_SRAM_INT 0
C_EMIO_GPIO_WIDTH 64
C_INCLUDE_ACP_TRANS_CHECK 0
C_PS7_SI_REV PRODUCTION
C_DDR_RAM_BASEADDR 0x00000000
C_DDR_RAM_HIGHADDR 0x1FFFFFFF
C_UART0_BASEADDR 0xE0000000
C_UART0_HIGHADDR 0xE0000FFF
C_UART1_BASEADDR 0xE0001000
C_UART1_HIGHADDR 0xE0001FFF
C_I2C0_BASEADDR 0xE0004000
C_I2C0_HIGHADDR 0xE0004FFF
C_I2C1_BASEADDR 0xE0005000
C_I2C1_HIGHADDR 0xE0005FFF
C_SPI0_BASEADDR 0xE0006000
C_SPI0_HIGHADDR 0xE0006FFF
C_SPI1_BASEADDR 0xE0007000
C_SPI1_HIGHADDR 0xE0007FFF
C_CAN0_BASEADDR 0xE0008000
C_CAN0_HIGHADDR 0xE0008FFF
C_CAN1_BASEADDR 0xE0009000
C_CAN1_HIGHADDR 0xE0009FFF
C_GPIO_BASEADDR 0xE000A000
C_GPIO_HIGHADDR 0xE000AFFF
C_ENET0_BASEADDR 0xE000B000
C_ENET0_HIGHADDR 0xE000BFFF
C_ENET1_BASEADDR 0xE000C000
C_ENET1_HIGHADDR 0xE000CFFF
C_SDIO0_BASEADDR 0xE0100000
C_SDIO0_HIGHADDR 0xE0100FFF
C_SDIO1_BASEADDR 0xE0101000
C_SDIO1_HIGHADDR 0xE0101FFF
C_USB0_BASEADDR 0xE0102000
C_USB0_HIGHADDR 0xE0102FFF
C_USB1_BASEADDR 0xE0103000
C_USB1_HIGHADDR 0xE0103FFF
C_TTC0_BASEADDR 0xE0104000
C_TTC0_HIGHADDR 0xE0104FFF
C_TTC1_BASEADDR 0xE0105000
C_TTC1_HIGHADDR 0xE0105FFF
C_M_AXI_GP0_PROTOCOL AXI3
C_M_AXI_GP0_ID_WIDTH 12
C_M_AXI_GP0_ADDR_WIDTH 32
C_M_AXI_GP0_DATA_WIDTH 32
C_M_AXI_GP0_ENABLE_STATIC_REMAP 0
C_M_AXI_GP0_SUPPORTS_NARROW_BURST 0
C_M_AXI_GP0_SUPPORTS_REORDERING 0
C_INTERCONNECT_M_AXI_GP0_WRITE_ISSUING 8
C_INTERCONNECT_M_AXI_GP0_READ_ISSUING 8
C_M_AXI_GP1_PROTOCOL AXI3
C_M_AXI_GP1_ID_WIDTH 12
C_M_AXI_GP1_ADDR_WIDTH 32
C_M_AXI_GP1_DATA_WIDTH 32
C_M_AXI_GP1_ENABLE_STATIC_REMAP 0
C_M_AXI_GP1_SUPPORTS_NARROW_BURST 0
C_M_AXI_GP1_SUPPORTS_REORDERING 0
C_INTERCONNECT_M_AXI_GP1_WRITE_ISSUING 8
C_INTERCONNECT_M_AXI_GP1_READ_ISSUING 8
C_S_AXI_GP0_PROTOCOL AXI3
 
Name Value
C_S_AXI_GP0_ID_WIDTH 6
C_S_AXI_GP0_ADDR_WIDTH 32
C_S_AXI_GP0_DATA_WIDTH 32
C_INTERCONNECT_S_AXI_GP0_WRITE_ACCEPTANCE 8
C_INTERCONNECT_S_AXI_GP0_READ_ACCEPTANCE 8
C_S_AXI_GP1_PROTOCOL AXI3
C_S_AXI_GP1_ID_WIDTH 6
C_S_AXI_GP1_ADDR_WIDTH 32
C_S_AXI_GP1_DATA_WIDTH 32
C_INTERCONNECT_S_AXI_GP1_WRITE_ACCEPTANCE 8
C_INTERCONNECT_S_AXI_GP1_READ_ACCEPTANCE 8
C_S_AXI_ACP_PROTOCOL AXI3
C_S_AXI_ACP_ID_WIDTH 3
C_S_AXI_ACP_ADDR_WIDTH 32
C_S_AXI_ACP_DATA_WIDTH 64
C_S_AXI_ACP_SUPPORTS_USER_SIGNALS 1
C_S_AXI_ACP_ARUSER_WIDTH 5
C_S_AXI_ACP_AWUSER_WIDTH 5
C_INTERCONNECT_S_AXI_ACP_WRITE_ACCEPTANCE 8
C_INTERCONNECT_S_AXI_ACP_READ_ACCEPTANCE 8
C_S_AXI_HP0_PROTOCOL AXI3
C_S_AXI_HP0_ID_WIDTH 6
C_S_AXI_HP0_ADDR_WIDTH 32
C_S_AXI_HP0_DATA_WIDTH 64
C_INTERCONNECT_S_AXI_HP0_WRITE_ACCEPTANCE 8
C_INTERCONNECT_S_AXI_HP0_READ_ACCEPTANCE 8
C_S_AXI_HP1_PROTOCOL AXI3
C_S_AXI_HP1_ID_WIDTH 6
C_S_AXI_HP1_ADDR_WIDTH 32
C_S_AXI_HP1_DATA_WIDTH 64
C_INTERCONNECT_S_AXI_HP1_WRITE_ACCEPTANCE 8
C_INTERCONNECT_S_AXI_HP1_READ_ACCEPTANCE 8
C_S_AXI_HP2_PROTOCOL AXI3
C_S_AXI_HP2_ID_WIDTH 6
C_S_AXI_HP2_ADDR_WIDTH 32
C_S_AXI_HP2_DATA_WIDTH 64
C_INTERCONNECT_S_AXI_HP2_WRITE_ACCEPTANCE 8
C_INTERCONNECT_S_AXI_HP2_READ_ACCEPTANCE 8
C_S_AXI_HP3_PROTOCOL AXI3
C_S_AXI_HP3_ID_WIDTH 6
C_S_AXI_HP3_ADDR_WIDTH 32
C_S_AXI_HP3_DATA_WIDTH 64
C_INTERCONNECT_S_AXI_HP3_WRITE_ACCEPTANCE 8
C_INTERCONNECT_S_AXI_HP3_READ_ACCEPTANCE 8
C_S_AXI_GP0_BASEADDR 0xE0000000
C_S_AXI_GP0_HIGHADDR 0xFFFFFFFF
C_S_AXI_GP0_LOWOCM_DDR_BASEADDR 0x00000000
C_S_AXI_GP0_LOWOCM_DDR_HIGHADDR 0x3FFFFFFF
C_S_AXI_GP1_BASEADDR 0xE0000000
C_S_AXI_GP1_HIGHADDR 0xFFFFFFFF
C_S_AXI_GP1_LOWOCM_DDR_BASEADDR 0x00000000
C_S_AXI_GP1_LOWOCM_DDR_HIGHADDR 0x3FFFFFFF
C_S_AXI_ACP_BASEADDR 0x00000000
C_S_AXI_ACP_HIGHADDR 0x3FFFFFFF
C_S_AXI_ACP_HIGHOCM_BASEADDR 0xFFFC0000
C_S_AXI_ACP_HIGHOCM_HIGHADDR 0xFFFFFFFF
C_S_AXI_HP0_BASEADDR 0x00000000
C_S_AXI_HP0_HIGHADDR 0x3FFFFFFF
C_S_AXI_HP0_HIGHOCM_BASEADDR 0xFFFC0000
C_S_AXI_HP0_HIGHOCM_HIGHADDR 0xFFFFFFFF
C_S_AXI_HP1_BASEADDR 0x00000000
C_S_AXI_HP1_HIGHADDR 0x3FFFFFFF
C_S_AXI_HP1_HIGHOCM_BASEADDR 0xFFFC0000
C_S_AXI_HP1_HIGHOCM_HIGHADDR 0xFFFFFFFF
C_S_AXI_HP2_BASEADDR 0x00000000
C_S_AXI_HP2_HIGHADDR 0x3FFFFFFF
C_S_AXI_HP2_HIGHOCM_BASEADDR 0xFFFC0000
C_S_AXI_HP2_HIGHOCM_HIGHADDR 0xFFFFFFFF
C_S_AXI_HP3_BASEADDR 0x00000000
C_S_AXI_HP3_HIGHADDR 0x3FFFFFFF
C_S_AXI_HP3_HIGHOCM_BASEADDR 0xFFFC0000
C_S_AXI_HP3_HIGHOCM_HIGHADDR 0xFFFFFFFF
C_M_AXI_GP0_SUPPORTS_THREADS 1
C_M_AXI_GP0_THREAD_ID_WIDTH 12
C_M_AXI_GP1_SUPPORTS_THREADS 1
C_M_AXI_GP1_THREAD_ID_WIDTH 12
C_NUM_F2P_INTR_INPUTS 2
C_EN_DDR 1
C_EN_SMC 0
C_EN_QSPI 1
C_EN_CAN0 0
C_EN_CAN1 0
C_EN_ENET0 0
C_EN_ENET1 0
C_EN_GPIO 0
C_EN_I2C0 0
C_EN_I2C1 0
C_EN_PJTAG 0
C_EN_SDIO0 1
C_EN_SDIO1 0
C_EN_SPI0 0
C_EN_SPI1 0
C_EN_UART0 0
C_EN_UART1 1
C_EN_MODEM_UART0 0
C_EN_MODEM_UART1 0
C_EN_TTC0 0
C_EN_TTC1 0
C_EN_WDT 0
C_EN_TRACE 0
C_EN_USB0 0
C_EN_USB1 0
C_FCLK_CLK0_FREQ 100000000
C_FCLK_CLK1_FREQ 145454544
C_FCLK_CLK2_FREQ 50000000
C_FCLK_CLK3_FREQ 50000000
C_FCLK_CLK0_BUF TRUE
C_FCLK_CLK1_BUF TRUE
C_FCLK_CLK2_BUF TRUE
C_FCLK_CLK3_BUF TRUE
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.




Busses TOP

axi_interconnect_1   AXI Interconnect
AXI4 Memory-Mapped Interconnect

IP Specs
Core Version Documentation
axi_interconnect 1.06.a IP


axi_interconnect_1 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 INTERCONNECT_ACLK I 1 processing_system7_0_FCLK_CLK0
1 INTERCONNECT_ARESETN I 1 processing_system7_0_FCLK_RESET0_N
Bus Connections
INSTANCE INTERFACE TYPE INTERFACE NAME
processing_system7_0 MASTER M_AXI_GP0
axi_gpio_0 SLAVE S_AXI
axi_iic_0 SLAVE S_AXI
axi_spi_0 SLAVE S_AXI
axi_uartlite_0 SLAVE S_AXI
axi_gpio_led SLAVE S_AXI
axi_gpio_pmodPortMux SLAVE S_AXI
axi_gpio_1 SLAVE S_AXI
axi_gpio_2 SLAVE S_AXI
axi_gpio_3 SLAVE S_AXI
axi_uartlite_1 SLAVE S_AXI
axi_uartlite_2 SLAVE S_AXI
axi_uartlite_3 SLAVE S_AXI
axi_iic_2 SLAVE S_AXI
axi_iic_3 SLAVE S_AXI
axi2axi_connector_1 SLAVE S_AXI
axi_iic_1 SLAVE S_AXI


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY rtl
C_BASEFAMILY rtl
C_NUM_SLAVE_SLOTS 1
C_NUM_MASTER_SLOTS 1
C_AXI_ID_WIDTH 1
C_AXI_ADDR_WIDTH 32
C_AXI_DATA_MAX_WIDTH 32
C_S_AXI_DATA_WIDTH 0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020
C_M_AXI_DATA_WIDTH 0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020
C_INTERCONNECT_DATA_WIDTH 32
C_S_AXI_PROTOCOL 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_PROTOCOL 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_BASE_ADDR 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
C_M_AXI_HIGH_ADDR 0x0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_BASE_ID 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_THREAD_ID_WIDTH 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_IS_INTERCONNECT 0b0000000000000000
C_S_AXI_ACLK_RATIO 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_IS_ACLK_ASYNC 0b0000000000000000
C_M_AXI_ACLK_RATIO 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_IS_ACLK_ASYNC 0b0000000000000000
C_INTERCONNECT_ACLK_RATIO 1
C_S_AXI_SUPPORTS_WRITE 0b1111111111111111
C_S_AXI_SUPPORTS_READ 0b1111111111111111
C_M_AXI_SUPPORTS_WRITE 0b1111111111111111
C_M_AXI_SUPPORTS_READ 0b1111111111111111
C_AXI_SUPPORTS_USER_SIGNALS 0
C_AXI_AWUSER_WIDTH 1
C_AXI_ARUSER_WIDTH 1
C_AXI_WUSER_WIDTH 1
C_AXI_RUSER_WIDTH 1
C_AXI_BUSER_WIDTH 1
C_AXI_CONNECTIVITY 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
C_S_AXI_SINGLE_THREAD 0b0000000000000000
C_M_AXI_SUPPORTS_REORDERING 0b1111111111111111
C_S_AXI_SUPPORTS_NARROW_BURST 0b1111111111111111
C_M_AXI_SUPPORTS_NARROW_BURST 0b1111111111111111
C_S_AXI_WRITE_ACCEPTANCE 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_READ_ACCEPTANCE 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_WRITE_ISSUING 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
 
Name Value
C_M_AXI_READ_ISSUING 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_ARB_PRIORITY 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_SECURE 0b0000000000000000
C_S_AXI_WRITE_FIFO_DEPTH 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_WRITE_FIFO_TYPE 0b1111111111111111
C_S_AXI_WRITE_FIFO_DELAY 0b0000000000000000
C_S_AXI_READ_FIFO_DEPTH 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_READ_FIFO_TYPE 0b1111111111111111
C_S_AXI_READ_FIFO_DELAY 0b0000000000000000
C_M_AXI_WRITE_FIFO_DEPTH 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_WRITE_FIFO_TYPE 0b1111111111111111
C_M_AXI_WRITE_FIFO_DELAY 0b0000000000000000
C_M_AXI_READ_FIFO_DEPTH 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_READ_FIFO_TYPE 0b1111111111111111
C_M_AXI_READ_FIFO_DELAY 0b0000000000000000
C_S_AXI_AW_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_AR_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_W_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_R_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_B_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_AW_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_AR_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_W_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_R_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_B_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_INTERCONNECT_R_REGISTER 0
C_INTERCONNECT_CONNECTIVITY_MODE 0
C_USE_CTRL_PORT 0
C_USE_INTERRUPT 1
C_RANGE_CHECK 2
C_S_AXI_CTRL_PROTOCOL AXI4LITE
C_S_AXI_CTRL_ADDR_WIDTH 32
C_S_AXI_CTRL_DATA_WIDTH 32
C_BASEADDR 0xFFFFFFFF
C_HIGHADDR 0x00000000
C_DEBUG 0
C_S_AXI_DEBUG_SLOT 0
C_M_AXI_DEBUG_SLOT 0
C_MAX_DEBUG_THREADS 1
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


axi_interconnect_2   AXI Interconnect
AXI4 Memory-Mapped Interconnect

IP Specs
Core Version Documentation
axi_interconnect 1.06.a IP


axi_interconnect_2 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 INTERCONNECT_ACLK I 1 processing_system7_0_FCLK_CLK0
1 INTERCONNECT_ARESETN I 1 processing_system7_0_FCLK_RESET0_N
Bus Connections
INSTANCE INTERFACE TYPE INTERFACE NAME
axi2axi_connector_1 MASTER M_AXI
axi_spi_1 SLAVE S_AXI
axi_spi_2 SLAVE S_AXI
axi_spi_3 SLAVE S_AXI
axi_gpio_oled SLAVE S_AXI


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY rtl
C_BASEFAMILY rtl
C_NUM_SLAVE_SLOTS 1
C_NUM_MASTER_SLOTS 1
C_AXI_ID_WIDTH 1
C_AXI_ADDR_WIDTH 32
C_AXI_DATA_MAX_WIDTH 32
C_S_AXI_DATA_WIDTH 0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020
C_M_AXI_DATA_WIDTH 0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020
C_INTERCONNECT_DATA_WIDTH 32
C_S_AXI_PROTOCOL 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_PROTOCOL 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_BASE_ADDR 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
C_M_AXI_HIGH_ADDR 0x0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_BASE_ID 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_THREAD_ID_WIDTH 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_IS_INTERCONNECT 0b0000000000000000
C_S_AXI_ACLK_RATIO 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_IS_ACLK_ASYNC 0b0000000000000000
C_M_AXI_ACLK_RATIO 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_IS_ACLK_ASYNC 0b0000000000000000
C_INTERCONNECT_ACLK_RATIO 1
C_S_AXI_SUPPORTS_WRITE 0b1111111111111111
C_S_AXI_SUPPORTS_READ 0b1111111111111111
C_M_AXI_SUPPORTS_WRITE 0b1111111111111111
C_M_AXI_SUPPORTS_READ 0b1111111111111111
C_AXI_SUPPORTS_USER_SIGNALS 0
C_AXI_AWUSER_WIDTH 1
C_AXI_ARUSER_WIDTH 1
C_AXI_WUSER_WIDTH 1
C_AXI_RUSER_WIDTH 1
C_AXI_BUSER_WIDTH 1
C_AXI_CONNECTIVITY 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
C_S_AXI_SINGLE_THREAD 0b0000000000000000
C_M_AXI_SUPPORTS_REORDERING 0b1111111111111111
C_S_AXI_SUPPORTS_NARROW_BURST 0b1111111111111111
C_M_AXI_SUPPORTS_NARROW_BURST 0b1111111111111111
C_S_AXI_WRITE_ACCEPTANCE 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_READ_ACCEPTANCE 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_WRITE_ISSUING 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
 
Name Value
C_M_AXI_READ_ISSUING 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_ARB_PRIORITY 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_SECURE 0b0000000000000000
C_S_AXI_WRITE_FIFO_DEPTH 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_WRITE_FIFO_TYPE 0b1111111111111111
C_S_AXI_WRITE_FIFO_DELAY 0b0000000000000000
C_S_AXI_READ_FIFO_DEPTH 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_READ_FIFO_TYPE 0b1111111111111111
C_S_AXI_READ_FIFO_DELAY 0b0000000000000000
C_M_AXI_WRITE_FIFO_DEPTH 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_WRITE_FIFO_TYPE 0b1111111111111111
C_M_AXI_WRITE_FIFO_DELAY 0b0000000000000000
C_M_AXI_READ_FIFO_DEPTH 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_READ_FIFO_TYPE 0b1111111111111111
C_M_AXI_READ_FIFO_DELAY 0b0000000000000000
C_S_AXI_AW_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_AR_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_W_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_R_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_B_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_AW_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_AR_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_W_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_R_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_B_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_INTERCONNECT_R_REGISTER 0
C_INTERCONNECT_CONNECTIVITY_MODE 0
C_USE_CTRL_PORT 0
C_USE_INTERRUPT 1
C_RANGE_CHECK 2
C_S_AXI_CTRL_PROTOCOL AXI4LITE
C_S_AXI_CTRL_ADDR_WIDTH 32
C_S_AXI_CTRL_DATA_WIDTH 32
C_BASEADDR 0xFFFFFFFF
C_HIGHADDR 0x00000000
C_DEBUG 0
C_S_AXI_DEBUG_SLOT 0
C_M_AXI_DEBUG_SLOT 0
C_MAX_DEBUG_THREADS 1
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.




Bridges TOP

axi2axi_connector_1   AXI to AXI Connector
Wire Bridge Between Two AXI Interconnects

IP Specs
Core Version Documentation
axi2axi_connector 1.00.a IP


axi2axi_connector_1 IP Image
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
M_AXI MASTER AXI axi_interconnect_2 4 Peripherals.
S_AXI SLAVE AXI axi_interconnect_1 16 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_S_AXI_ADDR_WIDTH 32
C_S_AXI_DATA_WIDTH 32
C_S_AXI_ACLK_FREQ_HZ 100000000
C_S_AXI_ID_WIDTH 1
C_S_AXI_PROTOCOL AXI4
C_S_AXI_SUPPORTS_NARROW_BURST 1
C_S_AXI_SUPPORTS_READ 1
C_S_AXI_SUPPORTS_WRITE 1
C_S_AXI_SUPPORTS_USER_SIGNALS 0
C_S_AXI_AWUSER_WIDTH 1
C_S_AXI_ARUSER_WIDTH 1
C_S_AXI_WUSER_WIDTH 1
C_S_AXI_RUSER_WIDTH 1
C_S_AXI_BUSER_WIDTH 1
C_INTERCONNECT_S_AXI_WRITE_ACCEPTANCE 8
C_INTERCONNECT_S_AXI_READ_ACCEPTANCE 8
C_M_AXI_ADDR_WIDTH 32
C_M_AXI_DATA_WIDTH 32
C_M_AXI_PROTOCOL AXI4
C_M_AXI_ACLK_FREQ_HZ 100000000
C_M_AXI_SUPPORTS_THREADS 1
C_M_AXI_THREAD_ID_WIDTH 1
C_M_AXI_SUPPORTS_NARROW_BURST 1
C_M_AXI_SUPPORTS_READ 1
C_M_AXI_SUPPORTS_WRITE 1
C_M_AXI_SUPPORTS_USER_SIGNALS 0
C_M_AXI_AWUSER_WIDTH 1
C_M_AXI_ARUSER_WIDTH 1
C_M_AXI_WUSER_WIDTH 1
C_M_AXI_RUSER_WIDTH 1
C_M_AXI_BUSER_WIDTH 1
C_INTERCONNECT_M_AXI_WRITE_ISSUING 8
C_INTERCONNECT_M_AXI_READ_ISSUING 8
 
Name Value
C_S_AXI_NUM_ADDR_RANGES 4
C_S_AXI_RNG00_BASEADDR 0x41380000
C_S_AXI_RNG01_BASEADDR 0x42040000
C_S_AXI_RNG02_BASEADDR 0x42080000
C_S_AXI_RNG03_BASEADDR 0x420C0000
C_S_AXI_RNG04_BASEADDR 0xFFFFFFFF
C_S_AXI_RNG05_BASEADDR 0xFFFFFFFF
C_S_AXI_RNG06_BASEADDR 0xFFFFFFFF
C_S_AXI_RNG07_BASEADDR 0xFFFFFFFF
C_S_AXI_RNG08_BASEADDR 0xFFFFFFFF
C_S_AXI_RNG09_BASEADDR 0xFFFFFFFF
C_S_AXI_RNG10_BASEADDR 0xFFFFFFFF
C_S_AXI_RNG11_BASEADDR 0xFFFFFFFF
C_S_AXI_RNG12_BASEADDR 0xFFFFFFFF
C_S_AXI_RNG13_BASEADDR 0xFFFFFFFF
C_S_AXI_RNG14_BASEADDR 0xFFFFFFFF
C_S_AXI_RNG15_BASEADDR 0xFFFFFFFF
C_S_AXI_RNG00_HIGHADDR 0x4138FFFF
C_S_AXI_RNG01_HIGHADDR 0x4204FFFF
C_S_AXI_RNG02_HIGHADDR 0x4208FFFF
C_S_AXI_RNG03_HIGHADDR 0x420CFFFF
C_S_AXI_RNG04_HIGHADDR 0x00000000
C_S_AXI_RNG05_HIGHADDR 0x00000000
C_S_AXI_RNG06_HIGHADDR 0x00000000
C_S_AXI_RNG07_HIGHADDR 0x00000000
C_S_AXI_RNG08_HIGHADDR 0x00000000
C_S_AXI_RNG09_HIGHADDR 0x00000000
C_S_AXI_RNG10_HIGHADDR 0x00000000
C_S_AXI_RNG11_HIGHADDR 0x00000000
C_S_AXI_RNG12_HIGHADDR 0x00000000
C_S_AXI_RNG13_HIGHADDR 0x00000000
C_S_AXI_RNG14_HIGHADDR 0x00000000
C_S_AXI_RNG15_HIGHADDR 0x00000000
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.




Peripherals TOP

axi_gpio_0   AXI General Purpose IO
General Purpose Input/Output (GPIO) core for the AXI bus.

IP Specs
Core Version Documentation
axi_gpio 1.01.b IP


axi_gpio_0 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 S_AXI_ACLK I 1 processing_system7_0_FCLK_CLK0
1 GPIO_IO_O O 1 axi_gpio_0_GPIO_IO_O
2 GPIO_IO_I I 1 axi_gpio_0_GPIO_IO_I
3 GPIO_IO_T O 1 axi_gpio_0_GPIO_IO_T
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
S_AXI SLAVE AXI axi_interconnect_1 16 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex6
C_INSTANCE axi_gpio_inst
C_BASEADDR 0x41200000
C_HIGHADDR 0x4120FFFF
C_S_AXI_ADDR_WIDTH 9
C_S_AXI_DATA_WIDTH 32
C_GPIO_WIDTH 8
C_GPIO2_WIDTH 32
C_ALL_INPUTS 0
 
Name Value
C_ALL_INPUTS_2 0
C_INTERRUPT_PRESENT 0
C_DOUT_DEFAULT 0x00000000
C_TRI_DEFAULT 0xFFFFFFFF
C_IS_DUAL 0
C_DOUT_DEFAULT_2 0x00000000
C_TRI_DEFAULT_2 0xFFFFFFFF
C_S_AXI_PROTOCOL AXI4LITE
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


axi_gpio_1   AXI General Purpose IO
General Purpose Input/Output (GPIO) core for the AXI bus.

IP Specs
Core Version Documentation
axi_gpio 1.01.b IP


axi_gpio_1 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 S_AXI_ACLK I 1 processing_system7_0_FCLK_CLK0
1 GPIO_IO_O O 1 axi_gpio_1_GPIO_IO_O
2 GPIO_IO_T O 1 axi_gpio_1_GPIO_IO_T
3 GPIO_IO_I I 1 axi_gpio_1_GPIO_IO_I
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
S_AXI SLAVE AXI axi_interconnect_1 16 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex6
C_INSTANCE axi_gpio_inst
C_BASEADDR 0x412C0000
C_HIGHADDR 0x412CFFFF
C_S_AXI_ADDR_WIDTH 9
C_S_AXI_DATA_WIDTH 32
C_GPIO_WIDTH 8
C_GPIO2_WIDTH 32
C_ALL_INPUTS 0
 
Name Value
C_ALL_INPUTS_2 0
C_INTERRUPT_PRESENT 0
C_DOUT_DEFAULT 0x00000000
C_TRI_DEFAULT 0xFFFFFFFF
C_IS_DUAL 0
C_DOUT_DEFAULT_2 0x00000000
C_TRI_DEFAULT_2 0xFFFFFFFF
C_S_AXI_PROTOCOL AXI4LITE
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


axi_gpio_2   AXI General Purpose IO
General Purpose Input/Output (GPIO) core for the AXI bus.

IP Specs
Core Version Documentation
axi_gpio 1.01.b IP


axi_gpio_2 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 S_AXI_ACLK I 1 processing_system7_0_FCLK_CLK0
1 GPIO_IO_I I 1 axi_gpio_2_GPIO_IO_I
2 GPIO_IO_O O 1 axi_gpio_2_GPIO_IO_O
3 GPIO_IO_T O 1 axi_gpio_2_GPIO_IO_T
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
S_AXI SLAVE AXI axi_interconnect_1 16 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex6
C_INSTANCE axi_gpio_inst
C_BASEADDR 0x41300000
C_HIGHADDR 0x4130FFFF
C_S_AXI_ADDR_WIDTH 9
C_S_AXI_DATA_WIDTH 32
C_GPIO_WIDTH 8
C_GPIO2_WIDTH 32
C_ALL_INPUTS 0
 
Name Value
C_ALL_INPUTS_2 0
C_INTERRUPT_PRESENT 0
C_DOUT_DEFAULT 0x00000000
C_TRI_DEFAULT 0xFFFFFFFF
C_IS_DUAL 0
C_DOUT_DEFAULT_2 0x00000000
C_TRI_DEFAULT_2 0xFFFFFFFF
C_S_AXI_PROTOCOL AXI4LITE
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


axi_gpio_3   AXI General Purpose IO
General Purpose Input/Output (GPIO) core for the AXI bus.

IP Specs
Core Version Documentation
axi_gpio 1.01.b IP


axi_gpio_3 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 S_AXI_ACLK I 1 processing_system7_0_FCLK_CLK0
1 GPIO_IO_I I 1 axi_gpio_3_GPIO_IO_I
2 GPIO_IO_O O 1 axi_gpio_3_GPIO_IO_O
3 GPIO_IO_T O 1 axi_gpio_3_GPIO_IO_T
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
S_AXI SLAVE AXI axi_interconnect_1 16 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex6
C_INSTANCE axi_gpio_inst
C_BASEADDR 0x41340000
C_HIGHADDR 0x4134FFFF
C_S_AXI_ADDR_WIDTH 9
C_S_AXI_DATA_WIDTH 32
C_GPIO_WIDTH 8
C_GPIO2_WIDTH 32
C_ALL_INPUTS 0
 
Name Value
C_ALL_INPUTS_2 0
C_INTERRUPT_PRESENT 0
C_DOUT_DEFAULT 0x00000000
C_TRI_DEFAULT 0xFFFFFFFF
C_IS_DUAL 0
C_DOUT_DEFAULT_2 0x00000000
C_TRI_DEFAULT_2 0xFFFFFFFF
C_S_AXI_PROTOCOL AXI4LITE
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


axi_gpio_led   AXI General Purpose IO
General Purpose Input/Output (GPIO) core for the AXI bus.

IP Specs
Core Version Documentation
axi_gpio 1.01.b IP


axi_gpio_led IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 S_AXI_ACLK I 1 processing_system7_0_FCLK_CLK0
1 GPIO_IO_O O 1 axi_gpio_led_GPIO_IO_O
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
S_AXI SLAVE AXI axi_interconnect_1 16 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex6
C_INSTANCE axi_gpio_inst
C_BASEADDR 0x41240000
C_HIGHADDR 0x4124FFFF
C_S_AXI_ADDR_WIDTH 9
C_S_AXI_DATA_WIDTH 32
C_GPIO_WIDTH 8
C_GPIO2_WIDTH 32
C_ALL_INPUTS 0
 
Name Value
C_ALL_INPUTS_2 0
C_INTERRUPT_PRESENT 0
C_DOUT_DEFAULT 0x00000000
C_TRI_DEFAULT 0xFFFFFFFF
C_IS_DUAL 0
C_DOUT_DEFAULT_2 0x00000000
C_TRI_DEFAULT_2 0xFFFFFFFF
C_S_AXI_PROTOCOL AXI4LITE
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


axi_gpio_oled   AXI General Purpose IO
General Purpose Input/Output (GPIO) core for the AXI bus.

IP Specs
Core Version Documentation
axi_gpio 1.01.b IP


axi_gpio_oled IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 S_AXI_ACLK I 1 processing_system7_0_FCLK_CLK0
1 GPIO_IO_O O 1 axi_gpio_4_GPIO_IO_O
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
S_AXI SLAVE AXI axi_interconnect_2 4 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex6
C_INSTANCE axi_gpio_inst
C_BASEADDR 0x41380000
C_HIGHADDR 0x4138FFFF
C_S_AXI_ADDR_WIDTH 9
C_S_AXI_DATA_WIDTH 32
C_GPIO_WIDTH 8
C_GPIO2_WIDTH 32
C_ALL_INPUTS 0
 
Name Value
C_ALL_INPUTS_2 0
C_INTERRUPT_PRESENT 0
C_DOUT_DEFAULT 0x00000000
C_TRI_DEFAULT 0xFFFFFFFF
C_IS_DUAL 0
C_DOUT_DEFAULT_2 0x00000000
C_TRI_DEFAULT_2 0xFFFFFFFF
C_S_AXI_PROTOCOL AXI4LITE
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


axi_gpio_pmodPortMux   AXI General Purpose IO
General Purpose Input/Output (GPIO) core for the AXI bus.

IP Specs
Core Version Documentation
axi_gpio 1.01.b IP


axi_gpio_pmodPortMux IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 S_AXI_ACLK I 1 processing_system7_0_FCLK_CLK0
1 GPIO_IO_O O 1 axi_gpio_pmodPortMux_GPIO_IO_O
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
S_AXI SLAVE AXI axi_interconnect_1 16 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex6
C_INSTANCE axi_gpio_inst
C_BASEADDR 0x41280000
C_HIGHADDR 0x4128FFFF
C_S_AXI_ADDR_WIDTH 9
C_S_AXI_DATA_WIDTH 32
C_GPIO_WIDTH 8
C_GPIO2_WIDTH 32
C_ALL_INPUTS 0
 
Name Value
C_ALL_INPUTS_2 0
C_INTERRUPT_PRESENT 0
C_DOUT_DEFAULT 0x00000000
C_TRI_DEFAULT 0xFFFFFFFF
C_IS_DUAL 0
C_DOUT_DEFAULT_2 0x00000000
C_TRI_DEFAULT_2 0xFFFFFFFF
C_S_AXI_PROTOCOL AXI4LITE
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


axi_iic_0   AXI IIC Interface
AXI interface to Philips I2C bus v2.1

IP Specs
Core Version Documentation
axi_iic 1.02.a IP


axi_iic_0 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 S_AXI_ACLK I 1 processing_system7_0_FCLK_CLK0
1 Gpo O 1 axi_iic_0_Gpo
2 Sda_I I 1 axi_iic_0_Sda_I
3 Sda_O O 1 axi_iic_0_Sda_O
4 Sda_T O 1 axi_iic_0_Sda_T
5 Scl_I I 1 axi_iic_0_Scl_I
6 Scl_O O 1 axi_iic_0_Scl_O
7 Scl_T O 1 axi_iic_0_Scl_T
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
S_AXI SLAVE AXI axi_interconnect_1 16 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex6
C_INSTANCE axi_iic_inst
C_BASEADDR 0x41600000
C_HIGHADDR 0x4160FFFF
C_S_AXI_ADDR_WIDTH 9
C_S_AXI_DATA_WIDTH 32
C_IIC_FREQ 100000
 
Name Value
C_TEN_BIT_ADR 0
C_GPO_WIDTH 1
C_S_AXI_ACLK_FREQ_HZ 25000000
C_SCL_INERTIAL_DELAY 0
C_SDA_INERTIAL_DELAY 0
C_SDA_LEVEL 1
C_S_AXI_PROTOCOL AXI4LITE
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


axi_iic_1   AXI IIC Interface
AXI interface to Philips I2C bus v2.1

IP Specs
Core Version Documentation
axi_iic 1.02.a IP


axi_iic_1 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 S_AXI_ACLK I 1 processing_system7_0_FCLK_CLK0
1 Sda_I I 1 axi_iic_1_Sda_I
2 Sda_O O 1 axi_iic_1_Sda_O
3 Sda_T O 1 axi_iic_1_Sda_T
4 Scl_I I 1 axi_iic_1_Scl_I
5 Scl_O O 1 axi_iic_1_Scl_O
6 Scl_T O 1 axi_iic_1_Scl_T
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
S_AXI SLAVE AXI axi_interconnect_1 16 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex6
C_INSTANCE axi_iic_inst
C_BASEADDR 0x41640000
C_HIGHADDR 0x4164FFFF
C_S_AXI_ADDR_WIDTH 9
C_S_AXI_DATA_WIDTH 32
C_IIC_FREQ 100000
 
Name Value
C_TEN_BIT_ADR 0
C_GPO_WIDTH 1
C_S_AXI_ACLK_FREQ_HZ 25000000
C_SCL_INERTIAL_DELAY 0
C_SDA_INERTIAL_DELAY 0
C_SDA_LEVEL 1
C_S_AXI_PROTOCOL AXI4LITE
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


axi_iic_2   AXI IIC Interface
AXI interface to Philips I2C bus v2.1

IP Specs
Core Version Documentation
axi_iic 1.02.a IP


axi_iic_2 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 S_AXI_ACLK I 1 processing_system7_0_FCLK_CLK0
1 Sda_I I 1 axi_iic_2_Sda_I
2 Sda_O O 1 axi_iic_2_Sda_O
3 Sda_T O 1 axi_iic_2_Sda_T
4 Scl_I I 1 axi_iic_2_Scl_I
5 Scl_O O 1 axi_iic_2_Scl_O
6 Scl_T O 1 axi_iic_2_Scl_T
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
S_AXI SLAVE AXI axi_interconnect_1 16 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex6
C_INSTANCE axi_iic_inst
C_BASEADDR 0x41680000
C_HIGHADDR 0x4168FFFF
C_S_AXI_ADDR_WIDTH 9
C_S_AXI_DATA_WIDTH 32
C_IIC_FREQ 100000
 
Name Value
C_TEN_BIT_ADR 0
C_GPO_WIDTH 1
C_S_AXI_ACLK_FREQ_HZ 25000000
C_SCL_INERTIAL_DELAY 0
C_SDA_INERTIAL_DELAY 0
C_SDA_LEVEL 1
C_S_AXI_PROTOCOL AXI4LITE
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


axi_iic_3   AXI IIC Interface
AXI interface to Philips I2C bus v2.1

IP Specs
Core Version Documentation
axi_iic 1.02.a IP


axi_iic_3 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 S_AXI_ACLK I 1 processing_system7_0_FCLK_CLK0
1 Sda_I I 1 axi_iic_3_Sda_I
2 Sda_O O 1 axi_iic_3_Sda_O
3 Sda_T O 1 axi_iic_3_Sda_T
4 Scl_I I 1 axi_iic_3_Scl_I
5 Scl_O O 1 axi_iic_3_Scl_O
6 Scl_T O 1 axi_iic_3_Scl_T
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
S_AXI SLAVE AXI axi_interconnect_1 16 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex6
C_INSTANCE axi_iic_inst
C_BASEADDR 0x416C0000
C_HIGHADDR 0x416CFFFF
C_S_AXI_ADDR_WIDTH 9
C_S_AXI_DATA_WIDTH 32
C_IIC_FREQ 100000
 
Name Value
C_TEN_BIT_ADR 0
C_GPO_WIDTH 1
C_S_AXI_ACLK_FREQ_HZ 25000000
C_SCL_INERTIAL_DELAY 0
C_SDA_INERTIAL_DELAY 0
C_SDA_LEVEL 1
C_S_AXI_PROTOCOL AXI4LITE
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


axi_spi_0   AXI SPI Interface
AXI to Motorola Serial Peripheral Interface (SPI) adapter

IP Specs
Core Version Documentation
axi_spi 1.02.a IP


axi_spi_0 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 S_AXI_ACLK I 1 processing_system7_0_FCLK_CLK0
1 SCK_O O 1 axi_spi_0_SCK_O
2 MISO_I I 1 axi_spi_0_MISO_I
3 MOSI_O O 1 axi_spi_0_MOSI_O
4 SS_O O 1 axi_spi_0_SS_O
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
S_AXI SLAVE AXI axi_interconnect_1 16 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex6
C_BASEADDR 0x42000000
C_HIGHADDR 0x4200FFFF
C_S_AXI_ADDR_WIDTH 32
C_S_AXI_DATA_WIDTH 32
C_FIFO_EXIST 1
 
Name Value
C_SCK_RATIO 32
C_NUM_SS_BITS 2
C_NUM_TRANSFER_BITS 8
C_S_AXI_PROTOCOL AXI4LITE
C_INSTANCE axi_spi_inst
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


axi_spi_1   AXI SPI Interface
AXI to Motorola Serial Peripheral Interface (SPI) adapter

IP Specs
Core Version Documentation
axi_spi 1.02.a IP


axi_spi_1 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 S_AXI_ACLK I 1 processing_system7_0_FCLK_CLK0
1 SCK_O O 1 axi_spi_1_SCK_O
2 MISO_I I 1 axi_spi_1_MISO_I
3 MOSI_O O 1 axi_spi_1_MOSI_O
4 SS_O O 1 axi_spi_1_SS_O
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
S_AXI SLAVE AXI axi_interconnect_2 4 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex6
C_BASEADDR 0x42040000
C_HIGHADDR 0x4204FFFF
C_S_AXI_ADDR_WIDTH 32
C_S_AXI_DATA_WIDTH 32
C_FIFO_EXIST 1
 
Name Value
C_SCK_RATIO 32
C_NUM_SS_BITS 1
C_NUM_TRANSFER_BITS 8
C_S_AXI_PROTOCOL AXI4LITE
C_INSTANCE axi_spi_inst
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


axi_spi_2   AXI SPI Interface
AXI to Motorola Serial Peripheral Interface (SPI) adapter

IP Specs
Core Version Documentation
axi_spi 1.02.a IP


axi_spi_2 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 S_AXI_ACLK I 1 processing_system7_0_FCLK_CLK0
1 SCK_O O 1 axi_spi_2_SCK_O
2 MISO_I I 1 axi_spi_2_MISO_I
3 MOSI_O O 1 axi_spi_2_MOSI_O
4 SS_O O 1 axi_spi_2_SS_O
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
S_AXI SLAVE AXI axi_interconnect_2 4 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex6
C_BASEADDR 0x42080000
C_HIGHADDR 0x4208FFFF
C_S_AXI_ADDR_WIDTH 32
C_S_AXI_DATA_WIDTH 32
C_FIFO_EXIST 1
 
Name Value
C_SCK_RATIO 32
C_NUM_SS_BITS 1
C_NUM_TRANSFER_BITS 8
C_S_AXI_PROTOCOL AXI4LITE
C_INSTANCE axi_spi_inst
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


axi_spi_3   AXI SPI Interface
AXI to Motorola Serial Peripheral Interface (SPI) adapter

IP Specs
Core Version Documentation
axi_spi 1.02.a IP


axi_spi_3 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 S_AXI_ACLK I 1 processing_system7_0_FCLK_CLK0
1 SCK_O O 1 axi_spi_3_SCK_O
2 MISO_I I 1 axi_spi_3_MISO_I
3 MOSI_O O 1 axi_spi_3_MOSI_O
4 SS_O O 1 axi_spi_3_SS_O
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
S_AXI SLAVE AXI axi_interconnect_2 4 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex6
C_BASEADDR 0x420C0000
C_HIGHADDR 0x420CFFFF
C_S_AXI_ADDR_WIDTH 32
C_S_AXI_DATA_WIDTH 32
C_FIFO_EXIST 1
 
Name Value
C_SCK_RATIO 32
C_NUM_SS_BITS 1
C_NUM_TRANSFER_BITS 8
C_S_AXI_PROTOCOL AXI4LITE
C_INSTANCE axi_spi_inst
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


axi_uartlite_0   AXI UART (Lite)
Generic UART (Universal Asynchronous Receiver/Transmitter) for AXI.

IP Specs
Core Version Documentation
axi_uartlite 1.02.a IP


axi_uartlite_0 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 S_AXI_ACLK I 1 processing_system7_0_FCLK_CLK0
1 RX I 1 axi_uartlite_0_RX
2 TX O 1 axi_uartlite_0_TX
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
S_AXI SLAVE AXI axi_interconnect_1 16 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex6
C_INSTANCE axi_uartlite_inst
C_S_AXI_ACLK_FREQ_HZ 100000000
C_BASEADDR 0x42C00000
C_HIGHADDR 0x42C0FFFF
C_S_AXI_ADDR_WIDTH 4
 
Name Value
C_S_AXI_DATA_WIDTH 32
C_BAUDRATE 9600
C_DATA_BITS 8
C_USE_PARITY 0
C_ODD_PARITY 0
C_S_AXI_PROTOCOL AXI4LITE
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


axi_uartlite_1   AXI UART (Lite)
Generic UART (Universal Asynchronous Receiver/Transmitter) for AXI.

IP Specs
Core Version Documentation
axi_uartlite 1.02.a IP


axi_uartlite_1 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 S_AXI_ACLK I 1 processing_system7_0_FCLK_CLK0
1 RX I 1 axi_uartlite_1_RX
2 TX O 1 axi_uartlite_1_TX
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
S_AXI SLAVE AXI axi_interconnect_1 16 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex6
C_INSTANCE axi_uartlite_inst
C_S_AXI_ACLK_FREQ_HZ 100000000
C_BASEADDR 0x42C40000
C_HIGHADDR 0x42C4FFFF
C_S_AXI_ADDR_WIDTH 4
 
Name Value
C_S_AXI_DATA_WIDTH 32
C_BAUDRATE 9600
C_DATA_BITS 8
C_USE_PARITY 0
C_ODD_PARITY 0
C_S_AXI_PROTOCOL AXI4LITE
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


axi_uartlite_2   AXI UART (Lite)
Generic UART (Universal Asynchronous Receiver/Transmitter) for AXI.

IP Specs
Core Version Documentation
axi_uartlite 1.02.a IP


axi_uartlite_2 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 S_AXI_ACLK I 1 processing_system7_0_FCLK_CLK0
1 RX I 1 axi_uartlite_2_RX
2 TX O 1 axi_uartlite_2_TX
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
S_AXI SLAVE AXI axi_interconnect_1 16 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex6
C_INSTANCE axi_uartlite_inst
C_S_AXI_ACLK_FREQ_HZ 100000000
C_BASEADDR 0x42C80000
C_HIGHADDR 0x42C8FFFF
C_S_AXI_ADDR_WIDTH 4
 
Name Value
C_S_AXI_DATA_WIDTH 32
C_BAUDRATE 9600
C_DATA_BITS 8
C_USE_PARITY 0
C_ODD_PARITY 0
C_S_AXI_PROTOCOL AXI4LITE
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


axi_uartlite_3   AXI UART (Lite)
Generic UART (Universal Asynchronous Receiver/Transmitter) for AXI.

IP Specs
Core Version Documentation
axi_uartlite 1.02.a IP


axi_uartlite_3 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 S_AXI_ACLK I 1 processing_system7_0_FCLK_CLK0
1 RX I 1 axi_uartlite_3_RX
2 TX O 1 axi_uartlite_3_TX
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
S_AXI SLAVE AXI axi_interconnect_1 16 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex6
C_INSTANCE axi_uartlite_inst
C_S_AXI_ACLK_FREQ_HZ 100000000
C_BASEADDR 0x42CC0000
C_HIGHADDR 0x42CCFFFF
C_S_AXI_ADDR_WIDTH 4
 
Name Value
C_S_AXI_DATA_WIDTH 32
C_BAUDRATE 9600
C_DATA_BITS 8
C_USE_PARITY 0
C_ODD_PARITY 0
C_S_AXI_PROTOCOL AXI4LITE
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.




Timing Information TOP


Post Synthesis Clock Limits
No clocks could be identified in the design. Run platgen to generate synthesis information.