topLevel Project Status (08/27/2013 - 15:39:07)
Project File: top.xise Parser Errors: No Errors
Module Name: top Implementation State: Programming File Generated
Target Device: xc6slx9-2csg324
  • Errors:
No Errors
Product Version:ISE 14.2
  • Warnings:
153 Warnings (31 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
XPS Reports [-]
Report NameGenerated ErrorsWarningsInfos
Platgen Log FileTue Aug 27 15:22:29 20130028 Infos (28 new)
Simgen Log File    
BitInit Log FileTue Aug 27 15:39:05 20130011 Infos (11 new)
System Log File    
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 3,874 11,440 33%  
    Number used as Flip Flops 3,863      
    Number used as Latches 1      
    Number used as Latch-thrus 0      
    Number used as AND/OR logics 10      
Number of Slice LUTs 4,991 5,720 87%  
    Number used as logic 4,526 5,720 79%  
        Number using O6 output only 3,564      
        Number using O5 output only 62      
        Number using O5 and O6 900      
        Number used as ROM 0      
    Number used as Memory 274 1,440 19%  
        Number used as Dual Port RAM 88      
            Number using O6 output only 4      
            Number using O5 output only 0      
            Number using O5 and O6 84      
        Number used as Single Port RAM 0      
        Number used as Shift Register 186      
            Number using O6 output only 43      
            Number using O5 output only 1      
            Number using O5 and O6 142      
    Number used exclusively as route-thrus 191      
        Number with same-slice register load 177      
        Number with same-slice carry load 14      
        Number with other load 0      
Number of occupied Slices 1,429 1,430 99%  
Nummber of MUXCYs used 476 2,860 16%  
Number of LUT Flip Flop pairs used 5,223      
    Number with an unused Flip Flop 1,815 5,223 34%  
    Number with an unused LUT 232 5,223 4%  
    Number of fully used LUT-FF pairs 3,176 5,223 60%  
    Number of unique control sets 336      
    Number of slice register sites lost
        to control set restrictions
1,284 11,440 11%  
Number of bonded IOBs 78 200 39%  
    Number of LOCed IOBs 78 78 100%  
    IOB Flip Flops 6      
Number of RAMB16BWERs 14 32 43%  
Number of RAMB8BWERs 0 64 0%  
Number of BUFIO2/BUFIO2_2CLKs 1 32 3%  
    Number used as BUFIO2s 1      
    Number used as BUFIO2_2CLKs 0      
Number of BUFIO2FB/BUFIO2FB_2CLKs 0 32 0%  
Number of BUFG/BUFGMUXs 2 16 12%  
    Number used as BUFGs 2      
    Number used as BUFGMUX 0      
Number of DCM/DCM_CLKGENs 0 4 0%  
Number of ILOGIC2/ISERDES2s 3 200 1%  
    Number used as ILOGIC2s 3      
    Number used as ISERDES2s 0      
Number of IODELAY2/IODRP2/IODRP2_MCBs 23 200 11%  
    Number used as IODELAY2s 0      
    Number used as IODRP2s 1      
    Number used as IODRP2_MCBs 22      
Number of OLOGIC2/OSERDES2s 46 200 23%  
    Number used as OLOGIC2s 3      
    Number used as OSERDES2s 43      
Number of BSCANs 1 4 25%  
Number of BUFHs 0 128 0%  
Number of BUFPLLs 0 8 0%  
Number of BUFPLL_MCBs 1 4 25%  
Number of DSP48A1s 3 16 18%  
Number of ICAPs 0 1 0%  
Number of MCBs 1 2 50%  
Number of PCILOGICSEs 0 2 0%  
Number of PLL_ADVs 1 2 50%  
Number of PMVs 0 1 0%  
Number of STARTUPs 0 1 0%  
Number of SUSPEND_SYNCs 0 1 0%  
Average Fanout of Non-Clock Nets 3.88      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentTue Aug 27 15:29:22 2013048 Warnings (24 new)1013 Infos (969 new)
Translation ReportCurrentTue Aug 27 15:31:15 2013031 Warnings (7 new)3 Infos (0 new)
Map ReportCurrentTue Aug 27 15:35:30 2013024 Warnings (0 new)10 Infos (1 new)
Place and Route ReportCurrentTue Aug 27 15:37:09 2013026 Warnings (0 new)2 Infos (0 new)
Power Report     
Post-PAR Static Timing ReportCurrentTue Aug 27 15:37:39 201301 Warning (0 new)4 Infos (0 new)
Bitgen ReportCurrentTue Aug 27 15:38:31 2013023 Warnings (0 new)0
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentTue Aug 27 15:38:33 2013
WebTalk Log FileCurrentTue Aug 27 15:38:46 2013

Date Generated: 08/27/2013 - 15:39:08