Overview
Block Diagram
External Ports
Processor
processing_system7_0
Busses
axi_interconnect_1
axi_interconnect_2
Bridge
axi2axi_connector_1
Peripherals
axi_gpio_0
axi_gpio_1
axi_gpio_2
axi_gpio_3
axi_gpio_led
axi_gpio_oled
axi_gpio_pmodPortMux
axi_iic_0
axi_iic_1
axi_iic_2
axi_iic_3
axi_spi_0
axi_spi_1
axi_spi_2
axi_spi_3
axi_uartlite_0
axi_uartlite_1
axi_uartlite_2
axi_uartlite_3
Timing Information