Carmel (MAXREFDES18#) Code Documentation  V01.00
High Accuracy Analog Current/Voltage Output
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platform.c
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1 /*
2  * Copyright (c) 2010-2011 Xilinx, Inc. All rights reserved.
3  *
4  * Xilinx, Inc.
5  * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
6  * COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
7  * ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
8  * STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
9  * IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
10  * FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
11  * XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
12  * THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
13  * ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
14  * FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
15  * AND FITNESS FOR A PARTICULAR PURPOSE.
16  *
17  */
18 
19 #include "xparameters.h"
20 #include "xil_cache.h"
21 
22 #include "platform_config.h"
23 
24 #ifdef STDOUT_IS_PS7_UART
25 #include "xuartps.h"
26 #elif defined(STDOUT_IS_16550)
27 #include "xuartns550_l.h"
28 #endif
29 
30 #define UART_BAUD 9600
31 
32 void
34 {
35 #ifdef __PPC__
36  Xil_ICacheEnableRegion(CACHEABLE_REGION_MASK);
37  Xil_DCacheEnableRegion(CACHEABLE_REGION_MASK);
38 #elif __MICROBLAZE__
39 #ifdef XPAR_MICROBLAZE_USE_ICACHE
40  Xil_ICacheEnable();
41 #endif
42 #ifdef XPAR_MICROBLAZE_USE_DCACHE
43  Xil_DCacheEnable();
44 #endif
45 #endif
46 }
47 
48 void
50 {
51  Xil_DCacheDisable();
52  Xil_ICacheDisable();
53 }
54 
55 void
57 {
58 #ifdef STDOUT_IS_PS7_UART
59  /* Use the PS UART for Zynq devices */
60  XUartPs Uart_Ps_0;
61  XUartPs_Config *Config_0 = XUartPs_LookupConfig(UART_DEVICE_ID);
62  XUartPs_CfgInitialize(&Uart_Ps_0, Config_0, Config_0->BaseAddress);
63  XUartPs_SetBaudRate(&Uart_Ps_0, UART_BAUD);
64 #elif defined(STDOUT_IS_16550)
65  XUartNs550_SetBaud(STDOUT_BASEADDR, XPAR_XUARTNS550_CLOCK_HZ, UART_BAUD);
66  XUartNs550_SetLineControlReg(STDOUT_BASEADDR, XUN_LCR_8_DATA_BITS);
67 #endif
68 }
69 
70 void
72 {
73  enable_caches();
74  init_uart();
75 }
76 
77 void
79 {
81 }