Features and Benefits
- DOCSIS 3.0 performance: 4 QAM carriers
- ACLR over full band (47 MHz to 1 GHz)
- −75 dBc @ fOUT = 200 MHz
- −72 dBc @ fOUT = 800 MHz (noise)
- −67 dBc @ fOUT = 800 MHz (harmonics)
- Unequalized MER = 42 dB
- ACLR over full band (47 MHz to 1 GHz)
- On chip and bypassable
- 4 QAM encoders with SRRC filters, 16× to 512× interpolation, rate converters, and modulators
- Flexible data interface: 4, 8, 16, or 32 bits wide with parity
- Power: 1.6 W (IFS = 20 mA, fDAC = 2.4 GHz, LVDS interface)
- Direct to RF synthesis support with fS mix mode
- Built-in self-test (BIST) support
- Input connectivity check
- Internal random number generator
The AD9789 is a flexible QAM encoder/interpolator/upconverter combined with a high performance, 2400 MSPS, 14-bit RF digital-to-analog converter (DAC). The flexible digital interface can accept up to four channels of complex data. The QAM encoder supports constellation sizes of 16, 32, 64, 128, and 256 with SRRC filter coefficients for all standards.
The on-chip rate converter supports a wide range of baud rates with a fixed DAC clock. The digital upconverter can place the channels from 0 to 0.5 × fDAC. This permits four contiguous channels to be synthesized and placed anywhere from dc to fDAC.
The AD9789 includes a serial peripheral interface (SPI) for device configuration and status register readback. The flexible digital interface can be configured for data bus widths of 4, 8, 16, and 32 bits. It can accept real or complex data.
The AD9789 operates from 1.5 V, 1.8 V, and 3.3 V supplies for a total power consumption of 1.6 W. It is supplied in a 164-ball chip scale package ball grid array for lower thermal impedance and reduced package parasitics. No special power sequencing is required. The clock receiver powers up muted to prevent start-up noise.
- Highly integrated and configurable QAM mappers, interpolators, and upconverters for direct synthesis of one to four DOCSIS- or DVB-C-compatible channels in a block.
- Low noise and intermodulation distortion (IMD) performance enable high quality synthesis of signals up to 1 GHz.
- Flexible data interface supports LVDS for improved SFDR or CMOS input data for less demanding applications.
- Interface is configurable from 4-bit nibbles to 32-bit words and can run at up to 150 MHz CMOS or 150 MHz LVDS double data rate (DDR).
- Manufactured on a CMOS process, the AD9789 uses a proprietary switching technique that enhances dynamic performance.
- Broadband communications systems
- Cellular infrastructure
- Point-to-point wireless
Please contact your local ADI distributor or sales person for samples.
Product Lifecycle Production
At least one model within this product family is in production and available for purchase. The product is appropriate for new designs but newer alternatives may exist.
Evaluation Kits (1)
Software & Systems Requirements
Tools & Simulations
AD9789 Companion Parts
Recommended Clock Source
- For a PLL clock source: ADF4150.
- For a clock source with multiple output VCO frequencies: AD9518-1.
- For a clock and data buffer: ADCLK914.
- For a PLL clock source with integrated VCO: ADF4350.
Recommended Clock Distribution Device
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal.
Sample & Buy
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Pricing displayed is based on 1-piece. The USA list pricing shown is for budgetary use only, shown in United States dollars (FOB USA per unit), and is subject to change. International prices may vary due to local duties, taxes, fees and exchange rates.