Features and Benefits
- JESD204B (Subclass 1) coded serial digital outputs
- 2.0 W total power at 1 GSPS (default settings)
- 1.5 W total power at 500 MSPS (default settings)
- SFDR = 85 dBFS at 340 MHz, 80 dBFS at 985 MHz
- SNR = 65.3 dBFS at 340 MHz (AIN = −1.0 dBFS), 60.5 dBFS at 985 MHz
- ENOB = 10.8 bits at 10 MHz
- DNL = ±0.5 LSB
- INL = ±2.5 LSB
- Noise density = −154 dBFS/Hz at 1 GSPS
- 1.25 V, 2.5 V, and 3.3 V dc supply operation
- No missing codes
- Internal ADC voltage reference
- Flexible input range
- AD9690-1000: 1.46 V p-p to 1.94 V p-p (1.70 V p-p nominal)
- AD9690-500: 1.46 V p-p to 2.06 V p-p (2.06 V p-p nominal)
- Programmable termination impedance
- 400 Ω, 200 Ω, 100 Ω, and 50 Ω differential
- 2 GHz usable analog input full power bandwidth
- Amplitude detect bits for efficient AGC implementation
- 2 integrated wideband digital processors
- 12-bit NCO, up to 4 cascaded half-band filters
- Differential clock input
- Integer clock divide by 1, 2, 4, or 8
- Flexible JESD204B lane configurations
- Small signal dither
The AD9690 is a 14-bit, 1 GSPS/500 MSPS analog-to-digital converter (ADC). The device has an on-chip buffer and sample-and-hold circuit designed for low power, small size, and ease of use. This device is designed for sampling wide bandwidth analog signals of up to 2 GHz. The AD9690 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.
The ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. The ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations.
The analog input and clock signals are differential inputs. The ADC data output is internally connected to two digital down-converters (DDCs). Each DDC consists of four cascaded signal processing stages: a 12-bit frequency translator (NCO), and four half-band decimation filters.
In addition to the DDC blocks, the AD9690 has several functions that simplify the automatic gain control (AGC) function in the communications receiver.
The programmable threshold detector allows monitoring of the incoming signal power using the fast detect output bits of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input.
Users can configure the Subclass 1 JESD204B-based high speed serialized output in a variety of one-, two-, or four-lane con-figurations, depending on the DDC configuration and the acceptable lane rate of the receiving logic device. Multiple device synchronization is supported through the SYSREF± and SYNCINB± input pins.
The AD9690 has flexible power-down options that allow significant power savings when desired. All of these features can be programmed using a 1.8 V to 3.3 V capable 3-wire SPI.p>
The AD9690 is available in a Pb-free, 64-lead LFCSP and is specified over the −40°C to +85°C industrial temperature range. This product may be protected by one or more U.S. or international patents.
- Wide full power bandwidth supports IF sampling of signals up to 2 GHz.
- Buffered inputs with programmable input termination eases filter design and implementation.
- Two integrated wideband decimation filters and numerically controlled oscillator (NCO) blocks supporting multiband receivers.
- Flexible serial port interface (SPI) controls various product features and functions to meet specific system requirements.
- Programmable fast overrange detection.
- 9 mm × 9 mm 64-lead LFCSP.
- Multiband, multimode digital receivers 3G/4G, TD-SCDMA, W-CDMA, GSM, LTE
- General-purpose software radios
- Ultrawideband satellite receivers
- Signals intelligence (SIGINT)
- DOCSIS 3.0 CMTS upstream receive paths
- HFC digital reverse path receivers
Product Lifecycle Recommended for New Designs
This product has been released to the market. The data sheet contains all final specifications and operating conditions. For new designs, ADI recommends utilization of these products.
Evaluation Kits (1)
The AD9680-1000EBZ/AD9234-1000EBZ/AD9690-1000EBZ is an evaluation board for the AD9680-1000 14-Bit, 1000MSPS JESD204B, Dual Analog-to-Digital Converter/ AD9234-1000 14-BIT, 1000 MSPS JESD204B, Dual Analog to Digital Converter/ AD9690-1000 14-Bit, 500 MSPS, 1 GSPS JESD204B, Analog-to-Digital Converter. This reference design provides all of the support circuitry required to operate the ADC in its various modes and configurations. It is designed to interface directly with the ADS7-V2EBZ data capture card, allowing users to download captured data for analysis. The Visual Analog software package, which is used to interface with the device's hardware, allows users to download captured data for analysis with a user-friendly graphical interface. The SPI Controller software package is also compatible with this hardware, and allows the user to access the SPI programmable features of the AD9680/AD9234/AD9690. The user guide wiki provides documentation and instructions to configure the device for performance evaluation in the lab.
The AD9680/AD9234/AD9690 data sheet provides additional information related to device configuration and performance, and should be consulted when using the evaluation board. All documents and Visual Analog and SPI Controller are available at the High Speed ADC Evaluation Boards page. For additional information or questions, please email email@example.com
- Analog signal source and antialiasing filter
- Sample Clock Source
- REFCLOCK source for FPGA receiver
- PC running Windows 7, XP or Vista
- USB 2.0 port recommended (USB 1.1 compatible)
- AD9680-1000EBZ Evaluation Board
- ADS7-V2EBZ FPGA Based Data Capture Kit
Tools & Simulations
This command line executable tool generates a Verilog module which implements the JESD204 receive transport layer. The user specifies in a configuration file one or more modes to be supported by the transport layer module. These modes are defined as a set of JESD204 parameter values: L, M, F, S, N', and CF. The transport layer converts JESD204 lane data output from a JESD204 link layer IP to a data bus with a fixed width, containing interleaved virtual converter samples. Both JESD204B and JESD204C link layers are supported.
The JESD204x Frame Mapping Table Generator tool consists of two Windows executables that will allow the user to input any valid combination of JESD204x parameters (L, M, F, S, NP) in order to output a .csv file that illustrates the frame mapping of the JESD204x mode in table format. There is an executable that allows the user to input a single JESD204x mode and another, that allows the user to input the parameters for multiple JESD204x modes in a specified .csv format in order to output a .csv file that illustrates the frame mapping of each of the JESD204x modes that were input into separate tables.
FPGA Interoperability Reports (2)
Technical Articles (1)
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal.
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Pricing displayed is based on 1-piece. The USA list pricing shown is for budgetary use only, shown in United States dollars (FOB USA per unit), and is subject to change. International prices may vary due to local duties, taxes, fees and exchange rates.