Features and Benefits
- 1.8 V analog supply operation
- 1.8 V CMOS or 1.8 V LVDS output
- SNR = 61.7 dBFS at 70 MHz
- SFDR = 85 dBc at 70 MHz
- Low power: 95 mW/channel at 125 MSPS
- Differential analog input with 650 MHz bandwidth
- IF sampling frequencies to 200 MHz
- On-chip voltage reference and sample-and-hold circuit
- 2 Vp-p differential analog input
- DNL = ±0.13 LSB
- See data sheet for additional features
The AD9608 is a monolithic, dual-channel, 1.8 V supply, 10-bit, 105 MSPS/125 MSPS analog-to-digital converter (ADC) that features a high performance sample-and-hold circuit and an on-chip voltage reference.
The product uses multistage differential pipeline architecture with output error correction logic to provide 10-bit accuracy at 125 MSPS data rates and to guarantee no missing codes over the full operating temperature range.
The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI).
A differential clock input controls all internal conversion cycles. An optional duty cycle stabilizer (DCS) compensates for wide variations in the clock duty cycle while maintaining excellent overall ADC performance.
The digital output data is presented in offset binary, Gray code, or twos complement format. A data output clock (DCO) is provided for each ADC channel to ensure proper latch timing with receiving logic. Logic levels of 1.8 V CMOS and 1.8 V LVDS are supported. Output data can also be multiplexed onto a single output bus.
The AD9608 is available in a 64-lead RoHS-compliant LFCSP and is specified over the industrial temperature range (−40°C to +85°C).
- Operates from a single 1.8 V analog power supply and features a separate digital output driver supply to accommodate 1.8 V CMOS or 1.8 V LVDS logic families.
- The patented sample-and-hold circuit maintains excellent performance for input frequencies up to 200 MHz and is designed for low cost, low power, and ease of use.
- Includes a standard serial port interface that supports various product features and functions, such as data output format-ting, internal clock divider, power-down, DCO/data timing, and offset adjustments.
- Packaged in a 64-lead, RoHS-compliant LFCSP that is pin compatible with the AD9650, AD9269 and AD9268 16-bit ADC’s, the AD9258 and AD9648 14-bit ADC, the AD9628 and AD9231 12-bit ADC’s, and the AD9204 10-bit ADC’s, enabling a simple migration path between 10-bit and 16-bit converters sampling from 20 MSPS to 125 MSPS.
- Diversity radio systems
- I/Q demodulation systems
- Broadband data applications
- Battery-powered instruments
- Hand held scope meters
- Portable medical imaging
Product Lifecycle Recommended for New Designs
This product has been released to the market. The data sheet contains all final specifications and operating conditions. For new designs, ADI recommends utilization of these products.
Evaluation Kits (2)
The AD9608-125EBZ is an evaluation board for the AD9608, dual 10-bit ADC. This reference design provides all of the support circuitry to operate devices in their various modes and configurations, It is designed to interface directly with the HSC-ADC-EVALCZ data capture card, allowing users to download captured data for analysis. The Visual Analog software package, which is used to interface with the device’s hardware, allows users to download captured data for analysis with a user-friendly graphical interface. The SPI controller software package is also compatible with this hardware and allows the user to access the SPI programmable features of the AD9608.
The AD9608 data sheet provides additional information related to device configuration and performance and should be consulted when using these tools. All documents and Visual Analog and SPI Controller are available at the High Speed ADC Evaluation Boards page. For additional information or questions, please email firstname.lastname@example.org.
Features & Benefits
- Full featured evaluation board for the AD9608
- SPI interface for setup and control
- External, on-board oscillator, or AD9517 clocking option
- Balun/transformer or amplifier input drive option
- LDO regulator or switching power supply options
- VisualAnalog® and SPI controller software interfaces
The HSC-ADC-EVALCZ high speed converter evaluation platform uses an FPGA based buffer memory board to capture blocks of digital data from the Analog Devices high speed analog-to-digital converter (ADC) evaluation boards. The board is connected to the PC through a USB port and is used with VisualAnalog® to quickly evaluate the performance of high speed ADCs. The evaluation kit is easy to set up. Additional equipment needed includes an Analog Devices high speed ADC evaluation board, a signal source, and a clock source. Once the kit is connected and powered, the evaluation is enabled instantly on the PC.
Features & Benefits
- 64kB FIFO Depth
- Works with single and multi-channel ADCs
- Use with VisualAnalog® software
- Based on Virtex-4 FPGA
- May require adaptor to interface with some ADC eval boards
- Allows programming of SPI control Up to 644 MSPS SDR / 800MSPS DDR Encode Rates on each channel
- DDR Encode Rates on each channel
Documentation & Resources
AN-905: VisualAnalog™ Converter Evaluation Tool Version 1.0 User Manual8/18/2020
AN-878: High Speed ADC SPI Control Software (Rev. A)3/20/2018
AN-835: Understanding High Speed ADC Testing and Evaluation (Rev. B)5/12/2015
AN-282: Fundamentals of Sampled Data Systems2/14/2015
AN-756: Sampled Systems and the Effects of Clock Phase Noise and Jitter (Rev. 0)2/14/2015
AN-827: A Resonant Approach to Interfacing Amplifiers to Switched-Capacitor ADCs (Rev. 0)2/14/2015
AN-935: Designing an ADC Transformer-Coupled Front End (Rev. 0)2/14/2015
AN-742: Frequency Domain Response of Switched-Capacitor ADCs (Rev. C)2/14/2015
AN-1142: Techniques for High Speed ADC PCB Layout (Rev. 0)2/2/2012
AN-737: How ADIsimADC Models an ADC (Rev. B)11/9/2007
AN-807: Multicarrier WCDMA Feasibility (Rev. 0)11/9/2007
AN-808: Multicarrier CDMA2000 Feasibility (Rev. 0)11/9/2007
AN-803: Pin Compatible High Speed ADCs Simplify Design Tasks (Rev. 0)11/29/2006
Tools & Simulations
AD9608 IBIS Model
For designers who are selecting or evaluating high speed ADCs, VisualAnalog™ is a software package that combines a powerful set of simulation and data analysis tools with a user-friendly graphical interface.
AD9608 Companion Parts
Recommended Clock Drivers
- For low jitter performance along with on chip PLL and VCO: AD9523, AD9523-1, AD9524.
- For low jitter performance: AD9510, AD9511, AD9512, AD9513, AD9514, AD9515.
Recommended Driver Amplifiers
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal.
Sample & Buy
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Pricing displayed is based on 1-piece. The USA list pricing shown is for budgetary use only, shown in United States dollars (FOB USA per unit), and is subject to change. International prices may vary due to local duties, taxes, fees and exchange rates.