AD9265
PRODUCTION16-Bit, 125 MSPS/105 MSPS/80 MSPS, 1.8 V Analog-to-Digital Converter
- Part Models
- 6
- 1ku List Price
- Starting From $63.92
Part Details
- SNR = 79.0 dBFS @ 70 MHz and 125 MSPS
- SFDR = 93 dBc @ 70 MHz and 125 MSPS
- Low power: 373 mW @ 125 MSPS
- 1.8 V analog supply operation
- 1.8 V CMOS or LVDS output supply
- Integer 1-to-8 input clock divider
- IF sampling frequencies to 300 MHz
- −154.3 dBm/Hz small signal input noise with 200 Ω input impedance @ 70 MHz and 125 MSPS
- Optional on-chip dither
- Programmable internal ADC voltage reference
- Integrated ADC sample-and-hold inputs
- Flexible analog input range: 1 V p-p to 2 V p-p
- Differential analog inputs with 650 MHz bandwidth ADC clock duty cycle stabilizer
- Serial port control
- User-configurable, built-in self-test (BIST) capability Energy-saving power-down modes
The AD9265 is a 16-bit, 125 MSPS analog-to-digital converter (ADC). The AD9265 is designed to support communications applications where high performance combined with low cost, small size, and versatility is desired.
The ADC core features a multistage, differential pipelined architecture with integrated output error correction logic to provide 16-bit accuracy at 125 MSPS data rates and guarantees no missing codes over the full operating temperature range.
The ADC features a wide bandwidth differential sample-and-hold analog input amplifier supporting a variety of user-selectable input ranges. It is suitable for multiplexed systems that switch full-scale voltage levels in successive channels and for sampling single-channel inputs at frequencies well beyond the Nyquist rate. Combined with power and cost savings over previously available ADCs, the AD9265 is suitable for applications in communications, instrumentation and medical imaging.
A differential clock input controls all internal conversion cycles. A duty cycle stabilizer provides the means to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance over a wide range of input clock duty cycles. An integrated voltage reference eases design considerations.
The ADC output data format is either parallel 1.8 V CMOS or LVDS (DDR). A data output clock is provided to ensure proper latch timing with receiving logic.
Programming for setup and control is accomplished using a 3-wire SPI-compatible serial interface. Flexible power-down options allow significant power savings, when desired. An optional on-chip dither function is available to improve SFDR performance with low power analog input signals.
The AD9265 is available in a Pb-free, 48-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C.
APPLICATIONS
- Communications
- Multimode digital receivers (3G)
- GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, and TD-SCDMA
- Smart antenna systems
- General-purpose software radios
- Broadband data applications
- Ultrasound equipment
PRODUCT HIGHLIGHTS
- On-chip dither option for improved SFDR performance with low power analog input.
- Proprietary differential input that maintains excellent SNR performance for input frequencies up to 300 MHz.
- Operation from a single 1.8 V supply and a separate digital output driver supply accommodating 1.8 V CMOS or LVDS outputs.
- Standard serial port interface (SPI) that supports various product features and functions, such as data formatting (offset binary, twos complement, or gray coding), enabling the clock duty cycle stabilizer, DCS, power-down, test modes, and voltage reference mode.
- Pin compatibility with the AD9255, allowing a simple migration from 16 bits down to 14 bits.
Documentation
Data Sheet 1
User Guide 1
Application Note 1
Technical Articles 4
Evaluation Design File 3
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal. View our quality and reliability program and certifications for more information.
| Part Model | Pin/Package Drawing | Documentation | CAD Symbols, Footprints, and 3D Models |
|---|---|---|---|
| AD9265BCPZ-105 | 48-Lead LFCSP (7mm x 7mm x 0.85mm w/ EP) | ||
| AD9265BCPZ-125 | 48-Lead LFCSP (7mm x 7mm x 0.85mm w/ EP) | ||
| AD9265BCPZ-80 | 48-Lead LFCSP (7mm x 7mm x 0.85mm w/ EP) | ||
| AD9265BCPZRL7-105 | 48-Lead LFCSP (7mm x 7mm x 0.85mm w/ EP) | ||
| AD9265BCPZRL7-125 | 48-Lead LFCSP (7mm x 7mm x 0.85mm w/ EP) | ||
| AD9265BCPZRL7-80 | 48-Lead LFCSP (7mm x 7mm x 0.85mm w/ EP) |
| Part Models | Product Lifecycle | PCN |
|---|---|---|
|
Feb 1, 2024 - 24_0009 Qualification of alternative Wafer Fab for TSMC 0.18um Mixed Signal CMOS Process |
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| AD9265BCPZ-105 | PRODUCTION | |
| AD9265BCPZ-125 | PRODUCTION | |
| AD9265BCPZ-80 | PRODUCTION | |
| AD9265BCPZRL7-105 | PRODUCTION | |
| AD9265BCPZRL7-125 | PRODUCTION | |
| AD9265BCPZRL7-80 | PRODUCTION | |
|
Jun 9, 2021 - 20_0126 Conversion of Select Sizes LFCSP Products from Punched to Sawn and Transfer of Assembly Site to ASE Korea |
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| AD9265BCPZ-105 | PRODUCTION | |
| AD9265BCPZ-125 | PRODUCTION | |
| AD9265BCPZ-80 | PRODUCTION | |
| AD9265BCPZRL7-105 | PRODUCTION | |
| AD9265BCPZRL7-125 | PRODUCTION | |
| AD9265BCPZRL7-80 | PRODUCTION | |
|
Sep 13, 2017 - 16_0077 CANCELLED: Conversion of Select 4x4, 5x5, 6x6 and 7x7mm LFCSP Package Outlines from Punch to Sawn and Transfer of Assembly Site to ASE Korea. |
||
| AD9265BCPZ-105 | PRODUCTION | |
| AD9265BCPZ-125 | PRODUCTION | |
| AD9265BCPZ-80 | PRODUCTION | |
| AD9265BCPZRL7-105 | PRODUCTION | |
| AD9265BCPZRL7-125 | PRODUCTION | |
| AD9265BCPZRL7-80 | PRODUCTION | |
|
Feb 25, 2025 - 25_0055 Gold Wire to Copper Wire Conversion(PCA) |
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| AD9265BCPZ-125 | PRODUCTION | |
| AD9265BCPZ-80 | PRODUCTION | |
| AD9265BCPZRL7-125 | PRODUCTION | |
| AD9265BCPZRL7-80 | PRODUCTION | |
This is the most up-to-date revision of the Data Sheet.
Software Resources
Evaluation Software 0
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Hardware Ecosystem
| Parts | Product Life Cycle | Description |
|---|---|---|
| Clock Distribution Devices 3 | ||
| AD9513 | RECOMMENDED FOR NEW DESIGNS | 800 MHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs |
| AD9514 | RECOMMENDED FOR NEW DESIGNS | 1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs |
| AD9515 | RECOMMENDED FOR NEW DESIGNS | 1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Two Outputs |
| Clock Generation Devices 3 | ||
| AD9510 | RECOMMENDED FOR NEW DESIGNS | 1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs |
| AD9511 | RECOMMENDED FOR NEW DESIGNS | 1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Five Outputs |
| AD9512 | RECOMMENDED FOR NEW DESIGNS | 1.2 GHz Clock Distribution IC, Two 1.6 GHz Inputs, Dividers, Delay Adjust, Five Outputs |
| Digital Control VGAs 2 | ||
| AD8376 | RECOMMENDED FOR NEW DESIGNS | Ultralow Distortion IF Dual VGA |
| AD8372 | RECOMMENDED FOR NEW DESIGNS | 41 dB Range, 1 dB Step Size, Programmable Dual VGA |
| Fully Differential Amplifiers 2 | ||
| ADL5561 | RECOMMENDED FOR NEW DESIGNS |
2.9 GHz Ultralow Distortion RF/IF Differential Amplifier |
| ADL5562 | RECOMMENDED FOR NEW DESIGNS | 3.3 GHz Ultralow Distortion RF/IF Differential Amplifier |
| Single-Ended to Differential Amplifiers 2 | ||
| ADA4937-2 | RECOMMENDED FOR NEW DESIGNS | Ultralow Distortion Differential ADC Driver (Dual) |
| ADA4938-2 | RECOMMENDED FOR NEW DESIGNS | Ultralow Distortion Differential ADC Driver (Dual) |
Tools & Simulations
Virtual Eval - BETA
Virtual Eval is a web application to assist designers in product evaluation of ADCs, DACs, and other ADI products. Using detailed models on Analog’s servers, Virtual Eval simulates crucial part performance characteristics within seconds. Configure operating conditions such as input tones and external jitter, as well as device features like gain or digital down-conversion. Performance characteristics include noise, distortion, and resolution, FFTs, timing diagrams, response plots, and more.
Open ToolVisual Analog
For designers who are selecting or evaluating high speed ADCs, VisualAnalog™ is a software package that combines a powerful set of simulation and data analysis tools with a user-friendly graphical interface.
Open ToolADIsimRF
ADIsimRF is an easy-to-use RF signal chain calculator. Cascaded gain, noise, distortion and power consumption can be calculated, plotted and exported for signal chains with up to 50 stages. ADIsimRF also includes an extensive data base of device models for ADI’s RF and mixed signal components.
Open ToolS-Parameter 1
AD9265 Simulink ADIsimADC Model
Open ToolAD9265 IBIS Models 1
Evaluation Kits
AD9265 Evaluation Board
Resources
High Speed Controller Board