AD9234
RECOMMENDED FOR NEW DESIGNS
- Part Models
- 4
- 1ku List Price
- Starting From $305.59
Overview
- JESD204B (Subclass 1) coded serial digital outputs
- 1.5 W total power per channel at 1 GSPS (default settings)
- SFDR
- 79 dBFS at 340 MHz (1 GSPS)
- 85 dBFS at 340 MHz (500 MSPS)
- SNR
- 63.4 dBFS at 340 MHz (AIN = −1.0 dBFS, 1 GSPS)
- 65.6 dBFS at 340 MHz (AIN = −1.0 dBFS, 500 MSPS)
- ENOB = 10.4 bits at 10 MHz (1 GSPS)
- DNL = ±0.16 LSB; INL = ±0.35 LSB (1 GSPS)
- Noise density
- −151 dBFS/Hz (1 GSPS)
- −150 dBFS/Hz (500 MSPS)
- 1.25 V, 2.5 V, and 3.3 V dc supply operation
- Low swing full-scale input
- 1.34 V p-p typical (1 GSPS)
- 1.63 V p-p typical (500 MSPS)
- No missing codes
- Internal ADC voltage reference
- Flexible termination impedance
- 400 Ω, 200 Ω, 100 Ω, and 50 Ω differential
- 2 GHz usable analog input full power bandwidth
- 95 dB channel isolation/crosstalk
- Amplitude detect bits for efficient AGC implementation
- Differential clock input
- Optional decimate by 2 DDC per channel
- Differential clock input
- Integer clock divide by 1, 2, 4, or 8
- Flexible JESD204B lane configurations
- Small signal dither
The AD9234 is a dual, 12-bit, 1 GSPS/500 MSPS ADC. The device has an on-chip buffer and sample-and-hold circuit designed for low power, small size, and ease of use. This product is designed for sampling wide bandwidth analog signals. The AD9234 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.
The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth buffered inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. Each ADC data output is internally connected to an optional decimate-by-2 block. The AD9234 has several functions that simplify the automatic gain control (AGC) function in a communications receiver.
The programmable threshold detector allows monitoring of the incoming signal power using the fast detect output bits of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input. In addition to the fast detect outputs, the AD9234 also offers signal monitoring capability. The signal monitoring block provides additional information about the signal being digitized by the ADC.
Users can configure the Subclass 1 JESD204B-based high speed serialized output in a variety of one-, two-, or four-lane configurations, depending on the acceptable lane rate of the receiving logic device and the sampling rate of the ADC. Multiple device synchronization is supported through the SYSREF± and SYNCINB± input pins.
The AD9234 has flexible power-down options that allow significant power savings when desired. All of these features can be programmed using a 1.8 V to 3.3 V capable 3-wire SPI.
The AD9234 is available in a Pb-free, 64-lead LFCSP and is specified over the −40°C to +85°C industrial temperature range. This product is protected by a U.S. patent.
PRODUCT HIGHLIGHTS
- Low power consumption analog core, 12-bit, 1.0 GSPS dual analog-to-digital converter (ADC) with 1.5 W per channel.
- Wide full power bandwidth supports IF sampling of signals up to 2 GHz.
- Buffered inputs with programmable input termination eases filter design and implementation.
- Flexible serial port interface (SPI) controls various product features and functions to meet specific system requirements.
- Programmable fast overrange detection.
- 9 mm × 9 mm 64-lead LFCSP.
- Pin compatible with the AD9680 14-bit, 1 GSPS dual ADC.
APPLICATIONS
- Communications
- Diversity multiband, multimode digital receivers
- 3G/4G, TD-SCDMA, W-CDMA, GSM, LTE
- Point-to-point radio systems
- Digital predistortion observation path
- General-purpose software radios
- Ultrawideband satellite receiver
- Instrumentation (spectrum analyzers, network analyzers, integrated RF test solutions)
- Digital oscilloscopes
- High speed data acquisition systems
- DOCSIS 3.0 CMTS upstream receive paths
- HFC digital reverse path receivers
Documentation
Data Sheet 1
User Guide 1
Technical Articles 2
Device Drivers 1
FPGA Interoperability Reports 2
Webcast 2
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal. View our quality and reliability program and certifications for more information.
| Part Model | Pin/Package Drawing | Documentation | CAD Symbols, Footprints, and 3D Models |
|---|---|---|---|
| AD9234BCPZ-1000 | 64-Lead LFCSP (9mm x 9mm w/ EP) | ||
| AD9234BCPZ-500 | 64-Lead LFCSP (9mm x 9mm w/ EP) | ||
| AD9234BCPZRL7-1000 | 64-Lead LFCSP (9mm x 9mm w/ EP) | ||
| AD9234BCPZRL7-500 | 64-Lead LFCSP (9mm x 9mm w/ EP) |
| Part Models | Product Lifecycle | PCN |
|---|---|---|
|
Feb 1, 2017 - 16_0273 AD9234-500/1000 Die Revision and Data Sheet Change |
||
| AD9234BCPZ-1000 | PRODUCTION | |
| AD9234BCPZ-500 | PRODUCTION | |
| AD9234BCPZRL7-1000 | PRODUCTION | |
| AD9234BCPZRL7-500 | PRODUCTION | |
This is the most up-to-date revision of the Data Sheet.
Software Resources
Device Drivers 1
Evaluation Software 2
JESD204x Frame Mapping Table Generator
The JESD204x Frame Mapping Table Generator tool consists of two Windows executables that will allow the user to input any valid combination of JESD204x parameters (L, M, F, S, NP) in order to output a .csv file that illustrates the frame mapping of the JESD204x mode in table format. There is an executable that allows the user to input a single JESD204x mode and another, that allows the user to input the parameters for multiple JESD204x modes in a specified .csv format in order to output a .csv file that illustrates the frame mapping of each of the JESD204x modes that were input into separate tables.
JESD204 Interface Framework
Integrated JESD204 software framework for rapid system-level development and optimization
Can't find the software or driver you need?
Hardware Ecosystem
| Parts | Product Life Cycle | Description |
|---|---|---|
| Clock ICs 5 | ||
| LTC6951 | LAST TIME BUY | Ultralow Jitter Multi-Output Clock Synthesizer with Integrated VCO |
| LTC6952 | LAST TIME BUY | Ultralow Jitter, 4.5GHz PLL with 11 Outputs and JESD204B / JESD204C Support |
| HMC7044 | RECOMMENDED FOR NEW DESIGNS | High Performance, 3.2 GHz, 14-Output Jitter Attenuator with JESD204B and JESD204C Support |
| AD9528 | RECOMMENDED FOR NEW DESIGNS | JESD204B/JESD204C Clock Generator with 14 LVDS/HSTL Outputs |
| LTC6953 | LAST TIME BUY | Ultralow Jitter, 4.5GHz Clock Distributor with 11 Outputs and JESD204B/JESD204C Support |
| Differential Amplifiers 1 | ||
| ADL5565 | RECOMMENDED FOR NEW DESIGNS |
6 GHz Ultrahigh Dynamic Range Differential Amplifier |
| Fanout Buffers & Splitters 2 | ||
| LTC6955 | LAST TIME BUY | Ultralow Jitter, 7.5GHz, 11 Output Fanout Buffer Family |
| HMC7043 | RECOMMENDED FOR NEW DESIGNS |
High Performance, 3.2 GHz, 14-Output Fanout Buffer with JESD204B/JESD204C |
| LDO Linear Regulators 1 | ||
| ADP1741 | PRODUCTION | 2 A, Low VIN, Dropout, CMOS Linear Regulator |
| Switching Regulators & Controllers 2 | ||
| ADP2164 | PRODUCTION | 6.5V, 4 A, High Efficiency, Step-Down DC-to-DC Regulator |
| ADP2384 | PRODUCTION | 20 V, 4 A, Synchronous Step-Down DC-to-DC Regulator |
| Variable Gain Amplifiers (VGA) 1 | ||
| ADA4961 | RECOMMENDED FOR NEW DESIGNS | Low Distortion, 3.2 GHz, RF DGA |
Tools & Simulations
Virtual Eval - BETA
Virtual Eval is a web application to assist designers in product evaluation of ADCs, DACs, and other ADI products. Using detailed models on Analog’s servers, Virtual Eval simulates crucial part performance characteristics within seconds. Configure operating conditions such as input tones and external jitter, as well as device features like gain or digital down-conversion. Performance characteristics include noise, distortion, and resolution, FFTs, timing diagrams, response plots, and more.
Open ToolADC Companion Transport Layer RTL Code Generator Tool
This command line executable tool generates a Verilog module which implements the JESD204 receive transport layer. The user specifies in a configuration file one or more modes to be supported by the transport layer module. These modes are defined as a set of JESD204 parameter values: L, M, F, S, N', and CF. The transport layer converts JESD204 lane data output from a JESD204 link layer IP to a data bus with a fixed width, containing interleaved virtual converter samples. Both JESD204B and JESD204C link layers are supported.
Open ToolIBIS Model 1
Evaluation Kits
AD9680/AD9234/AD9690 Evaluation Board
Resources
FPGA Based Data Capture Kit