Redundant 2-Wire Bus for High Reliability Systems

Introduction

The effort to achieve high reliability in data processing, data storage and communication systems has necessitated the use of circuitry to monitor parameters such as temperature, fan speed, and system voltages. These circuits often communicate through 2-wire serial buses, such as SMBus or I2C. Redundant subsystems are important in high reliability systems, and the 2-wire bus subsystem is no exception. High reliability 2-wire bus systems incorporate two master controllers in a redundant configuration, to maintain system operation if one master fails or is removed. In a redundant configuration, each master is connected to its own 2-wire bus, while all of the slaves are connected to a single downstream redundant bus. Either master can take control of the redundant bus at any time.

Figure 1 shows a circuit using two LTC4302’s, each dedicated to a master, to allow either master to take control of a redundant 2-wire bus. The LTC4302’s GPIO pins default to a high impedance state at power-up, so that 10K pull-up resistors R5, R6 and R13 set each GPIO voltage high. With each LTC4302’s GPIO1 pin connected to the CONN pin of the other, both LTC4302’s are active at power-up and can be accessed via their SDAIN and SCLIN pins.

Figure 1. Two LTC4302s in a redundant bus application, with a hardware reset on the CONN pins.

In this configuration, each master can take control of the downstream redundant bus with two Write Byte operations to its dedicated LTC4302. In the first operation, the master activates the connection to the downstream redundant bus, and writes both of its GPIO pins low. With the GPIO1 pin low, the other master is disconnected from the redundant bus and is also prevented from communicating with its LTC4302. In the second operation, the master writes a logic high to its GPIO1 pin, so that the other master is again free to communicate with its LTC4302. Using this technique, the common GPIO2 pin is low whenever one of the masters is connected to the redundant bus, so that each master can read its LTC4302 to determine whether the other master has control of the redundant bus.

Either master can take control of the redundant bus at any time except under two conditions. First, if a master tries to access its LTC4302 and receives no Acknowledge signal, it knows that the other master has completed the first Write Byte operation, but has not yet re-written its GPIO1 pin back high. Second, if both masters try to connect to the redundant bus within 100ns of each other, both are connected to the bus temporarily, and are then disconnected.

A disadvantage of this scheme is that two separate write operations are required for a master to take control of the downstream bus properly. After the first operation, the new master has control of the redundant bus, and the other master cannot access its own LTC4302 because its CONN pin is low. If the new master is removed from the system, or if its 2-wire bus locks up before it can complete the second write operation to write a logic high to its GPIO1 pin, then the other master is permanently prevented from taking control of the redundant bus through the 2-wire interface. An externally controlled pull-down device would have to be used to pull the CONN pin of the new master low, as shown by N-Channel MOSFET transistors N1 and N2 in Figure 1.

Figure 2 shows an alternative approach to solve this problem. Each master can take control of the redundant bus using a single Write Byte operation. For example, Master 0 commands its LTC4302 to connect to the redundant bus and also to force logic lows on both of its GPIO pins. When its GPIO1 pin transitions high-to-low, the circuit formed by R9, C2 and the two two-input NAND gates generates a negative pulse on the other LTC4302’s CONN pin. The duration of the pulse is set by the R9 • C2 time constant and is roughly 3.3μs. Pulsing CONN low resets the registers of the LTC4302 to their default states, thereby disconnecting Master 1 from the redundant bus. After 1μs, Master 1’s CONN pin returns high, and Master 1 is again free to take control of the redundant bus.

Figure 2. Alternate implementation of two LTC4302s in a redundant bus application, with lock-up prevention circuitry.

The LTC4302 also provides bidirectional buffering, keeping the capacitances of the master buses and the redundant bus isolated from each other. Rise time accelerator circuitry further eases the burden of heavy capacitive loads by providing strong pull-up currents during rising edges to reduce the rise time. Thanks to these two features, the LTC4302 enables the implementation of much larger 2-wire bus systems than are possible with a simple unbuffered multiplexer.

Об авторах

Generic_Author_image

John Ziegler