Maximum SNR vs Clock Jitter

When designing the clock network for a high speed ADC one of the most critical parameters is jitter. The amount of clock jitter will set the maximum SNR that you can achieve for a given input frequency. Most modern high speed ADCs have about 80fs of jitter, and the encode clock of the ADC should be in that ball park.It certainly should be less that 1ps for maximum performance of the ADC.

The relationship between SNR and jitter is given by this equation:

Maximum SNR vs Clock Jitter

Where fin is the frequency of the input signal, and tj is the jitter of the clock. The equation shows that for a high frequency input signal and a fixed amount of jitter the maximum SNR will decrease. This is because a faster slewing signal will have more of a voltage error with a given amount of jitter:

Maximum SNR vs Clock Jitter
Figure 1. ADC Noise vs. Clock Jitter

For input signals that have relatively low frequency content, under 1MHz lets say, the clock jitter becomes less critical, but when the frequency of the input signal is several hundred megahertz the jitter on the clock will be the dominate source of error, and will be the limiting factor for SNR.

Here is an easy chart that shows how SNR degrades with input frequency and jitter from the clock:

 

Maximum SNR vs Clock Jitter
Figure 2. LTC2208 SNR vs. Frequency vs. RMS Jitter

Simply find the input frequency you are using on the X axis, and the required SNR on the Y axis, and you can see exactly how little jitter you will need on your clock to achieve the desired SNR. In order to combine the jitter from the clock with the jitter from the ADC you will need to sum the two terms in terms of power.

For example if you have a 100MHz input signal, and you want 78dB of SNR you will need a clock source with less than 200fs of jitter.  Typical FPGAs will have up to 50ps of additive jitter, and should not be used an ADC clock. Typically VCXOs and low jitter PLLs are the best ADC clock sources. 

It is important to note that these equations are derived from standard sampling theory and apply to all ADCs, from any manufacturer. 

When designing a system with a high speed ADC it is important to consider clock jitter. It can severely limit the SNR you can achieve in a system, and can potentially be a show stopped in a system design. Keeping the clock jitter as low as possible is just as important as the design of the front end circuitry. It should not be an afterthought, but should be considered in the first stages of the design.

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Clarence Mayott

Clarence Mayott is a mixed signal application section leader with over 10 years of experience at Linear Technology.

Beginning with the DC1151, a demo board for the LTC2246H, Clarence has designed nearly all of the high speed ADC demo boards for Linear Technology. These boards have been used for evaluation purposes in a wide range of applications. He designed demo boards with complete signal chains combining amplifiers and ADC combinations to help the end customer evaluate systems more easily. He also designed companion boards, including clock and signal source boards, to help facilitate the evaluation of high speed ADC demo boards. Clarence manages the continued development of PScope, the software used for various pipeline and SAR ADCs.

His expertise in design and layout of demo boards allows him to instruct customers on how to implement high speed ADCs into their own designs. He has worked on many technical areas, including medical, automotive and communications. His experience allows him to see schematic errors, minute layout errors, and other design flaws in designs.

With the release of the LTC2000, Clarence has expanded his knowledge base to include high speed DACs and waveform generation in addition to high speed ADCs. As an application section leader he oversees the continued development of LTDACGen a new software tool for generating complex waveforms for high speed DACs.

He has given technical trainings both within Linear Technology and to potential customers describing how to implement proper signal chains from the antenna through the FPGA.

He received an M.S. in Electrical Engineering from Santa Clara University and a B.S. degree in Electrical Engineering from California State University Polytechnic San Luis Obispo.