Increase Spectral Resolution for the LTC2387-18 Demo Board - Part 1


The LTC2387-18 is a low noise, high speed, 18-bit 15Msps successive approximation register (SAR) ADC. The combination of excellent linearity and wide dynamic range makes the LTC2387-18 ideal for high speed imaging and instrumentation applications. No latency operation provides a unique solution for high speed control loop applications. The very low distortion at high input frequencies enables communications applications requiring wide dynamic range and significant signal bandwidth. To support high speed operation while minimizing the number of data lines, the LTC2387-18 features a serial LVDS digital interface that is easy to connect to an FPGA. The LVDS interface has one-lane and two-lane output modes, allowing the user to optimize the interface data rate for each application.

The DC2290A-A is a demonstration circuit for the LTC2387-18. The sample rate (Fs) for this board is 15Msps and digitized data exits the ADC in serial fashion. The following refers to the LTC2387-18 but applies to all members of the LTC2387 family (LTC2386 & LTC2385) and to the other varients of the DC2290A demonstration circuits, the only difference being the sample rate and the number of bits.

The DC2290A demonstration circuit includes an Altera Cyclone III FPGA, which is programmed in Verilog to deserialize the ADC output data stream and deliver it onto the 18 bit parallel bus of the DC890B USB data collection card. The DC890B conditions this data so that it can be passed to a PC and displayed in PSCOPE. The PScope software collects and analyzes data from the ADC in both the time and frequency domains and displays relevant parameters for the device being evaluated. The maximum FFT size for PSCOPE is 131K, which in this case yields a spectral resolution of about 114Hz per bin. Below is a section of a typical 65K point FFT for a 9.76KHz tone under these conditions, yielding a noise per bin of –139.4dBFS.

Typical 65K Point FFT for a 9.76KHz Tone

65K Point FFT of a 9.76KHz Tone, Noise per Bin of –139.4dBFS

Improving Frequency Resolution via Downsampling & Lowpass Filter

What if we wanted more frequency resolution or wanted to observe noise levels and signals very close to zero frequency? Lowering the sample rate is one option. This should have the effect of narrowing the bin size and hence lowering the noise level per bin. The problem with this approach is aliasing. Aliasing is a normal consequence of the sampling process. It means that the analog input spectrum is sliced into chunks Fs/2 wide, which are folded on top of one another to constitute the final output spectrum. Normally the sample rate is selected such that the bulk of the analog input signal content lies below Fs/2. The signal content is limited to this area of the spectrum by lowpass filtering the analog input signal and noise. Herein lies the problem with simply lowering the sample rate – it means the user must reduce the bandwidth of the analog input signal or the lowpass filter that precedes the ADC. Neither of these measures are typically practical.

A much better alternative is to leave the sample rate alone and downsample the digitized output of the ADC. Note that in order to avoid aliasing of signals and noise (as discussed above) we must lowpass filter the output before downsampling. This is done using a digital filter, rather than an analog one. Because this can be done in an FPGA, it is easy to implement and modify. For example, if we have a spectrum that was obtained by sampling at 15Msps, we may want to increase the frequency resolution by a factor of 128. To do this effectively, the output samples must be limited to the spectrum that lies between 0Hz and 7.5/128MHz, or 58.593KHz. The samples may then be downsampled by a factor of 128 with little or no aliasing. The resolution will be increased by a factor of 128, and the noise per bin should be 21dB lower than the original spectrum.

This processing can be done by adding a module to the existing Verilog code that operates upon the 18 bit data words before they are passed along to the data collection system. The new version of code is then compiled and may be used to program the DC2290A demo board in either JTAG or Active Serial Programming mode.

Comb Integrator Cascade Filter

One simple way to lowpass filter and downsample is by using a Comb Integrator Cascade (CIC) filter. This filter is unique in that it requires no multiplication. A CIC filter is really just another name for a moving average (or boxcar) filter followed by a downsampler. Note that the impulse response of this filter is simply a series of N unity amplitude samples. Since the time response of the filter is a rectangular pulse, the frequency response is a Dirichlet function.


The first null of this function is at Fs/N, in this case 117.187KHz. Below is an example of the low frequency response of this filter.

Sinc Function

Implementing CIC Filter in Verilog

There are several ways to implement this filter in Verilog. One way is to build a shift register that holds N data words, summing the N positions of the register as each new word is loaded. The output of the summation is then downsampled to form the final output. Here is an example for N=128.

  1. First the FPGA deserializes the 18 bit data word.
  2. The word, along with a clock running at 15MHz, is passed to a module cic_128

wire [17:0] dout, dout_f;

cic_128 fir (

The first variable is the clock; the rising edge of this clock appears just after the deserialized data from the conversion is available. The next two variables are 18 bit data words – the first is the filter input and the second is the output. Here is the code for the module itself.


input clk;
input [17:0] din; //unfiltered sample

output [17:0] dout; //filtered sample

reg [2303:0] shift_reg;
reg [24:0] regout;
reg [17:0] dout;

shift_reg = 0;

wire [24:0] regout_a [63:0];
wire [24:0] regout_b [31:0];
wire [24:0] regout_c [15:0];
wire [24:0] regout_d [7:0];
wire [24:0] regout_e [3:0];
wire [24:0] regout_f [1:0];
wire [24:0] regout_g;

always @(posedge clk) //load the newest bit into the serial bit array on each rising edge of 'clk'
shift_reg <= {shift_reg[2285:0],din};
regout <= regout_g;

//divide the result by 128
dout <= regout[24:7];

genvar j;
for(j = 0;j < 64;j = j+1)
begin: echelon_a
assign regout_a[j] = {{7{shift_reg[j*18+17]}},shift_reg[j*18+17:j*18]} + {{7{shift_reg[(j+64)*18+17]}},shift_reg[(j+64)*18+17:(j+64)*18]};

for(j = 0;j < 32;j = j+1)
begin: echelon_b
assign regout_b[j] = regout_a[j] + regout_a[j+32];

for(j = 0;j < 16;j = j+1)
begin: echelon_c
assign regout_c[j] = regout_b[j] + regout_b[j+16];

for(j = 0;j < 8;j = j+1)
begin: echelon_d
assign regout_d[j] = regout_c[j] + regout_c[j+8];

for(j = 0;j < 4;j = j+1)
begin: echelon_e
assign regout_e[j] = regout_d[j] + regout_d[j+4];

for(j = 0;j < 2;j = j+1)
begin: echelon_f
assign regout_f[j] = regout_e[j] + regout_e[j+2];

assign regout_g = regout_f[0] + regout_f[1];


The heart of the module is shift_reg; this is a shift register that holds 128 x 18 bit words. These words are the data inputs din that are loaded into the shift register one after another. At each clock rising edge, the latest data word is loaded into the register and the oldest one is discarded. The sum of the 128 positions in the register is the output of the filter. This output is then scaled down by 7 bits to fit within an 18 bit word, and passed back to the main module as dout. At this point, the spectrum of these samples is just a lowpass filtered copy of the ADC output.

  1. The next step is downsampling, which is done by passing every 128th filter sample to the data collection board

Results of Part 1

The result is a spectrum that covers the Nyquist zone from DC to 58.593KHz. Using an FFT with 65K points, the bin width is 1.78Hz. Here is the FFT of the filtered and downsampled signal, with a noise per bin of –151.3dBFS.

FFT of the Filtered & Downsampled Signal

65K Point FFT of a 9.76KHz Tone, Noise per Bin of –151.3dBFS

The noise level per bin has been reduced by nearly 12dB per bin. This falls short of the predicted 21dB reduction for two reasons. First, because the filter is not ideal, there is nonzero response outside the passband. The downsampling process will alias the noise in these nonzero lobes back into the passband. The total power in these sidelobes is on the order of one tenth the power in the main lobe. Second, and more importantly, is the quantization noise in the final spectrum. For a sinusoid, the quantization noise is computed using the following formula, where N is the number of bits.

SNR = 1.76 + 6.02 * N

The final sample is quantized to 18 bits and the quantization noise will be approximately equal to 110.1dB, or 155.3dBFS per bin. The result obtained by filtering and downsampling approaches this level, revealing more spectral detail as well as resolution.

Using an Altera Cyclone III FPGA to deserialize and filter this data is resource-intensive. A compilation report of the Verilog code shows this implementation uses 74% of the available logic elements. The reason for this is the number of registers and adders required. At each sample instant, all 128 registers are added together in binary fashion, echelon after echelon. An attempt to construct a filter with a higher downsample ratio will fail, because the design will not fit into this FPGA. There are other more streamlined ways to build this type of filter, and we will cover that in the next installment. Both the Verilog and programming files for the code described herein are available on the right hand panel.

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Doug Stuetzle

Doug Stuetzle is a Senior Analog Applications Engineer at Linear Technology. He joined the company in 2003, providing applications support for active mixers, demodulators, and detectors in the RF product line. He also designed and supported the LTM9003, LTM9004, LTM9005, and LTM9013 RF – to – digital receiver modules. These modules were designed to meet the complex requirements of various digital communications standards, and encompass aspects of circuit design from GHz range RF through IF frequencies, down to a digitized output bit stream.

He is presently providing applications support for a variety of SAR and Delta Sigma A/D converters. His responsibilities include customer support, circuit design, PCB layout, and Verilog code generation for FPGA’s. He continues to expand his expertise in the areas of A/D converter drive circuits to maximize noise and linearity performance.

Prior to joining Linear Technology he spent 21 years designing RF, microwave, and optoelectronic circuits, modules, and systems for military and commercial customers. He holds an MSEE degree from Santa Clara University and a BSEE from San Jose State University.