The overriding factor limiting functionality in fiber-optic communication systems is available space. A compact APD (avalanche photo diode) bias solution with a high degree of feature integration is the key to breaking new ground in system size and performance. The LT3571 offers such a solution in a tiny 3mm × 3mm QFN package.
The LT3571 combines a current mode step-up DC/DC converter and a high side fixed voltage drop APD current monitor with an integrated 75V power switch and Schottky diode. The combination of a traditional voltage loop and a unique current loop allows customers to set an accurate APD current limit at any given bias voltage. The integrated high side current monitor provides an 8% accurate current that is proportional to the load current, making it possible to adjust the APD bias voltage via the CTRL pin. This feature-rich device makes it possible to produce a single stage boost converter to bias high voltage APDs in only 60mm2.
Low Noise APD Bias Supply
The gain of the APD is dependent on the bias voltage, so the bias supply must minimize the noise contamination from switching regulators and other sources. Figure 1 shows the LT3571 configured to produce an ultralow noise power supply for a 45V APD with 2.5mA of load current capability. The MONIN voltage is regulated by the internal voltage reference and the resistor divider made up of R1 and R2. Resistor RSENSE is selected to set the APD current limit at 200mV/1.2RSENSE – 0.2mA.
The CTRL pin can override the internal reference, making it possible to optimize the APD bias on the fly to maximize receiver performance.
When the CTRL pin is connected to a supply above 1V, the output voltage is regulated with feedback at 1V. When driven below 1V, the feedback and the output voltage follow accordingly.
The APD pin, the output of the current monitor, provides a voltage to the APD load that is fixed 5V below the MONIN pin. The LT3571 includes a precise current mirror with a factor-of-five attenuation. The proportional current output signal at the MON pin can be used to accurately indicate the APD signal strength. The voltage variance of APD pin voltage is only ±200mV over the entire input current range and the whole temperature range. Figure 2 shows the evaluation board for this topology.
The topology uses several filter capacitors to achieve ultralow noise performance. The capacitor at VOUT pin and the 0.1µF capacitor at the APD pin suppress switching noise. The 10nF feedforward capacitor across the MONIN and FB pins filters out high frequency internal reference and error amplifier noise. Figure 3 shows the measured switching noise is less than 500µVP–P at 1mA load current. This exceptionally low noise bias voltage gives the APD greater sensitivity and dynamic range.
Fast APD Current Monitor Transient Response
Design efforts in modern communications systems increasingly focus on 10Gbits/s GPON systems, which demand that the transient response of the APD current monitor is less than 100ns for a two-decades-of-magnitude input current step. To meet this challenging requirement, many designers rely on a simple discrete current mirror topology to reduce parasitic capacitance on the signal path, sacrificing monitor accuracy and board space. In contrast, the LT3571’s APD current monitor is carefully designed to provide not only a fixed voltage drop and high accuracy, but also the required fast transient response.
Figure 4 shows a compact circuit that responds quickly to current transients. Unlike the ultralow noise topology shown in Figure 1, the filter capacitor at the APD pin is moved to the MONIN pin. C2, C3 and RSENSE form a π filter to isolate the APD current monitor from high frequency switching noise. The capacitor at the MON pin is also removed to reduce the transient delay on the measurement path.
The transient speed is measured using the same technique described in the Linear Technology Design Note 447 “A Complete Compact APD Bias Solution for a 10GBit/s GPON System.” Figures 5 and 6 show the measured input signal falling transient response and input signal rising transient response, respectively, where the input current levels are 10µA and 1mA. Note that there is an inversion and DC offset present in the measurement. The measurements show a transient response time of less than 100ns, well within the stringent speed demands of the 10Gbits/s GPON system.
APD Bias Voltage Temperature Compensation
Typically, the APD reverse bias voltage is designed with a compensatory positive temperature coefficient. This can be easily implemented via the CTRL pin of the LT3571—a less complex and expensive solution than typical microprocessor-controlled methods.
The simplest scheme uses a resistor divider from the VREF pin to the CTRL pin, where the top resistor in the divider is an NTC (negative temperature coefficient) resistor. While simple, this method suffers from nonlinear temperature coefficient of the NTC resistor. A more precise method uses a transistor network as shown in Figure 7. The PTC (Positive Temperature Coefficient) of the CTRL pin voltage is realized by an emitter follower of Q1 and a VBE multiplier of Q2.
then the CTRL pin voltage is
Given VOUT at room and dVOUT/DT, the R1/R2 and R8/R7 can be calculated as follows
Resistors R5–R9 are selected to make I(Q1) = I(Q2) ≈ 10µA, and
Simulation using LTspice always gives a good starting point. The circuit shown in Figure 7 is designed to have VAPD = 50V (VOUT = 55V) at room and dVAPD/dT = 100mV/°C (dVOUT/dT = 100mV/°C). The measured temperature response is shown in Figure 8, which is very close to the design target.
The LT3571 is a highly integrated, compact solution to APD bias supply design. It provides a useful feature set and the flexibility to meet a variety of challenging requirements, such as low noise, fast transient response speed, and temperature compensation. With a high level of integration and superior performance, the LT3571 is the natural choice for APD bias supply design.