An Inside Look at High Speed ADC Accuracy, Part 3

Signal chain accuracy analysis can be an overwhelming task to understand in any design. In Part 2 of this series, many errors were discussed that accumulate throughout the signal chain and are eventually seen by the converter. Remember, the converter is the bottleneck of the signal chain and ultimately decides how accurately the signal can be represented. Therefore, choosing the converter is key to setting the overall system requirements. In this article, the focus will continue to build on this knowledge, analyzing the types of dc errors that can accumulate throughout the given signal chain. 

Two types of errors can accumulate through a signal chain—dc and ac. Errors that are dc or static, such as gain and offset, provide an understanding of the signal chain’s accuracy or sensitivity. Errors of the ac variety, otherwise known as noise and distortion, set the bounds 
on performance and dynamic range of the system. Both are important to understand because they both ultimately determine the resolution of the system.

This article will specifically analyze dc errors, breaking down each inaccuracy as it relates to both passive and active devices. A matrix or spread-sheet will be developed to show how to add or accumulate error within the signal through different methods.

For ac errors, refer to References 10 and 11. Here, a review of noise basics, such as bandwidth summation and error accumulation from an ac perspective, can determine the overall SNR of analog signal chain design. 

Figure 1. This simple data acquisition signal chain system was developed to provide 0.1% accuracy.

Signal Chain Recap

In Part 2 the goal was to design a simple data acquisition system that could meet 0.1% accuracy (Figure 1). Meaning for every 1 V input, the output would be either 0.99388 V or 1.00612 V. Therefore, the converter was defined to have a capable dynamic range of 60 dB or 9.67ENOB, assuming a 10 V full scale. It has two stages of amplifiers, a multiplexer, and an analog-to-digital converter (ADC). The sensor, cables, connector(s), printed circuit board (PCB) parasitics, and any outside influences/errors will be neglected in this analysis since this will depend heavily on the application or signal the designer is trying to measure.

To define references for each error, each stage of the analysis should be broken down into individual sections. The first stage of the data acquisition signal chain is a simple difference amplifier (Figure 2). The amplifier has a gain of 4× and input impedance of 500 Ω. The capacitors are in place for optional filtering purposes.


Figure 2. A difference amplifier is the first stage of the data acquisition signal chain.

The amplifier’s output signal is then applied to one of the eight inputs of the multiplexer (Figure 3). Each input is buffered with a damping resistor (RO) to minimize charge kickback from the multiplexer’s channel switching. Each channel internally will have some parasitic or characterized RO per the multiplexer’s data sheet specifications.


Figure 3. This 8:1 multiplexer has eight buffered inputs.

The resulting channel signal is then applied to a unity-gain buffer stage amplifier (Figure 4). The resistors are applied to minimize input bias current imbalance.


Figure 4. A channel signal would be applied to this type of buffer amplifier.

After the signal is buffered, it’s applied to the 12-bit, 1 MSPS ADC where it finally enters the digital domain (Figure 5). The series resistor is applied to buffer or dampen the signal between the amplifier and converter, adding source resistance between the two devices. This minimizes charge kick-back from the converter to the amplifier, much like the multiplexer. This also helps the amplifier output settle and prevents it from oscillating. 


Figure 5. Once a signal is buffered, it’s applied to a 12-bit, 1 MSPS ADC.

The capacitor provides a simple low-pass antialiasing filter (AAF) to attenuate signals and noise outside the band of interest. The design of the AAF depends greatly on the system’s design and application. Lastly, the pull-up and pull-down diodes add input protection against any fault conditions of extreme signal overload conditions that may be applied to the converter’s input.

Now that all of the signal chain components have been defined, let’s start looking at the errors associated with each stage. In the following sections, both passive and active errors will be reviewed based on each of the signal chain’s stages discussed here.

DC Passive Errors

All passive components have errors associated with them, especially resistors. Resistors seem like simple devices, but they can cause errors throughout any signal chain if not specified correctly for the design. Choosing the right type of resistor and its composition isn’t covered here. Keep in mind, though, that depending on the application, some resistor types may be better suited than others. 

Resistive dc errors result from nonideal resistor tolerances. Simply specifying the value tolerance isn’t enough. However, being overly critical about resistor error tolerances can also yield diminishing returns and overcomplicate the analysis. At least four critical specifications need attention when specifying a resistor type for a given signal chain:

  1. Value tolerance, usually specified in %.
  2. Temperature coefficient or drift, usually specified in ppm/°C.
  3. Life drift or qualification, usually specified in % over a set amount of hours (usually in 1000s).
  4. Value tolerance ratio, value tolerance specified in % when two or more resistors are present in a network or the same package and are matched in value.

To give an example of how resistor errors can accumulate (Figure 6), let’s look at the following: A 100 Ω resistor with a value tolerance of 1%,drift of 100 ppm/°C, and life tolerance of 5% will yield a resistance from 93.15 Ω to 106.85 Ω over a 5000 hour life within an 85°C temperature range:

Figure 6. This diagram illustrates a resistor error model.

Total Tolerance (RVALUE + RTOL + RCOEFF + RLIFE) = (RVALUE + ((RTOL/100) × RVALUE)+ (((RCOEFF × 0.000001) × TempRange) ×RVALUE) + ((RLIFE/100) × RVALUE))= 94 Ω to 106 Ω.

Hard to find information side note: some components have a life specification of only 1000 hours. Yet the design may call for a much longer time— say, 10,000 hours. To get around this, don’t multiply the 1000 hour figure by 8.77 (8766 hours/year); it’s much too pessimistic. Long-term drift in any precision analog circuit is going to have some amount of “random walk” to it. It’s more correct to take the square root of this number or √8.766 = ~3× the 1000 hour figure. Therefore, a 10,000 hour life number is √10.000 = 3.16 × 1000 hour specification and so on.

It should be noted that capacitors and inductors have errors too. However, these errors are usually negligible and add no substantial value for this type of dc analysis. These devices are also reactive in nature and have the greatest impact on filtering and bandwidth tolerances, which again isn’t applied in this particular dc analysis.

DC Active Errors

The signal chain described in Figure 1 has the most common building blocks, which describes one approach to implementing a data acquisition system. It consists of two amplifiers, a multiplexer, and an ADC. Keep in mind, however, that many types of active devices describe all sorts of signal chains and different system topologies. All active devices will have some sort of dc error(s) when implementing this type of analysis. It’s important to decide which of these errors need to be taken into account to understand the accuracy of the system under design.

Basically, two types/groups of errors are involved in dc accuracy. These errors are individual and global to all active devices. Individual active device errors will exhibit their known dc error relative to that device only. Such errors can be found in their respective data sheets. For example, input offset voltage of an amplifier would be considered an individual error because this error is particular to this active device only. 

Global errors are common to each of the active devices in the signal chain or system by the same amount, but exhibit a different error based on the active device’s individual performance (Figure 7). A global error example would be line regulation of the bus’s supply and temperature. Now, let’s break down each of these errors for the three active devices shown in the signal chain.

It’s well-known that amplifiers are still far from ideal. They have many errors that are commonly listed in the data sheet. Offset voltage and bias current are two common errors, but it’s also important to include any drift errors, long-term errors, and isolation errors such as powersupply rejection ratio (PSRR). Table 1 shows a listing of the following errors that should be considered when using amplifiers.

Table 1. Individual Amplifier Error
Specification Error
Input Offset Voltage Drift (V/C)
3.50 × 10–6
Input Bias Current Drift (A/C) 200 × 10–15
Input Bias Current (A) 150 × 10–9
Long-Term Drift (1000 hrs)(V) 3.75 × 10–3
Input Offset Current (A) 10 × 10–9
Power Supply Rejection Ratio (PSRR)(dB) –120
Input Offset Voltage (V) 200 × 10–6
Common-Mode Rejection Ratio (CMRR)(dB) –80

Multiplexers typically have fewer errors than an amplifier. The on resistance and channel isolation are the most influential multiplexer dc errors. Table 2 lists the errors that should be considered when using multiplexers.


Figure 7. Active devices suffer from two types of dc accuracy errors—individual and global.

Table 2. Individual Multiplexor Error
Specification Error
On Resistance (RON)(Ω) 400.00
Resistor Coefficient (ppm/°C) 200.00
Resistor Tolerance (%) 20.00
Channel Isolation (dB) –70.0

Converter errors were specifically reviewed in the first part of the series (shown below). Offset, gain, and DNL are well-known and understood. It’s important to include PSRR as well. The following list of converter errors should be considered when using ADCs from Part 1:

  • Relative accuracy, DNL, which was defined as ±0.5 LSBs.
  • Relative accuracy tempco, DNL tempco, which is typically included in the relative accuracy specification in the data sheet.
  • Gain tempco error, which was ±2.5 LSBs (from the previous example).
  • Offset tempco error, which was ±1.3 LBs from the previous example).
  • Power supply sensitivity, which is typically in the form of low frequency PSRR within the first Nyquist zone; this can typically be expressed as 60 dB or ±2 LSBs for a 12-bit ADC.

To keep the article at a reasonable length, this discussion will not go into the details on how each of these errors are derived within the active device itself. All of these errors are well-defined and described in various papers and texts. What’s important to note here is that all of the essential errors have been considered so that the analysis is robust enough to meet the system’s accuracy target specifications.

Individual active device errors have been suggested and defined. Now global errors should be considered, which influence the signal chain as a whole (Table 3). In this simple example, only temperature and line regulation will be factored into the analysis as global errors. However, it is important to add any other outside influences that may be inherent to the particular application or design.

Table 3. Global Signal Chain
Specification Error
Temperature (°C) –45 to +85
Power-Supply Line Regulation (%/V) 50 × 10–3

Putting It All Together

Now that all of the errors have been defined both actively and passively, it’s time to put them into a spreadsheet to calculate dc accuracy of the signal chain. Table 4 shows one such approach to accomplish this task. 

Even though there are many ways to go about analyzing signal chain accuracy, using the spreadsheet method offers the greatest flexibility. It also provides a solid understanding on how to go about crushing all of these error numbers down within the signal chain design. This method allows the designer to make quick and effective trade-offs between many suitable devices that may be considered for the design.

Take the time to produce a spreadsheet that has a good layout and is orderly. At the top, global errors and signal chain specifications are defined because these numbers affect the performance of the signal chain as a whole. The amplifier specifications/errors were also placed at the top, since there are many errors and two amplifier stages throughout the signal chain. 

Continuing down, on the left-hand side of the spreadsheet, all of the errors are divided down into each circuit stage. The resistor errors were also grouped with each stage to understand the trade-offs accordingly. The right-hand side shows a continuous calculation and accumulation of error as the signal flows to and from each stage.

In the calculations, all of the errors are put into a voltage format. This makes it easier, since the converter is at the end of the signal chain and has an input full scale described in voltage. RTO (refer to output) is used to describe the continuous accumulation of errors from one stage to the next. Each stage also produces a separate sum total and RSS (root sum square) total to show how the errors are accumulating depending on the method used.

Therefore, the end result in Table 4 shows a total accumulation of ±2.6% summed error and a ±1.6% RSS error. This is for the entire signal chain discussed throughout this article, given the data sheet specifications for each part and the global conditions stated previously at 26°C. 

Total Accumulation

Accuracy can be calculated in many ways and can take on many forms. Depending on how this is viewed by the designer, it should be understood and documented to avoid creating any misrepresented results. Remember from Part 1, simply taking the root sum square (RSS) of all these error sources might seem overly pessimistic. Yet, a statistical tolerance may be overly optimistic (the total sum of errors divided by the number of errors). Finding the actual tolerance of the entire signal chain error should be somewhere between these two thoughts or methods.

Therefore, when adding (accumulating) accuracy errors in the entire signal chain or any accuracy system analysis, the designer could use a weighted error source approach (as shown in the ADC example in Part 1), then RSS these error sources together. This will provide the best method in determining the entire signal chain’s overall error. 


Many errors occur with both passive and active devices. Not all are important, but keep in mind those that are important to the signal chain application at hand. Not all errors may be valid for every application. Deciding which errors are the most dominant or have the most influence or weight is essential to any dc accuracy error analysis. A spreadsheet was developed to show how the signal chain example in this article meets the requirements of <±2.0% accuracy.

Choosing the right passives can make just as much a difference in the total accumulated error in the signal chain as well as the active devices. Creating and partitioning a spreadsheet makes it simple and tidy to consider many different devices and trade-offs quickly. Finally, accumulation of error can take on many forms, and the most common practice used is the RSS accuracy method. 

However, some may argue that a weighted summation approach of errors is the right way to determine a true “worst-case dc error.” If not, this can easily cause a signal chain to be overdesigned, leading to more parts to compensate for the original set of errors. Not to mention the increase in cost and the design’s size, weight, and power (SWaP).

Table 4. Full Signal Chain Analysis Example
Signal Chain Specifications Value Specification Minimum Unit Maximum
Input Signal(V) 1 × 101 Amplifier Specifications
ADCNumber of Bits 1.2 × 101 Input offset voltage drift(V/C) 3.5 × 10–6 V 3.50 × 10–6
ADCInput Full Scale(Diff VP-P)with Margin 9.97 × 100 Input bias current drift(A/C) 2 × 10–13 A 2 × 10–13
ADCInput Full Scale(Diff VP-P) 1 × 100 Input bias current 1.5 × 10–7 A
ADCLSB Size(VP-P) 2.44 × 10–3

Long-term drift(V) (5000 hrs)

3.75 × 10–3 V
Temperature Range(–50°C to +80°C) 1 = 26°C 1 × 100 Input offset current(A) 1 × 10–8 A
Kelvin(K) 2.9915 × 102 PSRR (dB) –1.2 × 102 V 3.50 × 10–9
Boltzmann’s Constant(W-s/K) 1.38 × 10–23 Input offset voltage(V) 2 × 10–4 V
LDO Reg Line Regulation(%/V) 5 × 10–2 1ststage CMRR(dB) –8 × 101 V 5 × 10–4
1stStage Amplifier CMR(V) 5 × 100 ADCbuffer CMRR(dB) –8 × 101 V 5 × 10–4
Amplifier Buffer CMR(V) 5 × 100 En_op(V/√Hz) 6 × 10–9 V 3.36 × 10–6
Supply Voltage 7 × 100 In_op(nA/√Hz) 8 × 10–13 A 4.4829 × 10–10
BW (Hz) 2 × 105 Noise voltage(VP-P) 1.5 × 10–7 V 5.303 × 10–8
Nosie BW(Hz)—1st-Order System 3.14 × 105
Nosie BW(Hz)—2nd-Order System 2.444 × 105
Inputs Minimum Unit Maximum
1stStage Amplifier Circuit—Difference Amplifier Total tolerance(RF1+ RTOL+ RCOEFF+ RLIFE) 2.48122 × 104 Ω 2.49878 × 104
Amplifier Gain(Av) 1 × 100 Total tolerance(RF1+ RTOL + RCOEFF+ RLIFE) 2.48745 × 104 Ω 2.49878 × 104
RI1(Ω) 2.49 × 104 Total tolerance(RP1+ RTOL+ RCOEFF+ RLIFE) 1.24217 × 104 Ω 1.24939 × 104
RF1(Ω) 2.49 × 104 Total tolerance(RO1+ RTOL + RCOEFF + RLIFE
9.96475 × 101 Ω 1.003525 × 102
RP1(Ω)= RI1|| RF1 1.245 × 104 Total tolerance(Gain = RF1/RI1) 9.954660 × 10–1 Gain 1.0071 × 100
RO1(Ω) 1 × 102 Signal level 9.9547 × 10 V 1.00707 × 101
Resistor Coefficient(ppm/°C)
2.5 × 102 Input current offset × RP1—RTO 8.748575 × 10–7 V 8.839525 × 10–7
Resistor Tolerance(%) 1 × 10–1 Input offset voltage—RTO 4.060773 × 10–4 V 4.084398 × 10–4
Resistor Life Tolerance(%), 5000 hrs 2.5 × 10–1 Input bias error—RTO –2.16197 × 10–5 V 2.17455 × 10–5
1ststage total accuracyerror(sum) 1.3831 × 10–3 V 1.4346 × 10–3
1ststage total accuracy error(RSS) 1.0774 × 10–3 V 1.0837 × 10–3
Signal level(sum) 9.9560 × 100 V 1.00722 × 101
Signal Mux Signal level(RSS) 9.9557 × 100 V 1.00718 × 101
RON(Ω) 4 × 102 Total tolerance(RON+ RTOL+ RCOEFF) 3.199200 × 102 Ω 4.8008 × 102
Resistor Coefficient(ppm/C) 2 × 102 Channel-to-channel isolation error 1.5811 × 10–3 V 1.5811 × 10–3
Resistor Tolerance(%) 2 × 101
Channel Isolation(dB) –7 × 101
Amplifier Buffer Circuit
Resistor Coefficient(ppm/C) 2.5 × 101 Total tolerance(RI2+ RTOL+ RCOEFF+ RLIFE)
55.9426 × 104 Ω 5.60574 × 104
Resistor Tolerance(%) 1 × 10–1 Total tolerance(RF2+ RTOL+ RCOEFF+ RLIFE) 5.61424 × 103 Ω 5.62576 × 104
Resistor Life Tolerance(%), 5000 hrs 2.5 × 10–1 Total tolerance(Gain = RF2/RI2) 1.0015 × 100 Gain 1.0056 + × 100
Unity-Gain Buffer(Av) 1 × 100 Signal level(sum) 9.9727 × 100

V 1.01305 × 101
RI2(Ω) 5.6 × 104 Signal level(RSS) 9.9724 × 100 V 1.01301 × 101
RF2(Ω) 5.62 × 104 Input current offset × RI2—RTO 2.805049 × 10–4 V 2.805039 × 10–4
RADC(Ω) 3.32 × 101 Input offset voltage—RTO 3.9595 × 10–3 V 3.9758 × 10–3
RE1(Ω), (Diode Resistance) 1 × 10–1 Input bias error—RTO 1.56844 × 10–5 V 7.43156 × 10–5
RE2(Ω),(Diode Resistance) 1 × 10–1 ADCbuffer total accuracy error(sum) 4.7564 × 10–3 V 4.8334 × 10–3
ADCbuffer totalaccuracy error(RSS) 4.0009 × 10–3 V 4.0179 × 10–3
Signal level(sum) 9.9775 × 100 V 1.01353 × 101
Signal level(RSS) 9.9764 × 100 V 1.01342 × 101
ADC Circuit
Linearity, INL(LSB)– 1.5 = DS 1.5 × 100 V 3.6621 × 10–3
Offset Error(LSB)– 10 = DS 1 × 101 V 2.44141 × 10–2
Gain Error(%FSR)– 0.1 = DS 1 × 10–1 V 1 × 10–2
Offset Drift(ppm/C)– 30 = DSFT 3 × 101 V 3 × 10–4
Gain Drift(ppm/C)– 40 = DSFT 4 × 101 V 4 × 10–4
PSRR(dB)– 5 LSB = DSFT –6 × 101 V 3.5 × 10–6
Clock Rate, Fs(Hz) 4 × 105 ADCtotal accuracy error V 2.66403 × 10–2
Ideal 12-bit SNR(dB) 7.4 × 101 Total accuracy error(summed) 3.43610 × 10–2 V 3.44895 × 10–2
Data Sheet Min SINAD FS(dB) 6.5 × 101 Total accuracy error(RSS) 2.7007 × 10–2 V 2.70097 × 10–2
Data Sheet ENOB(bits) 1.05 × 101 Signal level(summed) 1.00041 × 101 V 1.01620 × 101
Signal level(RSS) 1.00031 × 101 V 1.01608 × 101
DC accuracy(± – %) 1.5774 × 100 %


1Cletus J. Kaiser. The Resistor Handbook. 2nd Edition, 1-11.


3Walt Kester. The Data Conversation Handbook. Analog Devices Inc.

4Walter G. Jung.  IC Op Amp Cookbook. 3rd  Edition.

5AN102: “Errors, What Are They and How Bad Can They Be?” Dataforth Corp.

6AN504: “SCM5B, Interpreting Drift Specifications.” Dataforth Corp.

7Eamon Nash. Errors and Error Budget Analysis in Instrumentation   Amplifier Applications.Analog Devices, Inc. 

8Eamon Nash. A Practical Review of Common Mode and Instrumentation  Amplifiers. Analog Devices, Inc.

9Robert G. Irvine. “Operational Amplifier Characteristics and  Applications.” 3rd Edition.

10MT-230, Noise Considerations in High Speed Converter Signal Chains. Analog Devices, Inc.

11“Noise Considerations in High Speed Converter Signal Chains.” DSP—  FPGA, August 2013.

12Rob Reeder. “An Inside Look at High Speed ADC Accuracy,” Electronic   Design, June, 2015.

13Rob Reeder. “An Inside Look at High Speed ADC Accuracy, Part 2.”   Electronic Design, November 2015.

14CN-0350: “12-Bit, 1 MSPS, Single-Supply, Two-Chip Data Acquisition System for Piezoelectric Sensors.” Analog Devices, Inc.

Об авторах

Rob Reeder

Rob Reeder

Rob Reeder was a senior system application engineer with Analog Devices Inc. in the High Speed Converter and RF Applications Group in Greensboro, NC. He has published numerous papers on converter interfaces, converter testing, and analog signal chain design for a variety of applications. Formerly, Rob was an applications engineer for the Aerospace and Defense Group for five years focusing on a variety of radar, EW, and instrumentation applications, and he was part of the high speed converter product line for nine years. His prior experience also includes test development and analog design engineer for the Multichip Products Group at ADI, designing analog signal chain modules for space, military, and high reliability applications for five years. Rob received his M.S.E.E. and B.S.E.E. degrees from Northern Illinois University in DeKalb, Ill., in 1998 and 1996, respectively.