TigerSHARC Processor Roadmap
The key to increasing performance density is maintaining a balance between greater computational performance, larger amounts of on chip memory integration, and greater I/O bandwidth. Improvements, increased processor clock rates, architectural enhancements, utilization of new memory technologies, and higher bandwidth I/O interfaces will enable TigerSHARC-based designs to increase system level performance while reducing costs, power consumption, and size.
By basing designs on a TigerSHARC programmable processor, applications in wireless communications, military, industrial, imaging, and medical markets will be able to leverage IP reuse from generation to generation reducing R&D costs and time to market. The newest entries into the TigerSHARC family, the ADSP-TS201S, ADSP-TS202S, and ADSP-TS203S, offer new levels of performance density with 4800 MMACs of 16-bit performance, 3600 MFLOPS of floating-point performance, 24 Mbits of on- chip memory, and 5 Gbytes of I/O bandwidth.