TigerSHARC Processor Architectural Features
Flexibility without compromise—the TigerSHARC® Processor provides leading-edge system performance while keeping the highest possible flexibility in software and hardware development.
The TigerSHARC Processor's balanced architecture utilizes characteristics of RISC, VLIW, and DSP to provide a flexible, "all software" approach that adds capacity while reducing costs and bills of material.
Adapts to evolving signal processing demands
The TigerSHARC's unique ability to process 1-, 8-, 16- and 32-bit fixed-point as well as floating-point data types on a single chip allows original equipment manufacturers to adapt to evolving telecommunications standards without encountering the limitations of traditional hardware approaches that rely on ASICs, FPGAs, and ASSPs.
Having the highest performance DSP for communications infrastructure and multiprocessing applications available, TigerSHARC allows wireless infrastructure manufacturers to continue evolving their design to meet the needs of their target system, while deploying a highly optimized and effective Node B solution that will realize significant overall cost savings.
Multiprocessor, general-purpose processing
The TigerSHARC Processor's balanced architecture optimizes system, cost, power, and density. A single TigerSHARC Processor, with its large on-chip memory, zero overhead DMA engine, large I/O throughput, and integrated multiprocessing support, has the necessary integration to be a complete node of a multiprocessing system.
This enables a multiprocessor network exclusively made up of TigerSHARCs without any expensive and power-consuming external memories or logic.
Parallelism and high throughput
- Up to four 32-bit instructions per cycle
- Large on-chip memory perfect for internal execution of up to 64,000 point FFTs
- High throughput internal and external bandwidth enables high sustained computation rates
TigerSHARC Processor families