Design Note 132: Fast Current Feedback Amplifiers Tame Low Impedance Loads

Introduction

Three current feedback amplifiers (CFAs) now available from Linear Technology can considerably ease the task of driving low impedance loads. This Design Note reviews the capabilities of the LT1206, LT1207 and LT1210 CFAs and addresses some design issues encountered when using them. These CFAs are fast and capable of delivering high levels of current. They can be readily compensated for reactive loads and are fully protected against thermal and short-circuit faults. Table 1 summarizes their electrical characteristics.

Table 1. Fast Current Feedback Amplifier Specifications
Part Number Number of CFAs Bandwidth (MHz) Rated Output Current (A) Supply Range (V)
Slew Rate (V/μs) (Note 1) Thermal Resistance
 θJA (°C/W) (NOTE 2)
Supply Current Low Power OP / Shutdown
LT1206 1 60 0.25 ±5 to ±15 ILIM/CLOAD 
to 900
DD = 25, PDIP = 100 
SO = 60, TO-220 = 5
20 Yes
LT1207 2 60 0.25  ±5 to ±15  ILIM/CLOAD
to 900
SO = 40 2 X 20 Yes
LT1210 1 35 1  ±5 to ±15 ILIM/CLOAD
to 1000
DD = 25,
SO = 40 
TO-220 = 5
30 Yes
Note 1: Slew rate depends on circuit configuration and capacitive load.
Note 2: θJA on SO packages measured with part mounted to a 2.5mm thick FR4 2oz copper PC board with 5000mm2 area.

Driving Transformer-Coupled Loads

Transformer coupling is frequently used to step up transmission line signals. Voltage signals amplified in this way are not constrained by local supply voltages, so the amplifier’s rated current rather than its voltage swing usually limits the power delivered to the load. Amplifiers with high output current drive are therefore appropriate for transformer-coupled systems.

Figure 1 shows a transformer-coupled application for ADSL in which an LT1210 drives a 100Ω twisted pair. The 1:3 transformer turns ratio allows just over 1W to reach the load at full output. Resistor RT acts as a primary side back-termination and also prevents large DC currents from flowing in the coil. The overall frequency response is flat to within 1dB from 500Hz to 2MHz. Distortion products at 1MHz are below –70dBc at a total output power of 0.56W (load plus termination), rising to –56dBc at 2.25W. If RT is removed, the amplifier will see a load of about 11Ω and the maximum output power will increase to 5W. A DC blocking capacitor should be used in this case.

Figure 1. Twisted Pair Driver ADSL. Voltage Gain is About 6; 5VP-P Input Corresponds to Full Output.

Bridging can be used to increase the output power transferred to a transformer. Differential operation also promotes the cancellation of even-order distortion. Figure 2 shows a differential application using an LT1207 as a bridge driver for HDSL. The dual CFA is configured for a gain of ten, delivering a 10VP-P signal to the nominal 35Ω load impedance. The output signal amplitude remains flat over an 8MHz bandwidth.

Figure 2. Bridge Driver for HDSL.

Driving Capacitive Loads

The devices in Table 1 combine the high output current required to slew large capacitances with appropriate frequency compensation. All of the CFAs described here are C-Load amplifiers and are stable with capacitive loads up to 10,000pF.

A good example of a difficult capacitive load is a clock driver for a charge-coupled device (CCD). These devices require precise multiphase clock signals to initiate the transfer of light-generated pixel charge from one charge reservoir to the next. Noise, ringing or overshoot on the clock signal must be avoided. Two problems complicate clock generation. First, CCDs present an input capacitance (typically 100pF to 3300pF) which is directly proportional to the number of sensing elements (pixels). Second, CCDs often require the clock’s amplitude to exceed the logic supply. The amplifying filter in Figure 3 addresses these issues. Both CFAs in the LT1207 are configured for a third-order Gaussian lowpass response with 1.6MHz cutoff frequency (one section is shown). This transfer function produces clean clock signals with controlled rise and fall times. Figure 4 shows the LT1207’s quadrature outputs driving two 3300pF loads that simulate a CCD image sensor. Ringing and overshoot are notably absent from the clock signals, which have rise and fall times of approximately 300ns.

Figure 3. CCD Clock Driver.

Figure 4. CCD Clock Driver Waveforms.

Об авторах

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Sean Gold

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William Jett