The ADF4351 is a wideband fractional-N and integer-N phase- locked loop PLL that covers frequencies from 35 MHz to 4400 MHz. The device has an integrated voltage controlled oscillator (VCO) with a fundamental frequency range from 2200 MHz to 4400 MHz. Multi-octave operation is achieved through the use of a bank of frequency dividers.

The ADL5801 is a high linearity, double balanced, active mixer with an integrated LO buffer amplifier that supports RF frequencies from 10 MHz to 6000 MHz. The mixer has a bias adjust feature to optimize the input linearity, noise figure and dc operating current. The circuit shown in Figure 1 has a simple LO interface for applications that require broadband up or down conversion. The interface provides coverage for RF frequencies ranging from 35 MHz to 4400 MHz.

The ADF4351 PLL has a differential LO output interface, and the ADL5801 is optimized for differential LO drive. Differential interfaces provide common-mode noise rejection and cancellation of even order harmonics.

Normally, pull-up bias inductors are recommended at the output port of the ADF4351. This solution delivers higher output power but limits the frequency range of the device. The standard evaluation board is equipped with two 7.5 nH pull-up inductors, which is optimal for frequencies above 500 MHz. In the Figure 1 circuit, the bias inductors are replaced with two-50 Ω pull-up resistors to reduce the frequency dependence of the output interface. This change results in lower power delivered at the output; however, the ADL5801 can tolerate this limitation since the device is specified to operate at LO drive levels as low as −10 dBm. Figure 2 is a comparison of the output power delivered by the device with resistive and inductive pull-up networks.

The resistive pull-up network presents a nominal differential impedance of 100 Ω at the output, and the differential input impedance of the LO port of the ADL5801 is 50 Ω. The impedance mismatch in the LO path of the mixer does not degrade the circuit performance. However, it is suggested that the length of the traces connecting the devices be kept as short as possible to minimize effects of the impedance mismatch.

The PLL-mixer interface described above exhibits excellent broadband performance as shown in Figure 3 and Figure 4. The circuit maintains an input IP3 of more than 25 dBm at frequencies below 3500 MHz, and 23 dBm up to 4400 MHz. The circuit exhibits conversion gain of more than −0.7 dB and noise figure less than 12.2 dB across the operating frequency band.

The power consumed by the circuit depends on the frequency of operation and the mixer’s bias point. The ADF4351 activates a combination of sections in its divider network to generate output frequencies that span multiple octaves. This combination dictates the power consumption of the PLL. For example, when the PLL is programmed to output a frequency of 35 MHz, the device activates all six divider networks and consumes 132 mA of current. This point represents the worst-case power consumption point for the device. Similarly, the bias level of the ADL5801, which can be used to adjust IP3 and noise figure, determines the power consumed by the mixer. The VSET pin is used to adjust the bias level of the device. Figure 5 and Figure 6 show the dc current, input IP3, and noise figure performance of the mixer as a function of the VSET voltage.

The VSET level is directly proportional to the dc operating current and input IP3, while the noise figure is inversely proportional to the VSET voltage. The mixer exhibits the best linearity at a VSET voltage of 3.6 V. At a mixer bias level of 3.6 V and the worst-case power consumption point for the PLL (all dividers on), the circuit consumes approximately 1.14 W.