Two buses connect the ADF7020
ISM transceiver with the ADuC7060 precision microcontroller. Both buses are serial and bidirectional. One of these buses configures the transceiver, and it requires four microprocessor ports. The second bus is the data bus, which enables the data transaction between controller and transceiver. This bus requires at least three microprocessor ports. In this particular application, two ports are used instead of one bidirectional port with two interrupts. This simplifies the software but necessitates the use of an extra diode and resistor to separate incoming and outgoing data streams. A parallel combination of two Schottky diodes ensures a logic low, which is less than 200 mV. The BAT54C has two diodes in the same package (connecting Pin 1 and Pin 2 together for a parallel configuration). All digital ports on the ADuC7060 have programmable pull-up resistors; however, an external pull-up resistor is also required. With a data rate of 10 kbps, a 4.7 kΩ resistor works well.
Three factors determine the overall current drawn by the circuit: the requirement of the individual components in both sleep and active modes), the amount of time the system is active, and the amount of time the transceiver itself is active.
The first factor is addressed by choosing low power components such as the ADuC7060 and the ADF7020. The second factor, minimizing the activity of the system, is achieved by keeping the system inactive as long as possible. It is worth considering the tradeoff between integer versus floating point arithmetic—in many cases, integer is sufficient, has a shorter execution time, and, thus, provides greater savings. The final factor, reducing air time, is achieved in part by using a protocol with minimum overhead, but also to a large extent by using the ADF7020, which has very high receiver sensitivity and good out-of-band rejection, thus maximizing the probability that the data package contains correct data.
The system spends the majority of time in deep sleep mode, with a current consumption of 50 μA to 60 μA (depending on ambient temperature). Timer 2 wakes the system every second. Every 60 seconds, an ADC measurement is executed, linearized, and transmitted. Timer 2 can wake the system from deep sleep; the other three timers cannot. Timer 2 is 16-bit, meaning that it wakes every second when running from a 32 kHz clock (in sleep mode). After the ADC is started, the system goes into pause mode (see the ADuC7060 data sheet for more information). This is a reduced power mode, albeit not as reduced as deep sleep. The ADC wakes the system when finished. A temperature value is calculated from the ADC results and is packaged and transmitted.
Packaging essentially means placing appropriate data in a buffer. In this case, the data consists of a 4-byte floating point temperature value and a 2-byte CRC (cyclic redundancy check). In a more complex system, a header with node address, received signal strength, and other information precedes this data. Before sending this buffer to the ADF7020 transceiver, an 8-byte preamb to help synchronize the receiving node and a 3-byte synchronization word, or sync word, are sent. This is a unique 3-byte number that is checked for a match at the receiver node before a package can be received.
The hardware is very similar on the receiving side; an ADF7020 transceiver is configured to listen for the unique sync word. After the sync word is received, the data package follows. The data is sent to the PC via the UART.
Flowcharts for the main loops of both the measurement node and the base receiving node are displayed in Figure 2.
Figure 2. Measuring and Receiving Node Main Loop Flowcharts
There are many modulation schemes supported by the ADF7020. In this case, the GFSK (gaussian frequency shift keying) is used. This has the benefit of having very good spectral efficiency. In this mode, the ADF7020 generates the data clock both when transmitting and receiving. The rising edge of this clock (DATA CLK) generates an interrupt, which causes the ADuC7060 to place the data on the output port, bit-by-bit as shown in Figure 3. When all the data has been clocked-out, the chip select is deasserted, and the ADuC7060 reenters deep sleep mode.
On the receiving side, the ADF7020 generates an interrupt when a matching sync word is received (Port INT/LOCK goes high for nine clock cycles).
This informs the ADuC7060 processor to prepare for the reception of a package. Each bit that is received from the package causes an interrupt in the ADuC7060. In the interrupt service routine (ISR), the bit stream is read and stored in a buffer. When all the bytes in the package have been received, a flag is set to indicate that a new package has been received. The main loop can now ensure the validity of the package by the checksum. A correct and complete package can be processed. In this case, this information is sent via the UART to the PC for display. The same ISR handles both the sending and receiving of data to/from the ADF7020 transceiver, as shown in Figure 4.
Figure 3. Data I/O Timing
Figure 4. Interrupt Service Routines for Handling Rx and Tx Data