Файлы проектирования и интеграции
- Bill of Materials
- Gerber Files
- PADS Files
- Assembly Drawing
Буква "Z" в наименовании компонента указывает на соответствие требованиям RoHS. Отмеченные платы нужны для оценки данной схемы
- EVAL-CN0198-SDPZ ($219.00) 5 V Regulator Supplies High Transient Current for Dynamic Power Controlled DAC
- EVAL-SDP-CB1Z ($99.00) Eval Control Board
ПО (код на С и/или FPGA) для связи с цифровым интерфейсом компонента.
Особенности и преимущества
- Quad 16-bit 4mA to 20mA and voltage output DAC
- Dynamic power control
- External 5V regulator
Области применения и технологии
- Контрольно-измерительные приборы
- Промышленная автоматика
Материалы по теме
Функции и преимущества схемы
The circuit shown in Figure 1 provides a unique power saving solution for a digital-to-analog converter (DAC)-based, 4 mA to 20 mA output circuit. To provide sufficient headroom for typical resistive loads between 10 Ω and 1000 Ω, traditional 4 mA to 20 mA output driver stages must operate on at least 20 V (plus some additional headroom) to provide a sufficient voltage to drive high value resistive loads. For low value resistive loads, however, the fixed value, high voltage supply results in significant internal power dissipation that can affect DAC accuracy and require additional heat sinking.
The AD5755 quad 16-bit DAC has four independent high efficiency, internal dc-to-dc converters that drive the four output stages at a dynamically adjusted boost voltage based on sensing the actual output voltage of the 4 mA to 20 mA driver. The boost circuit maintains several volts of headroom on the output stage, regardless of the load resistance, thereby reducing the maximum internal power dissipation by a factor of approximately 4× for a 24 mA output current into a 10 Ω load.
The internal dc-to-dc converters require an external 5 V supply and can draw significant currents when the DAC outputs full-scale slew. A high efficiency external dc-to-dc converter circuit based on the ADP2300 is driven from the 15 V and supplies this voltage. The ADP2300 has excellent transient response to large current steps up to 800 mA and ensures proper operation of the boost converters as well as eliminating the need for a separate 5 V supply.
The entire circuit operates on ±15 V supplies that allow the DAC to provide voltage outputs that cover the industrial signal level range of up to ±10 V in addition to the 4 mA to 20 mA outputs. This combination of parts is a low cost, power efficient solution that minimizes the number of external components required and that ensures 16-bit performance for varying load conditions.
This circuit enhances the slew rate control and dynamic power control features of the AD5755 to create a more complete and robust DAC solution. By implementing a simple step-down dc-to-dc converter using the ADP2300, the circuit can provide higher than normal supply currents that are required when slewing the AD5755 outputs.
The AD5755 behaves like any standard DAC converting digital data to analog current (for example, 0 mA to 20 mA, 4 mA to 24 mA, or 0 mA to 24 mA) or voltage outputs (0 V to 5 V, 0 V to 10 V, ±5 V, or ±10 V). The AD5755 operates with an extended AVSS power supply range to −26.4 V, and an AVDD range to +33.0 V.
Power Dissipation Control
In standard, current controlled module or actuator designs, the load resistor value can range from typically 50 Ω to 750 Ω, but it can be as low as 10 Ω or as high as 1 kΩ. The 4 mA to 20 mA output driver stage must operate on a supply voltage that provides sufficient headroom for the full range of the load resistor values. For example, when driving 24 mA into a 1 kΩ load, a supply voltage of greater than 27 V is required, assuming a 3 V headroom is needed. In this case, the internal package power dissipation due to the output driver is 3 V × 24 mA = 72 mW. However, when driving a 10 Ω load with the same 27 V supply voltage, the internal power dissipation of the driver is approximately 27 V × 24 mA = 648 mW. For a quad DAC, this is greater than 2.5 W.
The AD5755 circuitry senses the output voltage and dynamically regulates the boost supply voltage to meet supply voltage requirements plus a sufficient amount of headroom. For 24 mA output into 10 Ω, the boost voltage of 7.4 V results in an internal power dissipation of only 7.4 V × 24 mA = 178 mW. This represents nearly a 4× reduction in power vs. the unregulated case.
A separate boost supply voltage is generated for each of the four DAC outputs by four independent dc-to-dc converters operating on a 5 V input.
The AD5755 contains four independent, on-board dc-to-dc converters. They provide dynamic control of the VBOOST_X supply voltage for each individual channel. Figure 2 shows the discrete components needed for the dc-to-dc circuitry, and the following sections describe the operation of this circuitry.
It is recommended to place a 10 Ω, 100 nF low-pass RC filter after CDCDC. This consumes a small amount of power; however, it reduces the amount of ripple on the VBOOST_X supply. The suggested component values for LDCDC, CDCDC, and DDCDC are given in Table 1.
|LDCDC||XAL4040-103|| 10 μH
DC-to-DC Converter Operation
The on-board dc-to-dc converters use a constant frequency, peak current mode control scheme to step up an AVCC input of 4.5 V to 5.5 V to drive the AD5755 output channel. These are designed to operate in discontinuous conduction mode (DCM) with a duty cycle of <90% typical.
Discontinuous conduction mode refers to a mode of operation where the inductor current goes to zero for an appreciable percentage of the switching cycle. The dc-to-dc converters are nonsynchronous; that is, they require an external Schottky diode.
DC-to-DC Converter Output Voltage
When a channel current output is enabled, the converter regulates the VBOOST_X supply to 7.4 V (±5%) or (IOUT × RLOAD + Headroom), whichever is greater. The value of the headroom voltage is approximately 3 V. In the voltage output mode with the output disabled, the converter regulates the VBOOST_X supply to +15 V (±5%). In current output mode with the output disabled, the converter regulates the VBOOST_X supply to 7.4 V (±5%).
Within a channel, the VOUT_X and IOUT_X stages share a common VBOOST_X supply so that the outputs of the IOUT_X and VOUT_X stages can be tied together.
DC-to-DC Converter Settling Time
When in current output mode, the settling time for a step greater than approximately 1 V (IOUT × RLOAD) is dominated by the settling time of the dc-to-dc converter. The exception to this is when the required voltage at the IOUT_X pin plus the compliance voltage is below 7.4 V (±5%). The settling time for smaller loads is faster. The settling time for current steps less than 24 mA is also faster.
DC-to-DC Converter VMAX Functionality
The maximum VBOOST_X voltage is set in the dc-to-dc control register. On reaching this maximum voltage, the dc-to-dc converter is disabled, and the VBOOST_X voltage is allowed to decay by approximately 0.4 V. After the VBOOST_X voltage has decayed, the dc-to-dc converter is reenabled, and the voltage ramps up again to VMAX, if still required.
As seen in Figure 3, the DC-DCx bit in the status register asserts when the AD5755 is ramping to the VMAX value and deasserts when the voltage is decaying to VMAX − 0.4 V.
AVCC Supply Static Current Requirements
The dc-to-dc converter is designed to supply a VBOOST_X voltage of VBOOST = IOUT × RLOAD + Headroom
This means that, for a fixed load and output voltage, the dc-to-dc converter output current can be calculated by
IOUT is the output current from IOUT_X in amps.
ηVBOOST is the efficiency at VBOOST_X as a fraction.
AVCC Supply Slewing Current Requirements
The AICC current requirement while slewing is greater than in static operation because the output power increases to charge the output capacitance of the dc-to-dc converter. If not enough AICC current is provided, the AVCC voltage drops. Due to this AVCC drop, the AICC current required to slew increases further.
This means that the voltage at AVCC drops further, and the VBOOST_X voltage, and thus the output voltage, may never reach its intended value. Because this AVCC voltage is common to all channels, this may also affect other channels.
ADP2300 AVCC Supply
The ADP2300 and several discrete components are used to create a simple 5 V rail that meets the supply current demands of the AD5755 as previously described. The output voltage is set externally by a resistive voltage divider from the output voltage to the FB pin, as show in Figure 4.
Test Data and Results
All test data was gathered using the EVAL-AD5755SDZ, EVAL-SDP-CB1Z, and ADP2300-EVALZ boards. The integral nonlinearity (INL), differential nonlinearity (DNL), and total unadjusted error (TUE) of the system using the ADP2300 circuit is shown in Figure 5, Figure 6, and Figure 7, respectively. The AD5755 boost regulators were active for all the measurements.
Complete documentation for the system can be found in the CN0198 Design Support package.
Оценивание характеристик и тестирование схем
This circuit uses the EVAL-AD5755SDZ circuit board and the EVAL-SDP-CB1Z System Demonstration Platform (SDP) evaluation board. The two boards have 120-pin mating connectors, allowing for the quick setup and evaluation of the performance of the circuit.
The EVAL-AD5755SDZ circuit board contains the circuit to be evaluated, and the SDP evaluation board is used with the AD5755 Evaluation Software to capture data.
The following equipment is needed:
- A PC with a USB port and Windows® XP, Windows Vista® (32-bit), or Windows 7 (32-bit)
- The EVAL-AD5755SDZ circuit board
- The EVAL-SDP-CB1Z SDP evaluation board
- The ADP2300-EVALZ evaluation board
- The AD5755 Evaluation Software
- A power supply: ±15 V
- A digital multimeter (that is, Agilent 34401A)
- A GPIB-to-USB cable (only required for capturing analog data from the DAC and transferring it to the PC).
Load the evaluation software by placing the AD5755 Evaluation Software CD into the PC. Using My Computer, locate the drive that contains the evaluation software CD and open the Readme file. Follow the instructions contained in the Readme file for installing and using the evaluation software.
Functional Block Diagram
Figure 8 shows the test setup block diagram, and the EVAL-CN0198-SDPZ-SCH-RevX.pdf file has the circuit schematics. This file is contained in the CN0198-DesignSupport Package.
Connect the 120-pin connector on the EVAL-AD5755SDZ to the CON A connector on the EVAL-SDP-CB1Z. Used nylon hardware to firmly secure the two boards, using the holes provided at the ends of the 120-pin connectors.
With power to the supply off, do the following:
- Connect a ±15 V power supply to J5 terminal block on the EVAL-AD5755SDZ.
- Connect a 15 V power supply to the inputs of the ADP2300-EVALZ.
- Connect the output pins to the J6 connector of the EVAL-AD5755SDZ.
- Connect a ±15 V power supply to the J5 connector on the EVAL-AD5755SDZ.
- Connect the USB cable supplied with the SDP board to the USB port on the PC. Note: Do not connect the USB cable to the mini-USB connector on the SDP board at this time.
Apply power to the ADP2300-EVALZ and the EVAL-AD5755SDZ supplies.
Connect the USB cable from the PC to the mini-USB connector on the SDP board and launch the evaluation software.
Once USB communications are established, the SDP board can be used to send and receive data from the EVAL-AD5755SDZ.
Information regarding the EVAL-SDP-CB1Z can be found in the SDP User Guide.
Information and details regarding test setup and how to use the evaluation software for data capture can be found in the CN-0198 User Guide.
|ADP2300||Несинхронный понижающий импульсный стабилизатор 1.2 A/20 В, 700 кГц||
|AD5755||Четырехканальный, 16-разрядный ЦАП с выходом тока 4-20 мА и напряжения, последовательным входом и динамическим управлением энергопотреблением||