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Demonstration Circuit 1938A features the LT3072 dual, low noise, 2.5A programmable output, low dropout linear regulator. The input voltages VIN1 and VIN2 are independent and can range from 0.8V to 3.45V. Each channel has jumpers to set a three-bit code that determines output voltages VOUT1 and VOUT2 at pre-programmed levels with a range from 0.6V to 2.5V and a maximum output current of 2.5A. DC1938A requires a single external BIAS voltage that is higher than VIN1 and VIN2, between 2.375V and 5.25V and is at least 1.2V higher than the highest output voltage.

Each output is decoupled by a 1µF + 2.2µF + 6.8µF capacitor network and each input is decoupled with a 22µF capacitor. The internal reference of each channel is bypassed with a 0.1µF capacitor to reduce output noise and program the soft-start. 1500µF aluminum electrolytic capacitors and 220µF tantalum polymer capacitors hold up VIN1 and VIN2 but the aluminum electrolytic capacitors are cabling dependent and are not required on customer circuits. The BIAS voltage is bypassed at each channel’s BIAS pin with a 2.2µF capacitor and there is a single terminal for the BIAS input.

The positions of the VOUT1 and VOUT2 ENABLE jumpers either pull up the EN1 and EN2 pins to the BIAS voltage by a 100k resistor, short EN1 and EN2 to ground or float EN1 and EN2 so they can be driven directly by a signal applied to the EN1 and EN2 terminals. Each channel has a terminal for PWRGD that is pulled up to BIAS by a 51kΩ resistor. Resistors program a 3A output current limit and a 333mV/A output current monitoring voltage that is available at the IMON/LIM terminals. The TEMP terminal allows monitoring of die temperature.

VOIC allows automatic control of a pre-regulation voltage and the VOIC pins are bypassed with 1nF capacitors. MARGA1 and MARGA2 terminals for margining allow an optional external voltage to program an adjustment to each channel’s output voltage.

Banana jacks minimize voltage drops on VIN and VOUT connections. Each channel’s SENSE pin terminates at a 10µF capacitor near the VOUT banana jacks. The PCB design minimizes parasitic SENSE to GND and SENSE to OUT trace capacitance. VO1+, VO1-, VO2+ and VO2- terminals Kelvin-connect to the 10µF VOUT capacitors and are the optimal place to observe output voltage regulation and load transient response. Each output has a 560Ω pre-load so the minimum load requirement is met over the VOUT programming range.

DC1938A has placeholders identified on the schematic as optional (Opt) components that make it convenient to add capacitance, add filtering, parallel references or use the VOIC function – check the schematic for placeholder locations.

The LT3072 is well suited to microprocessor systems and instrumentation applications with stringent performance requirements for output noise and load transient response. Systems with high efficiency requirements will benefit from the low dropout of the LT3072. DC1938A features the LT3072 in a thermally enhanced 36-lead 4mm × 7mm QFN package. The LT3072 data sheet must be read in conjunction with this demo manual to properly use or modify demo circuit DC1938A.

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