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The AD5422 16-bit digital-to-analog converter (DAC) is software configurable and provides all the necessary current and voltage outputs.

The AD5700-1, the industry’s lowest power and smallest footprint HART-compliant IC modem, is used in conjunction with the AD5422 to form a complete HART-compatible 4 mA to 20 mA solution. The AD5700-1 includes a precision internal oscillator that provides additional space savings, especially in channel-to-channel isolated applications.

PLC/DCS solutions must be isolated from the local system controller to protect against ground loops and to ensure robustness against external events. Traditional solutions use discrete ICs for both power and digital isolation. When multichannel isolation is needed, the cost and space of providing discrete power solutions becomes a big disadvantage. Solutions based on optoisolators typically have reasonable output regulation but require additional external components, thereby increasing board area. Power modules are often bulky and can provide poor output regulation. The circuit in Figure 1 uses the ADuM347x family of isolators and power regulation circuitry along with associated feedback isolation. External transformers are used to transfer power across the isolation barrier.

The ADuM3482 provides the UART signal isolation for the AD5700-1.

The ADP2441, 36 V step-down dc-to-dc regulator, accepts an industrial standard 24 V supply, with wide tolerance on the input voltage. It steps this down to 5 V to power all controller side circuitry. The circuit also includes standard external protection on the 24 V supply terminals, as well as protection against dc overvoltage of +36 V down to −28 V.

¹ HART is a registered trademark of the HART Communication Foundation.

The automatic gain control (AGC) circuit is useful in multiple applications such as amplitude stabilization of a synthesizer, controlling output power in a transmitter, or optimizing dynamic range in a receiver. The circuit shown in Figure 1 uses the ADL6010 detector, along with the HMC985A voltage variable attenuator (VVA) and the HMC635 RF amplifier, to provide automatic gain control over a wide range of input frequencies (20 GHz to 37.5 GHz) and amplitude. Circuit performance, as measured by the AGC figures of merit described in this circuit note, are very good between 20 GHz and 30 GHz. The overall gain of the circuit falls off above 30 GHz. However, improvements can be made over narrow bands by using matching techniques not explored in this circuit note.

The AGC circuit has applications in microwave instrumentation and radar-based measurement systems.

The circuit shown in Figure 1 accurately measures return loss in a wireless transmitter from 1 GHz to 28 GHz without any need for system calibration.

The design is implemented on a single circuit board using a nonreflective RF switch; a microwave RF detector; and a 12-bit, precision analog-to-digital converter (ADC). To evaluate the circuit over the widest possible frequency range, a dual-port directional coupler with SMA connectors was used instead of a narrow-band, surface-mount directional coupler.

The circuit measures return loss of up to 20 dB over an input power range of 25 dB (return losses in excess of 20 dB can be measured over a smaller input power range).

A unique feature of the circuit is that it calculates return loss using a simple ratio of the digitized voltages from the RF detector, thereby eliminating the need for system calibration.

Figure 1. Voltage Standing Wave Ratio (VSWR) Evaluation Board Measurement Setup (All Connections and Decoupling Not Shown)

The circuit shown in Figure 1 is an RF power measurement circuit that accurately measures the power from an RF signal source within a frequency range of 9 kHz to 6 GHz, and has a nominal input power range of 45 dBm (−30 dBm to +15 dBm).

This circuit constitutes a complete rms RF power meter in a tiny form factor that can be powered entirely from a 5 V USB power supply. The measurement signal chain consists of an rms responding RF power detector and a 12-bit, precision analog-to-digital converter (ADC). These devices are powered by a CMOS linear regulator which generates 3.3 V from the 5 V USB supply.

A simple calibration routine can be performed at multiple frequencies to compensate for any frequency response variation of the circuit. Calibration data is stored in a lookup table, which is referenced during the RF power measurement.

This circuit shown in Figure 1 provides a complete solution that replaces a classical high voltage mechanical potentiometer with a push-button controlled digital potentiometer.

The circuit allows a low voltage digital potentiometer to control a high voltage source up to 20 V from batteries or other sources through simple push-button switches, offering ease of use and optimum power efficiency. The AD5116 digital potentiometer provides 64 wiper positions with an end-to-end resistor tolerance error of ±8%, making it suitable for wide range of adjustment.

In addition, the AD5116 contains an EEPROM that can manually save the wiper position to its desirable position through a push-button. This feature is useful in applications requiring a default position on power-up.

Figure 1. Direct Conversion Transmitter (Simplified Schematic: All Connections and Decoupling Not Shown)

A multichannel DDS virtually eliminates temperature and timing issues between channels compared to synchronizing multiple single channel devices for the same application. For instance, multichannel DDS outputs, though independent, share the same system clock edges in the chip. Consequently, the system clock edges across multiple chips would not track as well over temperature and power supply deviations compared to an integrated multichannel DDS. As a result, a multichannel DDS is better suited for producing a closer to ideal phase coherent frequency transition at the summed output.

Figure 1. Setup for Phase Coherent FSK Modulator (Simplified Schematic: All Connections and Decoupling Not Shown)

The measurement result is provided as serial data at the output of a 12-bit ADC (AD7466). A simple 4-point system calibration at ambient temperature is performed in the digital domain.

The interface between the RF detector and the ADC is straightforward, consisting of two signal scaling resistors and no active components. In addition, the ADL5902 internal 2.3 V reference voltage provides the supply and reference voltage for the micropower ADC. The AD7466 has no pipeline delay and is operated as a read-only SAR ADC.

The overall circuit achieves temperature stability of approximately ±0.5 dB.

Data is shown for the two devices operating over a −40°C to +85°C temperature range.

Figure 1. Software-Calibrated RF Power Measurement System

Low noise, low dropout regulators (LDOs) ensure that the power management scheme has no adverse impact on phase noise and EVM. This combination of components represents industry leading direct conversion transmitter performance over a frequency range of 500 MHz to 4.4 GHz.

This circuit is a complete implementation of the analog portion of a broadband direct conversion transmitter (analog baseband in, RF out). RF frequencies from 500 MHz to 4.4 GHz are supported through the use of a PLL with a broadband integrated voltage controlled oscillator (VCO). Harmonic filtering of the LO from the PLL ensures excellent quadrature accuracy.

Low noise LDOs ensure that the power management scheme has no adverse impact on phase noise and EVM. This combination of components represents industry-leading direct conversion transmitter performance over a frequency range of 500 MHz to 4.4 GHz

The circuit, shown in Figure 1, is a narrow, band-pass receiver front end based on the ADL5565 ultralow noise differential amplifier driver and the AD9642 14-bit, 250 MSPS analog-to-digital converter (ADC).

The third-order, Butterworth antialiasing filter is optimized based on the performance and interface requirements of the amplifier and ADC. The total insertion loss due to the filter network and other components is only 5.8 dB.

The overall circuit has a bandwidth of 18 MHz with a pass-band flatness of 3 dB. The signal-to-noise ratio (SNR) and spurious-free dynamic range (SFDR) measured with a 127 MHz analog input are 71.7 dBFS and 92 dBc, respectively. The sampling frequency is 205 MSPS, thereby positioning the IF input signal in the second Nyquist zone between 102.5 MHz and 205 MHz.

The combination of the ADRF6702 IQ modulator and the AD9122 16-bit dual 1.2 GSPS TxDAC has the dynamic range necessary for a modern high level QAM or OFDM based wireless transmitter as shown in Figure 1. The dynamic range of this circuit is good enough to enable both ZIF (zero IF/baseband) and CIF (complex IF up to 200 MHz to 300 MHz). The AD9122 has the option of up to 8× interpolation, as well as a 32-bit NCO for very fine IF frequency selectivity.

Overall performance of a transmitter is highly dependent on the dynamic range of the components directly in the signal chain. In a mixed-signal transmitter using a DAC and IQ modulator, the noise floor and distortion characteristics of these components define the overall dynamic range of the signal chain. However, the noise floor of the DAC can also be degraded by sample clock jitter, and the IQ modulator performance is dependent on the noise and spur characteristics of its local oscillator (LO). Using high performance components for sample clock and LO generation is, therefore, key to a high performance transmitter.

In addition, generating these signals physically close to the DAC and modulator on the PCB and using a single external reference can make the design much simpler. Generating the sample clock and LO (LO is very often a multi-GHz signal) separately and at some distance from the DAC and IQ modulator requires great care in the PCB layout. Subtle layout errors can cause coupling to and from these critical signals and degrade overall signal chain performance.

The signal chain performance is also heavily dependent on the DAC/ IQ modulator interface filter. For optimal performance, this passive filter should be designed after careful analysis of the required system specifications.

The ADRF6702 includes an on-board fractional PLL for LO generation so that a low frequency reference (typically less than 100 MHz) is all that is necessary to synthesize the IQ modulator LO. Using the PLL in the AD9516 clock generator allows a single reference to generate both the DAC sample clock and the PLL reference for the ADRF6702.

Figure 1. AD9122, ADRF6702, and AD9516 Used in a High Dynamic Range Transmitter

The third-order Butterworth antialiasing filter is optimized based on the performance and interface requirements of the amplifier and ADC. The total insertion loss due to the filter network and other components is only 1.8 dB.

The overall circuit has a bandwidth of 152 MHz with a pass band flatness of 1 dB. The SNR and SFDR measured with a 120 MHz analog input are 72.6 dBFS and 82.2 dBc, respectively.

Figure 1. 16-Bit, 250 MSPS Wideband Receiver Front End (Simplified Schematic: All Connections and Decoupling Not Shown) Gains, Losses, and Signal Levels Measured Values at 10 MHz

This circuit provides a simple and flexible interface between the AD9122 dual high speed TxDAC digital-to-analog converter and the ADL5375-05 broadband I/Q modulator. Because the DAC outputs and ADL5375-05 I/Q modulator inputs share a common bias level of 0.5 V, there is no need for any active or passive level shifting circuitry. The dc coupled interface facilitates I/Q modulator local oscillator (LO) leakage compensation by the DAC.

The 1.2 GSPS AD9122 DAC sampling rate and the wide bandwidth of the ADL5375-05 modulator I and Q inputs ensure that both zero-IF (ZIF) or complex-IF (CIF) architectures can be supported. In addition to filtering Nyquist images, the baseband filter provides excellent rejection of both differential-mode and common-mode DAC spurs.

The third-order Butterworth antialiasing filter is optimized based on the performance and interface requirements of the amplifier and ADC. The total insertion loss due to the filter network, transformer, and other resistive components is only 1.2 dB.

The overall circuit has a bandwidth of 290 MHz with a pass-band flatness of 1 dB. The SNR and SFDR measured with a 140 MHz analog input are 64.1 dBFS and 70.4 dBc, respectively.

The AD9467 is a buffered input 16-bit, 200 MSPS or 250 MSPS ADC with SNR performance of approximately 75.5 dBFS and SFDR performance between 95 dBFS and 98 dBFS. The ADL5565 differential amplifier is suitable for driving IF sampling ADCs because of its high input bandwidth, low distortion, and high output linearity.

This circuit note describes a systematic procedure for designing the interface circuit and the antialiasing filter that maintains high performance and ensures minimal signal loss. A resonant approach is used to design a maximally flat Butterworth fourth-order band-pass filter with a center frequency of 200 MHz.

Figure 1. Resonant Filter Design for Narrow Band High IF Applications Using the ADL5565 Differential Amplifier and the AD9467 ADC

Figure 1. Single Channel of Quad IF Receiver Front End (Simplified Schematic: All Connections and Decoupling Not Shown) Gains, Losses, and Signal Levels Measured Values at 10 MHz

This circuit is a frequency selective, radio frequency (RF) detector that offers 90 dB of detection range from 35 MHz to 4.4 GHz. Unlike a standalone detector that does not discriminate between signals in the frequency spectrum, this circuit has the ability to focus on a narrow band of frequencies, providing enhanced performance over the specified range. The detector circuit is rms responding and stable vs. temperature and frequency, making it an attractive solution for applications that require precise frequency, selective RF power measurement. The circuit also demonstrates strong immunity to unwanted blockers. Figure 1 shows a simplified schematic of the circuit.

Figure 1. Frequency Selective RF Detector (Simplified Schematic; All Connections and Decoupling Not Shown)

The circuit block diagram shown in Figure 1 is a low phase noise translation loop synthesizer (also known as an offset loop). This circuit translates the lower 100 MHz reference frequency of the

Figure 1. PLC/DCS Channel-to-Channel Isolated Temperature Input

(Simplified Schematic: All Connections and Decoupling Not Shown)

The circuit shown in Figure 1 precisely converts a 400 MHz to 6 GHz RF input signal to its corresponding digital magnitude and digital phase. The signal chain achieves 0° to 360° of phase measurement with 1° of accuracy at 900 MHz. The circuit uses a high performance quadrature demodulator, a dual differential amplifier, and a dual differential 16-bit, 1 MSPS successive approximation analog-to-digital converter (SAR ADC).

Figure 1. Simplified Receiver Subsystem for Magnitude and Phase Measurements(All Connections and Decoupling Not Shown)

Because they are sampled data devices, low power DDS devices must be followed by a suitable anti-imaging filter to remove spectral images. However, the maximum current output is approximately 4 mA into a recommended 200 Ω load; therefore, an optimum low power, low distortion op amp buffer at the DDS output provides a low impedance drive source for a high quality 50 Ω filter.

The combination of the DDS, output buffer, and seventh-order elliptic low pass filter provides high quality spectral performance.

The bandwidth of this filter can be dynamically adjusted as the bandwidth of the input signal changes. This ensures that the available dynamic range of the ADC that this circuit drives is fully used.

The core of the circuit is an integrated IQ demodulator with fractional-N PLL and VCO. With just one (variable) reference frequency, the PLL/VCO can provide and a local oscillator (LO) between 750 MHz and 1150 MHz. Precise quadrature balance and low output dc offsets ensure that there is minimal degradation of the error vector magnitude (EVM).

The interfaces between all of the components in this circuit are fully differential. Where dc coupling is required between stages, the bias levels of the adjacent stages are compatible with each other.

Figure 1. Direct Conversion receiver Simplified Schematic (All Connections and Decoupling Not Shown)

The performance is achieved using an active loop filter with 2.4 MHz bandwidth. This wide bandwidth loop filter is achievable because of the ADF4159 phase-frequency detector (PFD) maximum frequency of 110 MHz; and the AD8065 op amp high gain-bandwidth product of 145 MHz.

The AD8065 op amp used in the active filter can operate on a 24 V supply voltage that allows control of most wideband VCOs having tuning voltages from 0 V to 18 V.

Figure 1. Block Diagram of ADF4159, AD8065 Active Loop Filter, and 11.4 GHz to 12.8 GHz VCO. (Simplified Schematic: All Connections and Decoupling Not Shown)