Ракеты и высокоточные боеприпасы

ADIS16490 - это полнофункциональная инерциальная система, которая включает в себя трехосевой гироскоп и трехосевой акселерометр. Каждый из инерциальных датчиков, входящих в состав ADIS16490, основан на комбинации передовой технологии iMEMS^® и схемы обработки сигнала, оптимизирующей динамические характеристики. При изготовлении продукта каждый датчик подвергается калибровке чувствительности, смещения, взаимной ориентации осей и линейного ускорения (смещение гироскопа). В результате, каждому из датчиков соответствуют собственные формулы динамической компенсации, обеспечивающие точные измерения.

ADIS16490 представляет собой простой и экономически эффективный инструмент для интеграции многоосевых инерциальных измерений с малой погрешностью в промышленные системы, особенно в сравнении со сложностью и размерами инвестиций при использовании дискретных решений. Все необходимые испытания и калибровки проводятся на этапе изготовления продукта, благодаря чему время, затрачиваемое на его интеграцию в систему, значительно сокращается. Жесткое согласование взаимной ориентации осей упрощает проведение юстировки инерциальной системы координат в навигационных системах. Порт SPI и набор внутренних регистров обеспечивает простой интерфейс для сбора данных и конфигурирования устройства.

ADIS16490 имеет такие же габариты посадочного места и систему подключения, как и ADIS16375, ADIS16480, ADIS16485, а также ADIS16488A, что значительно упрощает процедуру модернизации существующих систем. Компонент выпускается в виде модуля с габаритами приблизительно 47 мм × 44 мм × 14 мм и имеет стандартный соединительный интерфейс.

Области применения

• Прецизионные измерительные приборы и стабилизация
• Системы управления, навигации и наведения
• Беспилотные летательные аппараты
• Прецизионные автономные механизмы, робототехника

ADIS16495 - это полнофункциональная инерциальная система, которая включает в себя трехосевой гироскоп и трехосевой акселерометр. Каждый из инерциальных датчиков, входящих в состав ADIS16495, основан на комбинации передовой технологии iMEMS^® и схемы обработки сигнала, оптимизирующей динамические характеристики. При изготовлении продукта каждый датчик подвергается калибровке чувствительности, смещения, взаимной ориентации осей и линейного ускорения (смещение гироскопа). В результате, каждому из датчиков соответствуют собственные формулы динамической компенсации, обеспечивающие точные измерения.

ADIS16495 представляет собой простой и экономически эффективный инструмент для интеграции многоосевых инерциальных измерений с малой погрешностью в промышленные системы, особенно в сравнении со сложностью и размерами инвестиций при использовании дискретных решений. Все необходимые испытания и калибровки проводятся на этапе изготовления продукта, благодаря чему время, затрачиваемое на его интеграцию в систему, значительно сокращается. Жесткое согласование взаимной ориентации осей упрощает проведение юстировки инерциальной системы координат в навигационных системах. Порт SPI и набор внутренних регистров обеспечивают простой интерфейс для сбора данных и конфигурирования устройства.

ADIS16495 имеет такие же посадочное место и тип соединительного разъема, как у ADIS16375, ADIS16480, ADIS16485, ADIS16488A и ADIS16490, что позволяет легко модернизировать существующие системы. ADIS16495 выпускается в алюминиевом корпус с габаритами приблизительно 47 мм × 44 мм × 14 мм и имеет стандартный соединительный интерфейс.

Области применения

• Прецизионные измерения, стабилизация
• Управление, наведение и навигация
• Авиационная электронная радиоаппаратура, беспилотные летательные аппараты
• Прецизионные автономные механизмы, робототехника

ADIS16497 - это полнофункциональная инерциальная система, которая включает в себя трехосевой гироскоп и трехосевой акселерометр. Каждый из инерциальных датчиков, входящих в состав ADIS16497, основан на комбинации передовой технологии iMEMS^® и схемы обработки сигнала, оптимизирующей динамические характеристики. При изготовлении продукта каждый датчик подвергается калибровке чувствительности, смещения, взаимной ориентации осей и линейного ускорения (смещение гироскопа). В результате, каждому из датчиков соответствуют собственные формулы динамической компенсации, обеспечивающие точные измерения.

ADIS16497 представляет собой простой и экономически эффективный инструмент для интеграции многоосевых инерциальных измерений с малой погрешностью в промышленные системы, особенно в сравнении со сложностью и размерами инвестиций при использовании дискретных решений. Все необходимые испытания и калибровки проводятся на этапе изготовления продукта, благодаря чему время, затрачиваемое на его интеграцию в систему, значительно сокращается. Жесткое согласование взаимной ориентации осей упрощает проведение юстировки инерциальной системы координат в навигационных системах. Порт SPI и набор внутренних регистров обеспечивают простой интерфейс для сбора данных и конфигурирования устройства.

ADIS16497 имеет такие же посадочное место и тип соединительного разъема, как у ADIS16375, ADIS16480, ADIS16485, ADIS16488A и ADIS16490, что позволяет легко модернизировать существующие системы. ADIS16497 выпускается в алюминиевом корпус с габаритами приблизительно 47 мм × 44 мм × 14 мм и имеет стандартный соединительный интерфейс.

Области применения

• Прецизионные измерения, стабилизация
• Управление, наведение и навигация
• Авиационная электронная радиоаппаратура, беспилотные летательные аппараты
• Прецизионные автономные механизмы, робототехника

ADIS16470 - это полнофункциональная инерциальная система, которая включает в себя трехосевой гироскоп и трехосевой акселерометр. Каждый из инерциальных датчиков, входящих в состав ADIS16470, основан на комбинации передовой технологии iMEMS^® и схемы обработки сигнала, оптимизирующей динамические характеристики. При изготовлении продукта каждый датчик подвергается калибровке чувствительности, смещения, взаимной ориентации осей и линейного ускорения (смещение гироскопа). В результате, каждому из датчиков соответствуют собственные формулы динамической компенсации, обеспечивающие точные измерения.

ADIS16470 представляет собой простой и экономически эффективный инструмент для интеграции многоосевых инерциальных измерений с малой погрешностью в промышленные системы, особенно в сравнении со сложностью и размерами инвестиций при использовании дискретных решений. Все необходимые испытания и калибровки проводятся на этапе изготовления продукта, благодаря чему время, затрачиваемое на его интеграцию в систему, значительно сокращается. Жесткое согласование взаимной ориентации осей упрощает проведение юстировки инерциальной системы координат в навигационных системах. Порт SPI и набор внутренних регистров обеспечивают простой интерфейс для сбора данных и конфигурирования устройства.

ADIS16470 выпускается в 44-контактном корпусе BGA, имеющем габариты приблизительно 11 мм × 15 мм × 11 мм.

Области применения

• Навигация, стабилизация и измерения
• Беспилотные и автономные средства передвижения
• Интеллектуальные сельскохозяйственные и строительные механизмы
• Промышленная/заводская автоматика, робототехника
• Виртуальная/дополненная реальность
• Интернет мобильных вещей

The ADAR1000 is a 4-channel, X and Ku frequency band, beamforming core chip for phased arrays. This device operates in half-duplex between receive and transmit modes. In receive mode, input signals pass through four receive channels and are combined in a common RF_IO pin. In transmit mode, the RF_IO input signal is split and passes through the four transmit channels. In both modes, the ADAR1000 provides a ≥31 dB gain adjustment range and a full 360° phase adjustment range in the radio frequency (RF) path, with better than 6-bit resolution (less than ≤0.5 dB and 2.8°, respectively).

Control of all the on-chip registers is through a simple 4-wire serial port interface (SPI). In addition, two address pins allow SPI control of up to four devices on the same serial lines. Additionally, dedicated transmit and receive load pins provide synchronization of all core chips in the same array, and a single pin controls fast switching between the transmit and receive modes.

The ADAR1000 is available in a compact, 88-terminal, 7 mm × 7 mm, LGA package and is specified from −40°C to +85°C.

Applications

• Phased Array Radar
• Satellite Communications Systems

The ADRV9009 is a highly integrated, radio frequency (RF) agile transceiver offering dual transmitters and receivers, integrated synthesizers, and digital signal processing functions. The IC delivers a versatile combination of the high performance and low power consumption demanded by 3G and 4G macro cell TDD base station applications.

The receive path consists of two independent, wide bandwidth, direct conversion receivers with state-of-the-art dynamic range. The part also supports a wide-bandwidth time-shared observation path receiver for use in TDD applications. The complete receive subsystem includes automatic and manual attenuation control, dc offset correction, quadrature error correction (QEC), and digital filtering, thus eliminating the need for these functions in the digital baseband. Several auxiliary functions such as ADCs, DACs, and GPIOs for PA and RF-front-end control are also integrated.

In addition to the autonomous AGC, it also has flexible external gain control modes, allowing significant flexibility in setting system level gain dynamically.

The received signals are digitized with a set of four high dynamic range continuous-time sigma-delta ADCs which provide inherent anti-aliasing. The combination of the direct conversion architecture, which does not suffer from out-of-band image mixing, and the lack of aliasing relaxes the requirements of the RF filters as compared to traditional IF receivers.

The transmitters use an innovative direct conversion modulator that achieves high modulation accuracy with exceptionally low noise.

The observation path consists of a wide bandwidth direct-conversion receiver with state-of-the-art dynamic range.

The transmitters use an innovative direct conversion modulator that achieves high modulation accuracy with exceptionally low noise.

The fully integrated phase-locked loop (PLL) provides high performance, low power fractional-N RF frequency synthesis for the transmitter and receiver signal paths. An additional synthesizer generates the clocks needed for the converters, digital circuits, and serial interface. Special precautions have been taken to provide the isolation demanded in high performance base station applications. All voltage controlled oscillators (VCOs) and loop filter components are integrated.

The high-speed JESD204B interface supports up to 12.288 Gbps lane rates resulting in two lanes per transmitter, and a single lane per receiver in the widest bandwidth mode. The interface also supports interleaved mode for lower bandwidths thus reducing the total number of high speed data interface lanes to one. Both fixed and floating-point data formats are supported. The floating-point format allows internal AGC to be invisible to the demodulator device. Details of the format are available in the device User Guide.

The core of the ADRV9009 can be powered directly from 1.3 V and 1.8 V regulators and is controlled via a standard 4 wire serial port. Comprehensive power-down modes are included to minimize power consumption in normal use. The ADRV9009 is packaged in a 12mm × 12 mm, 196-ball chip scale ball grid array (CSP_BGA).

Applications

• 3G/4G/5G TDD macro cell base stations
• TDD active antenna systems
• Massive MIMO
• Phased Array Radar
• Electronic Warfare
• Military Communications
• Portable test equipment

Посмотрите вебинар "Моделирование работы радиочастотных трансиверов от Analog Devices с помощью MATLAB и simRF".

AD9361 – это высококачественный, обладающий высокой степенью интеграции, конфигурируемый приемопередатчик (RF Agile Transceiver™), разработанный для использования в базовых станциях сетей 3G и 4G. Возможности программирования и способность работы в широком диапазоне частот делают его идеальным решением для создания различных приемопередающих радиоустройств. Компонент содержит аналоговый радиочастотный тракт, настраиваемый каскад аналого-цифровой обработки сигнала в полосе модулирующих частот и интегрированные синтезаторы частоты, упрощая проектирование систем благодаря конфигурируемому интерфейсу с процессором. Гетеродин приёмника AD9361 работает в диапазоне частот от 70 МГц до 6.0 ГГц, а гетеродин передатчика – от 47 МГц до 6,0 ГГц, перекрывая большинство лицензируемых и нелицензируемых диапазонов. Ширина полосы каналов составляет от менее 200 кГц до 56 МГц.

Два независимых приемника прямого преобразования имеют превосходные коэффициент шума и линейность. Каждая подсистема приема включает в себя блоки независимой автоматической регулировки усиления (AGC), коррекции смещения постоянной составляющей, коррекции квадратурных ошибок и цифровой фильтрации, тем самым устраняя необходимость реализации этих функций во внешнем коммуникационном процессоре. В AD9361 также имеются гибко конфигурируемые режимы ручного усиления, которыми можно управлять извне. Имеющиеся в каждом канале два аналого-цифровых преобразователя (ADC) с высоким динамическим диапазоном оцифровывают принятые синфазные (I) и квадратурные (Q) составляющие сигнала. Оцифрованные сигналы проходят через конфигурируемые прореживающие фильтры и КИХ-фильтры 128-порядка, после чего преобразуется в 12-разрядные выходные сигналы на соответствующей частоте дискретизации.

Передатчики построены на архитектуре прямого преобразования, которая обеспечивает высокую точность модуляции при сверхнизком шуме. Такая реализация передатчика позволяет получить лучшую в своем классе величину вектора ошибок <−40 дБ, что обеспечивает значительный запас на уровне системы при выборе внешнего усилителя мощности. Встроенный модуль контроля мощности передатчика может использоваться в качестве детектора мощности и позволяет выполнять очень точные измерения мощности передачи.

Полностью интегрированные синтезаторы с фазовой автоподстройкой частоты (ФАПЧ) с дробным коэффициентом деления и низким энергопотреблением генерируют частоты для всех каналов приема и передачи. В AD9361 обеспечивается уровень изоляции каналов, требуемый для систем дуплексной передачи с частотным разделением (FDD). Также в устройство интегрированы все компоненты ГУН и петлевых фильтров. Ядро AD9361 может питаться непосредственно от стабилизатора 1,3 В. Управление микросхемой осуществляется с помощью стандартного 4-проводного последовательного порта и четырех управляющих линий ввода/вывода. Для минимизации энергопотребления в процессе работы предусмотрены различные режимы пониженного потребления энергии. AD9361 выпускается в корпусе CSP_BGA со 144 шариковыми контактами, имеющем размеры 10 мм × 10 мм.

Области применения

• Системы связи "точка-точка"
• Базовые станции фемто-/пико-/микросот
• Радиосистемы общего назначения

The AD9213 is a single 12-bit, 10.25 GSPS, RF analog-to-digital converter (ADC) with a 6.5 GHz input bandwidth. The AD9213 has been optimized to support high dynamic range frequency and time domain applications requiring wide instantaneous bandwidth and low code error rates (CER). The AD9213 features a 16-lane JESD204B interface to support its maximum bandwidth capability.

The AD9213 achieves industry leading dynamic range and linearity performance while consuming only 5 W. Based on an interleaved pipeline architecture, the AD9213 features a proprietary calibration and randomization technique that suppresses interleaving spurious artifacts into its noise floor. The excellent linearity performance of the AD9213 under low level signal conditions is preserved by a combination of on-chip dithering and calibration resulting in excellent windowed spurious free performance (<−95 dBFS) over a wide range of input signal conditions.

Applications requiring less instantaneous bandwidth can benefit from the on-chip digital signal processing (DSP) capability of the AD9213 that reduces the output data rate along with the number of JESD204b lanes required to support it. The DSP path includes a digital downconverter (DDC) with a 48-bit, numerically controlled oscillator (NCO) followed by an I and Q digital decimator stage allowing for selectable decimation rates that are factors of two or three. For fast frequency hopping applications, the AD9213 NCO supports up to 16-profile settings with separate trigger input allowing for wide surveillance frequency coverage but at a reduced JESD204B lane count.

The AD9213 also supports sample accurate multichip synchronization that also includes synchronization of the NCOs. The AD9213 will be offered in a 192 flip-chip ball grid array (FcBGA) package. The AD9213 is specified over a junction temperature range of −10°C to +115°C.

Applications

• Spectrum analyzers
• Military communications
• Radar
• High performance digital storage oscilloscopes
• Active jamming/antijamming
• Electronic surveillance and countermeasures
• DPD observation path

The LVDT is a highly reliable sensor because the magnetic core can move without friction and does not touch the inside of the tube. Therefore, LVDTs are suitable for flight control feedback systems, position feedback in servomechanisms, automated measurement in machine tools, and many other industrial and scientific electromechanical applications where long term reliability is important.

This circuit uses the AD598 LVDT signal conditioner that contains a sine wave oscillator and a power amplifier to generate the excitation signals that drive the primary side of the LVDT. The AD598 also converts the secondary output into a dc voltage. The AD8615 rail-to-rail amplifier buffers the output of the AD598 and drives a low power 12-bit successive approximation analog-to-digital converter (ADC). The system has a dynamic range of 82 dB and a system bandwidth of 250 Hz, making it ideal for precision industrial position and gauging applications.

The signal conditioning circuitry of the system consumes only 15 mA of current from the ±15 V supply and 3 mA from the +5 V supply, making this ideal for remote applications. The circuit can operate a remote LVDT from up to 300 feet away, and the output can drive up to 1000 feet.

This circuit note discusses basic LVDT theory of operation and the design steps used to optimize the circuit shown in Figure 1 for a chosen bandwidth, including noise analysis and component selection considerations.

The circuit shown in Figure 1 is a complete linear variable differential transformer (LVDT) signal conditioning circuit that can accurately measure linear position or linear displacement from a mechanical reference. Synchronous demodulation in the analog domain is used to extract the position information and provides immunity to external noise. A 24-bit, Σ-Δ analog-to-digital converter (ADC) digitizes the position output for high accuracy.

LVDTs utilize electromagnetic coupling between the movable core and the coil assembly. This contactless (and hence frictionless) operation is a primary reason for why they are widely used in aerospace, process controls, robotics, nuclear, chemical plants, hydraulics, power turbines, and other applications where operating environments can be hostile and long life and high reliability are required.

The entire circuit, including the LVDT excitation signal, consumes only 10 mW of power. The circuit excitation frequency and output data rates are SPI programmable. The system has a programmable bandwidth vs. dynamic range trade-off. It supports bandwidths of over 1 kHz, and at a bandwidth of 20 Hz, the circuit has a dynamic range of 100 dB, making it ideal for precision industrial position and gauging applications.

The third-order Butterworth antialiasing filter is optimized based on the performance and interface requirements of the amplifier and ADC. The total insertion loss due to the filter network, transformer, and other resistive components is only 1.2 dB.

The overall circuit has a bandwidth of 290 MHz with a pass-band flatness of 1 dB. The SNR and SFDR measured with a 140 MHz analog input are 64.1 dBFS and 70.4 dBc, respectively.

A multichannel DDS virtually eliminates temperature and timing issues between channels compared to synchronizing multiple single channel devices for the same application. For instance, multichannel DDS outputs, though independent, share the same system clock edges in the chip. Consequently, the system clock edges across multiple chips would not track as well over temperature and power supply deviations compared to an integrated multichannel DDS. As a result, a multichannel DDS is better suited for producing a closer to ideal phase coherent frequency transition at the summed output.

Figure 1. Setup for Phase Coherent FSK Modulator (Simplified Schematic: All Connections and Decoupling Not Shown)

The performance is achieved using an active loop filter with 2.4 MHz bandwidth. This wide bandwidth loop filter is achievable because of the ADF4159 phase-frequency detector (PFD) maximum frequency of 110 MHz; and the AD8065 op amp high gain-bandwidth product of 145 MHz.

The AD8065 op amp used in the active filter can operate on a 24 V supply voltage that allows control of most wideband VCOs having tuning voltages from 0 V to 18 V.

Figure 1. Block Diagram of ADF4159, AD8065 Active Loop Filter, and 11.4 GHz to 12.8 GHz VCO. (Simplified Schematic: All Connections and Decoupling Not Shown)

This flexible arrangement allows the ADA4930-1 differential driver to operate on a single 3.3 V supply, while the AD9265 16-bit 125 MSPS ADC operates on a 1.8 V supply, thereby minimizing the total circuit power dissipation.

In broadband applications, the frequency range of interest often includes dc. To maximize the dynamic range of a differential input ADC, typical input signals can be relatively large, thereby requiring the differential driver to operate at lower gain settings. Under these conditions, the input common-mode voltage of the differential driver must stay within the specified range.

Independent control of the input and output common-mode voltage of differential amplifiers is often required in direct coupled single-supply applications such as processing demodulator outputs with high input common-mode voltages, x-ray applications with a dc component added to a differential component, and other places where the differential driver must handle low value input common-mode voltages. Low input common-mode voltage applications can include either single-ended or differential inputs, with zero, bipolar, or negative inputs.

The circuit, shown in Figure 1, is a narrow, band-pass receiver front end based on the ADL5565 ultralow noise differential amplifier driver and the AD9642 14-bit, 250 MSPS analog-to-digital converter (ADC).

The third-order, Butterworth antialiasing filter is optimized based on the performance and interface requirements of the amplifier and ADC. The total insertion loss due to the filter network and other components is only 5.8 dB.

The overall circuit has a bandwidth of 18 MHz with a pass-band flatness of 3 dB. The signal-to-noise ratio (SNR) and spurious-free dynamic range (SFDR) measured with a 127 MHz analog input are 71.7 dBFS and 92 dBc, respectively. The sampling frequency is 205 MSPS, thereby positioning the IF input signal in the second Nyquist zone between 102.5 MHz and 205 MHz.

The AD9467 is a buffered input 16-bit, 200 MSPS or 250 MSPS ADC with SNR performance of approximately 75.5 dBFS and SFDR performance between 95 dBFS and 98 dBFS. The ADL5565 differential amplifier is suitable for driving IF sampling ADCs because of its high input bandwidth, low distortion, and high output linearity.

This circuit note describes a systematic procedure for designing the interface circuit and the antialiasing filter that maintains high performance and ensures minimal signal loss. A resonant approach is used to design a maximally flat Butterworth fourth-order band-pass filter with a center frequency of 200 MHz.

Figure 1. Resonant Filter Design for Narrow Band High IF Applications Using the ADL5565 Differential Amplifier and the AD9467 ADC

Figure 1. Single Channel of Quad IF Receiver Front End (Simplified Schematic: All Connections and Decoupling Not Shown) Gains, Losses, and Signal Levels Measured Values at 10 MHz

The 3-axis accelerometer controls the high-side switch by monitoring the acceleration in three axes and closes or opens the switch depending on the presence or absence of motion.

The ADXL362 is an ultralow power, 3-axis accelerometer that consumes less than 100 nA in wake-up mode. Unlike accelerometers that use power duty cycling to achieve low power consumption, the ADXL362 does not alias input signals by under sampling; it samples continuously at all data rates. There is also an on-chip, 12-bit temperature sensor accurate to ±0.5°.

The ADXL362 provides 12-bit output resolution and has three operating ranges, ±2 g, ±4 g, and ±8 g. It is specified over a minimum temperature range of −40°C to +85°C. For applications where a noise level less than 480 μg/√Hz is desired, either of its two lower noise modes (down to 120 μg/√Hz) can be selected at a minimal increase in supply current.

The ADP195 is a high-side load switch designed for operation between 1.1 V and 3.6 V and is protected against reverse current flow from output to input. The device contains a low on-resistance, P-channel MOSFET that supports over 1.1 A of continuous load current and minimizes power losses.

The ADXL362 is a three-axis, ultralow power acceleration measurement system capable of measuring dynamic acceleration (resulting from motion or shock) as well as static acceleration (that is, gravity).

The moving component of the sensor is a polysilicon, surface micromachined structure, also referred to as a beam, built on top of a silicon wafer. Polysilicon springs suspend the structure over the surface of the wafer and provide a resistance against acceleration forces.

Deflection of the structure is measured using differential capacitors. Each capacitor consists of independent fixed plates and plates attached to the moving mass. Any acceleration deflects the beam and unbalances the differential capacitor, resulting in a sensor output whose amplitude is proportional to acceleration. Phase-sensitive demodulation is used to determine the magnitude and polarity of the acceleration.

Modes of Operation

The three basic modes of operation for the ADXL362 are standby, measurement, and wake-up.

• Placing the ADXL362 in standby mode suspends measurement and reduces current consumption to 10 nA. Any pending data or interrupts are preserved; however, no new information is processed. The ADXL362 powers up in standby mode with all sensor functions turned off.

• Measurement mode is the normal operating mode of the ADXL362. In this mode, acceleration data is continuously read, and the accelerometer consumes less than 3 μA across its entire range of output data rates of up to 400 Hz using a 2.0 V supply. All described features are available while operating in this mode. The ability to continuously output data from the minimum 12.5 Hz to the maximum 400 Hz data rate while still delivering less than 3 μA of current consumption is what defines the ADXL362. as an ultralow power accelerometer. Under sampling and aliasing do not occur with the ADXL362. because it continuously samples the full bandwidth of its sensor at all data rates.

• Wake-up mode is ideal for simple detection of the presence or absence of motion at extremely low power consumption (270 nA at a 2.0 V supply voltage). Wake-up mode is useful particularly for implementation of a motion-activated on/off switch, allowing the rest of the system to be powered down until activity is detected. Wake-up mode reduces current consumption to a very low level by measuring acceleration only 6 times a second to determine whether motion is present. In wake-up mode, all accelerometer features are available with the exception of the activity timer. All registers are accessible, and real-time data is available from the part.

The CN0274 evaluation software uses the wake-up mode of the ADXL362. That is, the ADXL362 is asleep until it detects motion at which point it enters measurement mode.

Power/Noise Tradeoff

The ADXL362 offers a few options for decreasing noise at the expense of only a small increase in current consumption.

The noise performance of the ADXL362 in normal operation, typically 7 LSB rms at 100 Hz bandwidth, is adequate for most applications, depending upon bandwidth and the desired resolution. For cases where lower noise is needed, the ADXL362 provides two lower noise, operating modes that trade reduced noise for somewhat higher supply current.

Table 1. ADXL362 Noise vs. Supply Current

Mode	Noise  (µg/√Hz Typical)	Current Consumption (µA Typical)
Normal Operation	380	2.7
Low Noise	280	4.5
Ultralow Noise	175	15

Table 1 shows the supply current values and noise densities obtained for normal operation and the two lower noise modes, at a typical 3.3 V supply.

The CN0274 evaluation software uses the normal operation noise mode of the ADXL362.

Motion Detection

The ADXL362 has built-in logic that detects activity (acceleration above a certain threshold) and inactivity (lack of acceleration above a certain threshold).

Detection of an activity or inactivity event is indicated in the status register and can also be configured to generate an interrupt. In addition, the activity status of the device, that is, whether it is moving or stationary, is indicated by the AWAKE bit.

Activity and inactivity detection can be used when the accelerometer is in either measurement mode or wake-up mode.

Activity Detection

An activity event is detected when acceleration stays above a specified threshold for a user-specified time period. The two activity detection events are absolute and referenced.

• When using absolute activity detection, acceleration samples are compared to a user set threshold to determine whether motion is present. For example, if a threshold of 0.5 g is set, and the acceleration on any axis is 1 g for longer than the user defined activity time, the activity status is asserted. In many applications, it is advantageous for activity detection to be based not on an absolute threshold but on a deviation from a reference point or orientation. This is particularly useful because it removes the effect on activity detection of the static 1 g imposed by gravity. When an accelerometer is stationary, its output can reach 1 g, even when it is not moving. In absolute activity, if the threshold is set to less than 1 g, activity is immediately detected in this case.
• In the referenced activity detection, activity is detected when acceleration samples are at least a user set amount above an internally defined reference, for the user defined amount of time. The reference is calculated when activity detection is engaged, and the first sample obtained is used as a reference point. Activity is only detected when the acceleration has deviated sufficiently from this initial orientation. The referenced configuration results in a very sensitive activity detection that detects even the most subtle motion events.

The CN0274 evaluation software uses the referenced mode of operation when searching for activity.

Inactivity Detection

An inactivity event is detected when acceleration remains below a specified threshold for a specified time. The two inactivity detection events are absolute and referenced.

• In absolute inactivity detection, acceleration samples are compared to a user set threshold for the user set time to determine the absence of motion.
• In referenced inactivity detection, acceleration samples are compared to a user specified reference for a user defined amount of time. When the part first enters the awake state, the first sample is used as a reference point, and the threshold is applied around it. If the acceleration stays inside the threshold, the part enters the asleep state. If an acceleration value moves outside the threshold, this point is then used as a new reference, and the thresholds are reapplied to this new point.

The CN0274 evaluation software uses the referenced mode of operation when searching for inactivity.

Linking Activity and Inactivity Detection

The activity and inactivity detection functions can be used concurrently, and processed manually by a host processor, or they can be configured to interact in several ways:

• In default mode, activity and inactivity detection are both enabled, and all interrupts must be serviced by a host processor; that is, a processor must read each interrupt before it is cleared and can be used again.
• In linked mode, activity and inactivity detection are linked to each other such that only one of the functions is enabled at any given time. Once activity is detected, the device is assumed moving or awake and stops looking for activity: inactivity is expected as the next event so only inactivity detection operates. When inactivity is detected, the device is assumed stationary or asleep. Activity is now expected as the next event so that only activity detection operates. In this mode, a host processor must service each interrupt before the next is enabled.
• In loop mode, motion detection operates as previously described in linked mode; however, interrupts do not need to be serviced by a host processor. This configuration simplifies the implementation of commonly used motion detection and enhances power savings by reducing the amount of power used in bus communication.
• When enabling autosleep mode in linked mode or loop mode, it causes the device to autonomously enter wake-up mode when inactivity is detected, and reenter measurement mode when activity is detected.

The CN0274 evaluation software uses the autosleep and loop modes to demonstrate the functionality of the ADXL362.

The AWAKE Bit

The AWAKE bit is a status bit that indicates whether the ADXL362 is awake or asleep. The device is awake when it has seen an activity condition, and the device is asleep when it has seen an inactivity condition.

The awake signal can be mapped to the INT1 or INT2 pin and can thus be used as a status output to connect or disconnect power to downstream circuitry based on the awake status of the accelerometer. Used in conjunction with loop mode, this configuration implements a trivial, autonomous motion-activated switch.

If the turn-on time of the downstream circuitry can be tolerated, this motion switch configuration can save significant system-level power by eliminating the standby current consumption of the rest of the application. This standby current can often exceed the full operating current of the ADXL362.

Interrupts

Several of the built-in functions of the ADXL362 can trigger interrupts to alert the host processor of certain status conditions.

Interrupts may be mapped to either (or both) of two designated output pins, INT1 and INT2, by setting the appropriate bits in the INTMAP1 and INTMAP2 registers. All functions can be used simultaneously. If multiple interrupts are mapped to one pin, the OR combination of the interrupts determines the status of the pin.

If no functions are mapped to an interrupt pin, that pin is automatically configured to a high impedance (high-Z) state. The pins are placed in this state upon a reset as well.

When a certain status condition is detected, the pin that condition is mapped to is activated. The configuration of the pin is active high by default, so that when it is activated, the pin goes high. However, this configuration can be switched to active low by setting the INT_LOW pin in the appropriate INTMAP register.

The INT pins may be connected to the interrupt input of a host processor and interrupts responded to with an interrupt routine. Because multiple functions can be mapped to the same pin, the STATUS register can be used to determine which condition caused the interrupt to trigger.

The CN0274 evaluation software configures the ADXL362 such that when activity is detected, the INT1 pin is high, and when inactivity is detected, the INT1 pin is low.

Test Results

All testing was performed using the EVAL-CN0274-SDPZ and the EVAL-SDP-CS1Z. Functionality of the part is demonstrated by setting the activity threshold at 0.5 g, the inactivity threshold at 0.75 g, and the number of inactivity samples at 20. When looking for activity, only one acceleration sample on any axis is required to cross the threshold.

Starting with the circuit oriented so that the battery pack is flat against the table, the printed circuit board (PCB) can be slowly rotated 90° in any direction causing the acceleration to cross the threshold as it approaches perpendicular to the initial orientation.

Figure 2 shows a screen shot of the CN0274 evaluation software showing the ADXL362 first asleep, looking for activity. Then, when Sample 11 crosses the threshold, the ADXL362 enters the awake state and begins looking for inactivity. The thresholds adjust to show the device is now looking for inactivity.

Figure 2. Screen Shot of Evaluation Software Output

For better visibility, the X-axis and Z-axis plots are disabled using the radio buttons above the chart. 

The output of the ADP195, or the interrupt pin itself, was measured using a digital multimeter. When the ADXL362 is awake, the interrupt goes high and drives the EN pin of the ADP195, high, which in turn drives the gate of the MOSFET low, causing the switch to close, connecting any downstream circuitry to the power supply. Conversely, when the ADXL362 is asleep, the interrupt drives the EN pin of the ADP195 low, which in turn drives the gate of the MOSFET high, causing the switch to open.

PCB Layout Considerations In any circuit where accuracy is crucial, it is important to consider the power supply and ground return layout on the board. The PCB should isolate the digital and analog sections as much as possible. The PCB for this system was constructed in a 4-layer stack up with large area ground plane layers and power plane polygons. See the MT-031 Tutorial for more discussion on layout and grounding, and the MT-101 Tutorial for information on decoupling techniques.

Decouple the power supply to the ADXL362 with 1 μF and 0.1 μF capacitors to properly suppress noise and reduce ripple. Place the capacitors as close to the device as possible. Ceramic capacitors are advised for all high frequency decoupling.

Power supply lines should have as large a trace width as possible to provide low impedance paths and reduce glitch effects on the supply line. Shield clocks and other fast switching digital signals from other parts of the board by digital ground. A photo of the PCB is shown in Figure 3.

A complete design support package for this circuit note can be found at www.analog.com/CN0274-DesignSupport.

Figure 3. Photo of EVAL-CN0274-SDPZ PCB

The third-order Butterworth antialiasing filter is optimized based on the performance and interface requirements of the amplifier and ADC. The total insertion loss due to the filter network and other components is only 1.8 dB.

The overall circuit has a bandwidth of 152 MHz with a pass band flatness of 1 dB. The SNR and SFDR measured with a 120 MHz analog input are 72.6 dBFS and 82.2 dBc, respectively.

Figure 1. 16-Bit, 250 MSPS Wideband Receiver Front End (Simplified Schematic: All Connections and Decoupling Not Shown) Gains, Losses, and Signal Levels Measured Values at 10 MHz