Design a PLL Filter When Only the Zero Resistor and Capacitor Are Adjustable

Introduction

As described in the references, a standard procedure can be used to determine the values of R0, C0, and CP for a second-order loop filter in a phase-locked loop (PLL). It uses open-loop bandwidth (ω0) and phase margin (ϕM) as design parameters, and can be extended to third-order loop filters to determine R2 and C2 (Figure 1). The procedure solves for CP directly and subsequently derives the remaining values.

In some cases, CP, R2, and C2 may be fixed-value components integrated within the PLL, leaving only R0 and C0 available for controlling the loop response. This nullifies the aforementioned procedure because CP cannot be adjusted. This article proposes an alternative procedure that can be used when the value of CP is fixed, and addresses limitations imposed by the inability to control the value of CP.

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Figure 1. Typical second-order and third-order passive loop filters.

Assumptions

This loop filter design method relies on two assumptions that are typically used in third-order passive filter designs that extend a second-order loop filter design to third-order by compensating for the presence of R2 and C2 through adjustment of R0 and C0.

  1. The pole frequency resulting from R2 and C2 should be at least an order of magnitude greater than ω0 (the desired open-loop unity-gain bandwidth); specifically f0 ≤ 0.1/(2πR2C2), where f0 = ω0/(2π).
  2. The load of the series combination of R2 and C2 on the R0-C0-CP network should be negligible.

Transfer Function of a Second-Order Loop Filter

A second-order loop filter has two time constants (T1 and T2) associated with its components:

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The loop filter’s transfer function, in terms of T1, T2, and CP, is important because it plays a significant role in the overall response of the PLL:

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PLL System Function

The small signal model shown in Figure 2 provides the means for formulating the PLL response and a template for analyzing phase variation at the output resulting from a phase disturbance at the input. Note that the voltage-controlled oscillator (VCO), being a frequency source, behaves like an ideal phase integrator, so its gain (KV) has a 1/s factor (the Laplace transform equivalent of integration). Hence, the small signal model of a PLL has frequency dependence (s = σ + jω).

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Figure 2. Small signal PLL model.

The closed-loop transfer function (HCL) for a PLL is defined as θOUTIN. The open-loop transfer function (HOL), defined as θFBIN, is related to the closed-loop transfer function. It is instructive to express HCL in terms of HOL because the open-loop transfer function contains clues about closed-loop stability:

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K represents the combined gains of the phase-frequency detector (PFD), charge pump, and VCO—that is, K = KDKV, where KD is the charge pump current in amperes and KV is the VCO gain in Hz/V. HOL, HCL, and HLF are all functions of s. The negative sign in Equation 4 shows the phase inversion implied by the negative feedback to the summing node in Figure 2. Defining HOL as in Equation 4 leads to subtraction in the denominator of Figure 5, which provides an intuitive explanation of closed-loop stability.

Inspection of Equation 5 reveals a potential loop stability problem. Given that HOL is a function of complex frequency (s = σ + jω), it necessarily has frequency dependent magnitude and phase components. Therefore, if HOL simultaneously exhibits unity gain and zero phase shift (or any integer multiple of 2π radians) for any particular value of s, the denominator of HCL becomes zero, the closed-loop gain becomes undefined, and the system becomes completely unstable. This implies that stability is governed by the frequency-dependent magnitude and phase characteristics of HOL. In fact, at the frequency for which the magnitude of HOL is unity, the phase of HOL must stay far enough from zero (or any integer multiple of 2π) to avoid a zero denominator in Equation 5.

The frequency, ω0, at which the magnitude of HOL is unity, holds great importance. The phase of HOL at ω0 defines the phase margin of the system ϕM. Both ω0 and ϕM can be derived from HOL.

Defining R0 and C0 in Terms of ω0 and ϕM

Using the design parameters ω0 and ϕM to determine the values of R0 and C0 requires expressions containing those four variables and other constant terms. Start with Equation 4, because it defines HOL. This includes HLF, which includes R0 and C0 via T1 and T2. Since HOL has magnitude and phase, it stands to reason that ω0 and ϕM can be incorporated as well.

Substituting Equation 3 into Equation 4 and rearranging terms yields Equation 6, which presents HOL in terms of T1 and T2 along with constants K, N, and CP:

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Evaluation at s = jω, yields the frequency response of HOL:

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The (jω)2 term in the denominator simplifies to –ω2:

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The magnitude and phase of HOL are:

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Keep in mind that T1 and T2 are shorthand expressions for algebraic combinations of R0, C0, and CP. Evaluating Equation 9 at ω = ω0 and setting |HOL| = 1 defines the unity gain frequency, ω0, as the frequency at which the magnitude of HOL is unity.

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Similarly, evaluating Equation 10 at ω = ω0 and setting ∠HOL = ϕM defines the phase margin, ϕM, as the phase of HOL at frequency ω0 (the unity gain frequency).

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It is a trivial matter to expand Equation 11 and Equation 12 by substituting Equation 1 for T2 and Equation 2 for T1, which brings R0 and C0 into the equations. Hence, we have succeeded in relating ω0 and ϕM to the variables R0 and C0 along with constants K, N, and CP.

Simultaneously solving the resulting equations for R0 and C0 is no trivial task. The symbolic processor available in MathCad® can solve the two simultaneous equations, but arccos must be substituted for arctan. This transformation enables the symbolic processor to solve for R0 and C0, yielding the following solution sets (R0A, C0A; R0B, C0B; R0C, C0C; and R0D, C0D). See the Appendix for details on transforming Equation 12 to use the arccos function.

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This result is problematic because the goal was to solve for R0 and C0 given ω0 and ϕM, but this indicates four possible R0, C0 pairs instead of a unique R0, C0 pair. However, closer inspection of the four results leads to a single solution set as follows.

Note that in the context of modeling a PLL, all of the variables in the above equations possess positive values, including cos(ϕM) because ϕM is constrained to values between 0 and π/2. As a result, C0A and R0B are clearly negative quantities. Therefore, solution sets R0A, C0A and R0B, C0B are immediately ruled out because negative component values are not acceptable. The R0C, C0C and R0D, C0D results require further analysis, however.

Note that the four equations involving R0C, C0C and R0D, C0D possess the common factor:

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Closer inspection reveals that Expression 13 has the form a2 – (2ac)cos(β) + c2. Equating this with the arbitrary quantity, b2, yields:

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Equation 14, the Law of Cosines, relates a, b, and c as the lengths of the three sides of a triangle with β being the interior angle of the vertex opposite side b. Since b2 is the square of the length of one side of a triangle, it must be a positive quantity, which implies the right side of Equation 14 must also be positive. Thus, Expression 13 must be a positive quantity, which means the denominator of R0D is positive. The numerator of R0D is also positive, therefore R0D must be negative, which rules out the R0D, C0D solution set. This leaves only the R0C, C0C pair as a contender for the simultaneous solution of Equation 11 and Equation 12.

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Constraints on R0 and C0

Although Equation 15 and Equation 16 are contenders for the simultaneous solution of Equation 11 and Equation 12, they are only valid if they result in positive values for both R0 and C0. Close inspection of R0 shows it to be positive—its numerator is positive, because the range of cos2(x) is 0 to 1—and its denominator is the same as Expression 13, which was previously shown to be positive. The numerator of C0 is also the same as Expression 13, so C0 is positive as long as its denominator satisfies the following condition:

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This is depicted graphically in Figure 3, in which the left and right sides of Equation 17 are each equated to y (blue and green curves) with the horizontal axis sharing ω0 and ϕM. The intersection of the two curves marks the boundary condition for ω0 and ϕM. The condition under which Equation 17 is true appears as the red arc. The portion of the horizontal axis beneath the red arc defines the range of ϕM and ω0 that ensures C0 is positive. Note the point on the horizontal axis directly below the intersection of the blue and green curves establishes ϕM_MAX, the maximum value of ϕM to ensure C0 is positive.

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Equation 18 requires that CP02 be less than K in order to satisfy the constraints of the arccos function for ϕM_MAX between 0 and π/2. This establishes ω0_MAX, the upper limit on ω0 to ensure C0 is positive.

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Figure 3. Constraint on C0 denominator.

Compensating for R2 and C2 (Third-Order Loop Filter)

In the case of a third-order loop filter, components R2 and C2 introduce additional phase shift, Δϕ, relative to the second-order loop filter:

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To deal with this excess phase shift, subtract it from the desired value of ϕM:

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Applying ϕM_NEW to Equation 15 and Equation 16 results in different values for R0 and C0 than for the second-order solution, with the new values compensating for the excess phase shift introduced by R2 and C2. The presence of R2 and C2 also affects ϕM_MAX, the maximum allowable value of ϕM. The new maximum value of ϕMM_MAX_NEW) is

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Conclusion

This article demonstrates using open-loop unity-gain bandwidth (ω0) and phase margin (ϕM) as design parameters for second-order or third-order loop filters when only components R0 and C0 are adjustable. Simulation of a PLL with a second-order loop filter using R0 and C0 yields an exact match to the theoretical frequency response of HOL and the resulting phase margin, thereby validating the equations. The parameters ω0 and ϕM have upper bounds for a second-order loop filter per Equation 19 and Equation 18, respectively.

The procedure for determining R0 and C0 assumed a second-order loop filter, but is extendible to third-order loop filter designs by adjusting the desired phase margin (ϕM) to a new value (ϕM_NEW) per Equation 21, yielding a new upper bound (ϕM_MAX_NEW) per Equation 22.

Although simulations using a second-order loop filter validated Equation 15 and Equation 16, validating the equations that extend the design procedure to third-order loop filter designs requires a redefinition of the loop filter response, HLF(s), to include R2 and C2 as follows:

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The incorporation of this form of HLF into the HOL and HCL equations enables simulations of third-order loop filter designs using R0 and C0. Such simulations reveal the calculated values of R0 and C0 deviate from the theoretical frequency response and phase margin associated with HOL for a PLL when using a third-order loop filter. This is predominantly due to the effect of R2 and C2 on HOL in a third-order loop filter.

Recall that the formulas for R0 and C0 assume a second-order loop filter, but R2 and C2 do not exist in a second-order filter, so including them as part of the loop filter constitutes a source of error in spite of adjusting R0 and C0 to compensate for the phase shift introduced by R2 and C2. Even in the presence of this error, however, simulation indicates that using the adjusted values of R0 and C0, but limiting the choice of ω0 to a maximum of ¼ of the value dictated by Equation 19 yields acceptable results. In fact, the simulated open-loop bandwidth and phase margin results deviate only slightly from the design parameters (ω0 and ϕM) for a PLL using a third-order loop filter.

Simulation Results

The following is the result of running four simulations of a PLL with a third-order loop filter. The simulations all have the following fixed-loop filter components and PLL parameters:

CP = 1.5 nF

R2 = 165 kΩ

C2 = 337 pF

KD = 30 µA

KV = 3072 (25 ppm/V at 122.88 MHz)

N = 100

Simulation 1 and Simulation 2 use ω0 = 100 Hz, which is near the calculated upper limit of 124.8 Hz (ω0_MAX). As such, Simulation 1 and Simulation 2 deviate from the design parameter values (ω0 and ϕM) by nearly 10%. On the other hand, Simulation 3 and Simulation 4 use ω0 = 35 Hz, which is approximately ¼ the upper limit. As expected, Simulation 3 and Simulation 4 hold much closer to the design parameters (ω0 and ϕM), yielding an error of only about 1%.

Table 1 summarizes the simulation results and also includes the calculated values of R0, C0, ω0_MAX, and ϕM_MAX for the given design parameters, ω0 and ϕM. Note that for the purpose of comparison it would be preferable for both Simulation 1 and Simulation 3 to use ϕM = 80°, but Simulation 1 must satisfy the constraint imposed by Equation 22 of ϕM < 48° (hence the choice of 42°).

Table 1: Simulation Summary

Simulation 1 Simulation 2 Simulation 3 Simulation 4
Parameter ω0 ϕM ω0 ϕM ω0 ϕM ω0 ϕM
Design 100 Hz 42° 100 Hz 30° 35 Hz 80° 35 Hz 30°
Simulation 93.1 Hz 38.7° 92.5 Hz 27.1° 34.9 Hz 79.0° 34.7 Hz 29.3°
R0 969.6 kΩ 1118 kΩ 240.1 kΩ 139.9 kΩ
C0 14.85 nF 3.670 nF 225.5 nF 21.24 nF
ω0_MAX 124.8 Hz 124.8 Hz 124.8 Hz 124.8 Hz
ϕM_MAX 48.0° 48.0° 84.8° 84.8°

Figure 4 and Figure 5 show the open- and closed-loop response for each simulation.

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Figure 4. Open-loop gain and phase.

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Figure 5. Closed-loop gain.

Appendix—Converting the Discontinuous Arctan Function to the Continuous Arccos Function

Equation 10 demonstrates that the angle ϕ is the difference between angle θ2 and angle θ1, where θ2 = arctan(ωT2) and θ1 = arctan(ωT1). Furthermore, ωT2 is expressible as x/1 and ωT1 as y/1:

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This implies the geometric relationship shown in Figure 6, with θ1 and θ2 defined by the triangles of Figure 6 (b) and (a), respectively. Figure 6 (c) combines these two triangles to show ϕ as the difference between θ1 and θ2.

The Law of Cosines relates an interior angle (θ) of a triangle to the lengths of the three sides of the triangle (a, b, and c) as follows:

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Applying the Law of Cosines to angle ϕ in Figure 6 (c) yields:

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Figure 6. Geometric representation of Equation 10.

Solving for ϕ:

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But, x/1 = ωT2 and y/1 = ωT1, allowing ϕ to be expressed in terms of T1 and T2.

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Ссылки

Brennan, Paul V. Phase-Locked Loops: Principles and Practice. McGraw-Hill, 1996.

Keese, William O. AN-1001, National Semiconductor Application Note, An Analysis and Performance Evaluation of a Passive Filter Design Technique for Charge Pump Phase-Locked Loops. May 1996.

MT-086: Fundamentals of Phase Locked Loops (PLLs).

PLLs/PLLs with Integrated VCOs.

Об авторах

Ken Gentile

Ken Gentile

Ken Gentile joined Analog Devices in 1998 as a system design engineer with the Clock and Signal Synthesis product line in Greensboro, NC, where he specializes in direct digital synthesis, analog filter design, and writing GUI-based engineering tools in MATLAB. Ken holds 10 patents. He has published 14 articles in various industry trade journals and over a dozen ADI application notes, as well as having presented at ADI’s annual General Technical Conference (GTC) in 2001, 2005, and 2006. He graduated with honors in 1996 with a B.S.E.E. from North Carolina State University. In his spare time, Ken enjoys reading, mathematical puzzles, and most anything related to science, engineering, and “backyard” astronomy.