Accelerate Your Test Capability and System Productivity with New MEMS Switches

Abstract

Advanced digital processor ICs require separate DC parametric and high speed digital automatic test equipment (ATE) passes for quality assurance. This creates significant cost and logistical challenges. This article explains how the ADGM1001 SPDT MEMS switch facilitates a one pass single insertion test for both DC parametric and high speed digital tests, reducing test cost and simplifying logistics for digital/RF system on chip (SoC) testing.

Figure 1. Operator mounting load board on tester for testing digital SoC.

ATE Challenges

The semiconductor market is evolving with higher speed and higher density interchip communications for advanced processors such as 5G modem ICs, graphics ICs, and central processing ICs. Assuring quality amidst this increasing complexity and demand for increased throughput is the ultimate challenge for today’s ATE designers. One critical aspect is the increasing number of transmitter (Tx)/receiver (Rx) channels, which require both high speed digital and DC parametric testing. These challenges are driving complexity in semiconductor tests and not addressing them leads to increased test time, increased load board complexity, and reduction in test throughput. In turn, this will drive up operational expenses (OPEX) and reduce productivity in a modern ATE environment.

To solve these ATE challenges, a switch that is operational at DC and high frequencies is needed. ADGM1001 can pass true 0 Hz DC signals and up to 64 Gbps high speed signals. This enables an efficient single test platform (one insertion) that can be configured to test both DC parameters and high speed digital communication standards, such as PCIe Gen 4/5/6, PAM4, and USB 4.

Figure 2. ADGM1001 eye diagram at 32 Gbps (RF1 to RFC with reference trace, pattern used PRBS 215-1).

How Are HSIO Pins Tested?

Testing high speed input output (HSIO) interfaces in a high volume manufacturing environment is a challenge. A common approach to validate an HSIO interface is to implement a high speed loopback test architecture. This incorporates both high speed and DC test paths in one configuration.

To perform high speed loopback testing, generally a pseudorandom bit sequence (PRBS) is transmitted at high speed from the transmitter and received at the receiver end after being looped back on the load board or test board as shown in Figure 3 (left side). At the receiver end, the sequence is analyzed to calculate the bit error rate (BER).

DC parametric tests, such as continuity and leakage tests, are performed on I/O pins to ensure device functionality. To perform these tests, pins need to be connected directly to a DC instrument where a current is forced and a voltage is measured in order to test for failures.

To perform both a high speed loopback test and a DC parametric test on the DUT I/Os, there are a few methods that can be used to test the digital SoC; for example, using MEMS switches or relays, or using two different types of load boards, one for high speed testing and the other for DC testing, which requires two insertions.

Performing high speed testing and DC parametric testing using relays becomes challenging as most relays don’t operate beyond 8 GHz, so users have to compromise on signal speed and test coverage. Moreover, relays are big in size and consume a large PCB area, which impacts the solution size. Reliability is always a concern for relays as they typically only last for 10 million switching cycles, which limits system uptime and load board lifetime.

Figure 3 shows a two insertion test method to perform a high speed loopback test and a DC parametric test. In Figure 3, the left side shows the high speed digital loopback test setup, where the transmitter of the DUT is connected back to the receiver through a coupling capacitor. On the right side of Figure 3 is the DC parametric test setup where DUT pins are directly connected to the ATE tester for parametric tests. Until now, it has not been possible to have both high speed loopback and DC test functionality on the same load board due to component limitations.

Figure 3. Illustration of a two insertion test methodology.

Challenges Associated with Two Test Insertions

  • Management of two sets of hardware: Users must maintain and manage two sets of load boards required for DC and loopback test. This adds significant overhead, particularly when testing a high volume of parts.
  • Higher test time and higher test cost: Two test insertion means every DUT must be tested twice, hence the indexing time during each test will be doubled, which ultimately increases the test cost and impacts the test throughput significantly.
  • Test time optimization: Test times can’t be optimized when two sets of hardware are involved. More cost will be incurred if a part fails the second insertion. The first insertion will have been wasted tester time.
  • More prone to human error: Since every DUT is tested twice, it doubles the risk of human error.
  • Solution set up × 2: The two test insertion approach involves two sets of hardware, which doubles the hardware setup time.
  • Logistics overhead: The two test insertion requires more component moves. It requires moving the components between testers and potentially between test houses, creating planning and logistical challenges.

How ADI’s DC to 34 GHz Switch Technology Solves the Double Insertion Problem with Superior Density

ADI’s 34 GHz MEMS switch technology offers both high speed digital and DC testing capability with superior density in a small 5 mm × 4 mm × 0.9 mm LGA package, as shown in Figure 4. To perform a high speed digital test, high speed signals from a transmitter are passed through the switch and routed back to a receiver, where after decoding, the BER is analyzed. For parametric DC testing, the switch connects the pins to the DC ATE tester where parametric tests such as continuity and leakage tests are performed to ensure device functionality. During parametric DC testing, MEMS switches also provide an option to communicate with ATE at high frequency, which is required in some applications.

Figure 4. ADGM1001 enabling both high speed digital and DC testing (highlighting P channel only).

Figure 5 shows a high speed digital testing solution comparing the use of relays and ADGM1001 MEMS switches. The solution provided by the MEMS switches is nearly 50% smaller than the relay solution as the ADGM1001 comes in a 5 × 4 × 0.9 mm LGA package, which is 20× smaller than a typical relay. The high frequency standards such as PCIe Gen 4/5, PAM4, USB 4, and SerDes drive multiple transmitter and receiver channels, which require intense PCB densification without any layout complication to mitigate channel-to-channel variation. To meet the demand of these evolving high frequency standards, MEMS switches offer intense densification and enhanced functionality in the load board design for digital SoC testing.

Figure 5. Comparing the loopback solution provided by relays vs. the ADGM1001.

Relays are typically large and have limited high frequency performance. They struggle to support higher frequency standards such as PCIe Gen 4/5, PAM4, USB 4, and SerDes with enhanced densification. The majority of the relays don’t operate beyond 8 GHz and their poor insertion loss at high frequencies impacts the signal integrity and limits the test coverage.

An Introduction to ADGM1001

The ADGM1001 SPDT MEMS switch provides class-leading performance from DC to 34 GHz. Due to the ultralow parasitics and wide bandwidth of the technology, the switch has minimal impact on signals up to 64 Gbps and offers minimal channel skew, jitter, and propagation delay enabling high fidelity data transmission. It provides a low insertion loss of 1.5 dB at 34 GHz and low RON of 3 Ω typically. It offers excellent linearity of 69 dBm and can handle high RF power of 33 dBm. It comes in a small 5 mm × 4 mm × 0.95 mm plastic SMD package, with 3.3 V power supply and simple low voltage control interface. All these features make the ADGM1001 an ideal candidate for ATE applications enabling both high speed digital and DC parametric testing capability in a single test insertion, as shown in Figure 4.

Figure 6. ADGM1001 RF performance.
Figure 7. Package type: 5 mm × 4 mm × 0.9 mm, 24-lead LGA package.

The ADGM1001 is easy to use. It can be operated by applying VDD of 3.3 V to Pin 23. However, VDD can operate from 3.0 V to 3.6 V. The switches can then be controlled normally via the logic control interface (Pin 1 to Pin 4) or via the SPI interface. All the required passive components for device functionality are integrated inside the package for ease of use and board space saving. Figure 8 shows the functional block diagram of the ADGM1001.

Figure 8. ADGM1001 functional block diagram.

Benefits of the ADGM1001 in Enabling a Single Insertion Test

  • Superior high speed and DC performance: Achieving wide bandwidth from DC to 34 GHz is the challenge for the industry today. ADGM1001 delivers leading performance from DC to 34 GHz in the areas of critical parameters such as insertion loss, linearity, RF power handling, and RON.
  • Reduction in OPEX:
  • Hardware reduction: A single insertion test requires single test hardware; hence, users don’t need to invest in two sets of hardware and test equipment, enabling a huge reduction in OPEX.
  • Tester uptime: The ADGM1001 offers 100 million cycles providing superior reliability as compared to relays and improves tester uptime, which ultimately reduces OPEX.
  • Improved test throughout: The ADGM1001 enables the use of a single insertion test, reducing the indexing time to half, which improves the test time significantly and provides improved test throughput and better asset utilization.
  • Dense solution and future-proof: The ADGM1001 offers improved densification and enhanced functionality. MEMS switch technology has robust roadmap serving switches that are operational from DC to high frequencies and it’s fully aligned to evolving technologies.
  • Reduction in logistic costs: The single insertion method requires fewer component moves, which reduces logistic costs and eases off planning overload.
  • Fewer component moves: In the single insertion test method, the DUT is tested in single insertion only which reduces the component moves and ultimately reduces the risk of human error.

Conclusion

The ADGM1001 is advancing switch technology from DC to 34 GHz, enabling the combination of high speed digital and DC parametric solutions for SoC testing. Its capabilities enable test time reduction, improvements in board real estate (leading to higher DUT counts and throughput), and increased uptime (improved reliability).

The ADGM1001 is the latest addition to the ADI’s MEMS switch family that continues to advance the needs of high speed SoC testing. ADI’s MEMS switch technology has a robust roadmap serving switching functions from DC to high frequencies to cater to future technology needs. So, stay tuned for future updates on ADI’s MEMS switch technology.

Об авторах

Richard Houlihan

Richard Houlihan

Richard Houlihan has 25 years in the electronic industry, spanning roles from design, product line management, marketing and business unit directorship. He now spearheads marketing and business development for Analog Devices’ leading switch and multiplexer product lines. Richard oversees strategic innovation and product development by leveraging his background in analog front-end architectures and broad market channel experience. He currently holds a degree in electrical engineering from Trinity College Dublin and an M.B.A. from Northeastern University, Boston.

Naveen Dhull

Naveen Dhull

Naveen Dhull received his B.Eng. degree in electronics from the Waterford Institute of Technology, Ireland in 2011. He joined Analog Devices in 2011 as an IC layout engineer and later moved to the Applications Group for switches and multiplexers in 2016. Since 2016, he has been a product application engineer at ADI focusing on RF switches using CMOS and MEMS switch technology.

Padraig Fitzgerald

Padraig Fitzgerald

Padraig Fitzgerald graduated from University of Limerick in 2002 with a bachelor’s degree in electronic engineering. He started at Analog Devices, Limerick, Ireland, as an evaluation engineer working on solid-state switches in 2002 and moved to switch design in 2007. Padraig completed a research master’s at Cork Institute of Technology on the reliability of MEMS switches. He also has a master’s degree in finance and economics from the University of London. He is currently a principal design engineer in the Precision Switch Group and is a product and device designer for the MEMS switch.