------------------------------------------------------------------------
This document describes the usage of the ADV202 Evaluation External
DMA tests. These tests are provided to assist in preliminary system
debug. These tests make use of internal and external DMA facilities
in the ADV202. Successful operation of these tests will confirm that
firmware loading and basic DMA operation is functional.

These test files can be used with ADV202 Engineering Sample versions 2
and 3 (ES2/ES3).
The testname.dat (ASCII Hex) files contain the firmware program to be
loaded to the processor RAM in Host No-Boot mode. The binary versions
of these files are available as testname.sea.

------------------------------------------------------------------------
TEST [1] : ADV202 Evaluation Single DREQ/DACK Read test usage
------------------------------------------------------------------------
Testname: eval_edma_singlerd0_loop
------------------------------------------------------------------------
Description: This test uses the internal processor to generate a data
pattern which can be read using External DMA Channel 0 (DREQ0n and
DACK0n).
It is important for the user to maintain the DACK0n pin high,
until the EDMA interface has been enabled by the Host.
------------------------------------------------------------------------
Procedure for running the test

1) Load program and perform SOFTRESET (production mode) in the standard
   protocol. Maintain DACK0n in high state.

2) Initialize Bus Mode (BUSMODE:Addr 0x8) Register
   Write hex value 0x000A to Direct Address 0x8.
   This sets the Host data width to 32-bit.

3) Initialize Miscellaneous Mode (MMODE:Addr 0x9) Register
   Write hex value 0x0009 to Direct Address 0x9.
   This sets Indirect Address Incrementing and 16-bit Register access
   modes.

4) Initialize External DMA Mode
   Write hex value 0xffff1408 to Direct Address 0xb (Indirect Addr Reg).
   Write hex value 0x0000300A to Direct Address 0xc (Indirect Data Reg).

4) Initialize External Interrupt (EIRQIE:Addr 0x5) Register
   Write hex value 0x00000400 to Direct Address 0x5.
   This enables Software Interrupt 0 (SWIRQ0).

5) Wait for IRQn to be asserted low
   [or poll Software Flag (SWFLAG:Addr 0x7) register for 0xFF04].
   This indicates that initialization is complete.

6) Clear Interrupt Flag (EIRQFLG:Addr 0x6)
   Write hex value 0x00000400 to Direct Address 0x6.
   This will cause the IRQn signal to go to the high (inactive) state.

7) Enable External DMA
   Write hex value 0xffff1408 to Direct Address 0xb (Indirect Addr Reg).
   Write hex value 0x0000300B to Direct Address 0xc (Indirect Data Reg).
   [This will cause DREQ0n to be asserted within 3 CLKIN cycles. DREQ0n
   is set to 6 clk cycles].

8) Host can perform reads with DREQ0n/DACK0n handshake after first
   DREQ0n pulse is generated by ADV202. The ARM processor generates
   a sequential pattern starting from 0x00010203 to 0xfcfdfeff, which
   is transferred to the FIFO with internal DMA in an infinite loop.


------------------------------------------------------------------------
TEST [2] : ADV202 Evaluation JDATA Read test usage
------------------------------------------------------------------------
Testname: eval_edma_jdatard0_loop
------------------------------------------------------------------------
Description: This test uses the internal processor to generate a byte-
stream which can be read through the JDATA port (XGPIO[15:8], DREQ0n,
and DACK0n).
It is important for the user to maintain the HOLD (DACK0n) pin high,
until the JDATA interface has been enabled by the internal processor.
------------------------------------------------------------------------
Procedure for running the test

1) Load program and perform SOFTRESET in the standard manner. Maintain
   HOLD (DACK0n) pin in high state and ignore VALID (DREQ0n) signal.

2) Initialize Miscellaneous Mode (MMODE:Addr 0x9) Register
   Write hex value 0x0009 to Direct Address 0x9.
   This sets Indirect Address Incrementing and 16-bit Register access
   modes.

3) Initialize Bus Mode (BUSMODE:Addr 0x8) Register
   Write hex value 0x0015 to Direct Address 0x8.
   This sets the Host data width to 16-bit and sets XGPIO[15:8] as
   JDATA port.

4) Initialize External Interrupt (EIRQIE:Addr 0x5) Register
   Write hex value 0x0400 to Direct Address 0x5.
   This enables Software Interrupt 0 (SWIRQ0).

5) Wait for IRQn to be asserted low
   [or poll Software Flag (SWFLAG:Addr 0x7) register for 0xFF05].
   This indicates that initialization is complete.

6) Clear Interrupt Flag (EIRQFLG:Addr 0x6)
   Write hex value 0x0400 to Direct Address 0x6.
   This will cause the IRQn signal to go to the high (inactive) state.

7) Host can now initiate JDATA reads by driving HOLD (DACK0n) to the
   low state. VALID (DREQ0n) will go to the high state in the following
   CLKIN cycle and data transfers will begin on XGPIO[15:8]. The data
   pattern is 0x00, 0x01, 0x02, ... 0xFF, 0x00, 0x01, etc.


------------------------------------------------------------------------
TEST [3] : ADV202 Evaluation Single DREQ/DACK Write/Read 2-Channel test usage
------------------------------------------------------------------------
Testname: eval_edma_singlewrrd0_2chn_loop
------------------------------------------------------------------------
Description: This test can be used to verify DREQ/DACK write and read
single transfers to/from the ADV202. It uses External DMA Channel 0
(DREQ0n/DACK0n) for writing and Channel 1 (DREQ1n/DACK1n) for reading.
It is important for the user to maintain the DACK0/DACK1 pins high,
until the EDMA interfaces has been enabled by the Host.
------------------------------------------------------------------------
Procedure for running the test

1) Load program and perform SOFTRESET (production mode) in the standard
   protocol. Maintain DACK0n in high state.

2) Initialize Bus Mode (BUSMODE:Addr 0x8) Register
   Write hex value 0x000A to Direct Address 0x8.
   This sets the Host data width to 32-bit.

3) Initialize Miscellaneous Mode (MMODE:Addr 0x9) Register
   Write hex value 0x0009 to Direct Address 0x9.
   This sets Indirect Address Incrementing and 16-bit Register access
   modes.

4) Initialize External DMA Mode for Channels 0 and 1
   Write hex value 0xffff1408 to Direct Address 0xb (Indirect Addr Reg).
   Write hex value 0x0000300A to Direct Address 0xc (Indirect Data Reg).
   Write hex value 0x0000300C to Direct Address 0xc (Indirect Data Reg).

5) Initialize FIFO Mode Register (FFMODE)
   Write hex value 0xffff1418 to Direct Address 0xb (Indirect Addr Reg).
   Write hex value 0x00000010 to Direct Address 0xc (Indirect Data Reg).
   This sets the Code FIFO (FIFO 0) to input and the Attribute FIFO
   (FIFO 1) to output. The FIFO depths for both FIFOs is set to 256
   words.

6) Initialize External Interrupt (EIRQIE:Addr 0x5) Register
   Write hex value 0x00000400 to Direct Address 0x5.
   This enables Software Interrupt 0 (SWIRQ0).

7) Wait for IRQn to be asserted low
   [or poll Software Flag (SWFLAG:Addr 0x7) register for 0xFF06].
   This indicates that initialization is complete.

8) Clear Interrupt Flag (EIRQFLG:Addr 0x6)
   Write hex value 0x00000400 to Direct Address 0x6.
   This will cause the IRQn signal to go to the high (inactive) state.

9) Enable External DMA for Channels 0 and 1
   Write hex value 0xffff1408 to Direct Address 0xb (Indirect Addr Reg).
   Write hex value 0x0000300B to Direct Address 0xc (Indirect Data Reg).
   Write hex value 0x0000300D to Direct Address 0xc (Indirect Data Reg).
   [This will cause DREQ0n to be asserted within 3 CLKIN cycles. The
    pulse duration is set to 1 CLKIN].

10) Host can perform writes with DREQ0n/DACK0n handshake after first
    DREQ0n pulse is generated by ADV202. After data is written to the
    ADV202, DREQ1n will pulse, indicating that data can be read out.
    This is a loop-back test, so the data read out is the same as the
    data which was written into Channel 0. There is a 1K word buffer,
    so the host may write up to 1K words before doing the first read.
    The test will run continuously in an infinite loop.


------------------------------------------------------------------------
TEST [4] : ADV202 Evaluation JDATA Write/Read test usage
------------------------------------------------------------------------
Testname: eval_edma_jdatawrrd0_loop
------------------------------------------------------------------------
Description: This test can be used to verify JDATA writes and reads to
and from the ADV202. The Host sets up the number of words (number of
bytes X 4) to be written, enables the EDMA/JDATA interface, and begins
writing data. When the programmed number of words is reached, the ADV202
disables the EDMA/JDATA interface, changes the interface direction, and
JDATA can be read from the part after the EDMA/JDATA interface has been
re-enabled by the Host. This continues in an infinite loop.
This assumes a 16-bit Host interface since we are in JDATA mode.
------------------------------------------------------------------------

Procedure for running the test

1) Load program and perform SOFTRESET (production mode) in the standard
   protocol. Maintain DACK0n in high state.

2) Initialize Bus Mode (BUSMODE:Addr 0x8) Register
   Write hex value 0x0015 to Direct Address 0x8.
   This sets the Host data width to 16-bit and assigns the external 
   HDATA[31:16] pins to JDATA[7:0].

3) Initialize Miscellaneous Mode (MMODE:Addr 0x9) Register
   Write hex value 0x000D to Direct Address 0x9.
   This disables Indirect Address Incrementing and sets up indirect
   accesses for internal 16-bit registers.

4) Enable External Interrupt (EIRQIE:Addr 0x5) Register
   Write hex value 0x0400 to Direct Address 0x5.
   This enables Software Interrupt 0 (SWIRQ0).

5) Set Indirect Address Register to External DMA0 Register (EDMOD0)
   Write hex value 0xffff to Direct Address 0xa (STAGE Reg).
   Write hex value 0x1408 to Direct Address 0xb (IADDR Reg).

6) Wait for IRQn low transition (or poll SWFLG for value 0xFF07) and
   then clear EIRQFLG by writing 0x0400 to Address 0x6.
   This indicates that initialization is complete and the Host can
   now enter the number of words to be written.

7) Use Command FIFO to initialize number of words to be written
   Write hex value 0x4144 to Direct Address 0x4 (COMMAND)
   Write hex value 0x5632 to Direct Address 0x4 (COMMAND)
   Write hex value 0x0000 to Direct Address 0x4 (COMMAND)
   Write hex value 0x0001 to Direct Address 0x4 (COMMAND)
   Write hex value 0x0000 to Direct Address 0x4 (COMMAND)
   Write hex value 0xXXXX to Direct Address 0x4 (COMMAND)

   The value of the last write is the number of 32-bit words to be
   written through the JDATA port. Since the JDATA port width is
   8-bits, this value is 4 times the number of JDATA transfers.
   A small number like 0x80 should be used initially until the test
   is confirmed to be running properly.

***NOTE: Steps 8 through 11 are set up as an infinite loop.

8) Wait for IRQn transition low again (or poll SWFLG for value 0x5555).
   This indicates that the part is ready to accept data after the Host
   enables the EDMA interface. This is done now by writing the value
   0x061B to the IDATA register (Addr:0xc). Please note that the data
   value is written to EDMOD0. This example sets VALID/HOLD to be both
   active high. This means that data will be transferred when DREQ0n is
   high and DACK0n is low. If opposite polarities are desired, the value
   written should be 0x001B. When polarities are changed, it is safer
   to first write the register with EDMA_EN bit set to zero, then drive
   the HOLD pin to the active state (to suppress unwanted transfers),
   and then enable the EDMA interface.

9) Clear Interrupt Flag (EIRQFLG:Addr 0x6) and begin JDATA writes.
   Write hex value 0x0400 to Direct Address 0x6.
   This will cause the IRQn signal to go to the high (inactive) state.
   JDATA writes can now begin. The number of bytes written should
   correspond to the number of words (X 4) programmed in Step 7.
   Once the programmed number of words are accepted by the ADV202, it
   will disable the JDATA port and re-initialize the configuration
   for JDATA reading (to check the written data). This will be indicated
   by a IRQn low transition (or by polling for 0xaaaa in SWFLG).

10) Wait for IRQn transition low (or poll SWFLG for value 0xaaaa).
    This indicates that the part is ready to provide data after the Host
    has enabled the EDMA interface. This is done now by writing the value
    0x061B to the IDATA register (Addr:0xc). This is similar to Step 8,
    but in this case this enables the EDMOD0 for reading. Again, data is
    transferred when DREQ0n is high and DACK0n is low. For opposite
    polarities, please follow the procedure described in Step 8.

11) Clear Interrupt Flag (EIRQFLG:Addr 0x6) and begin JDATA reads.
    Write hex value 0x0400 to Direct Address 0x6.
    This will cause the IRQn signal to go to the high (inactive) state.
    JDATA reads can now begin. The number of bytes read should
    correspond to the number of words (X 4) programmed in Step 7.
    Once the programmed number of words are read from the ADV202, it
    will disable the JDATA port and re-initialize the configuration
    for JDATA writing (loops back to Step 8). This will be indicated
    by a IRQn low transition (or by polling for 0x5555 in SWFLG).




