/* Copyright (c) 2021-2026, Analog Devices, Inc. All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *
 * 1. Redistributions of source code must retain the above copyright notice,
 * this list of conditions and the following disclaimer.
 *
 * 2. Redistributions in binary form must reproduce the above copyright notice,
 * this list of conditions and the following disclaimer in the documentation
 * and/or other materials provided with the distribution.
 *
 * 3. Neither the name of the copyright holder nor the names of its
 * contributors may be used to endorse or promote products derived from this
 * software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 */
/*!
* @brief     Abstract page table for core ARM0 of ADSP-SC846 family parts.
*
* @details
*            This is the table which defines the MMU attributes of memory.
*
*            The default distribution of L2 and L3 memory between the ARM and
*            the SHARC-FX cores is chosen to give the majority to the SHARC-FX
*            core, and smaller amounts to the ARM cores. However, the memory
*            requirements in your application for the ARM and SHARC-FX cores may
*            differ from this. In addition, the L3 memory allocated is that
*            which is available on the ADSPSC846W-EV-SOM board.
*
*            If you have a different amount of L3 memory, or change the
*            distribution of L2 or L3 memory between the cores, please note that
*            these changes must also be reflected in the ld script for core
*            ARM1 (adsp-sc846-arm1.ld), the Abstract Page Table for core ARM1
*            (apt-sc846-arm1.c), the ld scripts for your SHARC-FX projects,
*            and in the Abstract Page Table used for your ARM project.
*/

#if !defined(__ADSPSC846_FAMILY__)
 #error Target not supported
#endif

#include <runtime/mmu/adi_mmu.h>

/* See adi_mmu.h for definitions of the ADI_MMU_* memory class macros. */

#ifndef ADI_UNCACHED_SHARC_MEMORY
#define SHARC_L2 ADI_MMU_RO_CACHED
#define SHARC_L3 ADI_MMU_RO_CACHED
#else
#define SHARC_L2 ADI_MMU_RO_UNCACHED
#define SHARC_L3 ADI_MMU_RO_UNCACHED
#endif

/* ADI_CHANGES is defined for the default page table objects to ensure the
 * default symbols are weak.  Users should not define this macro when building
 * their application-specific page table.
 */
#ifdef ADI_CHANGES
const adi_mmu_AbstractPageEntry _adi_mmu_absPageTable[] __attribute__ ((weak)) =
#else
const adi_mmu_AbstractPageEntry _adi_mmu_absPageTable[] =
#endif
{
    /* THE ADDRESS RANGES IN THIS TABLE MUST BE IN ASCENDING ORDER. */

    /* L2 Boot ROM 2 */
    { 0x00000000u, 0x0000FFFFu, ADI_MMU_RO_CACHED           }, /* 64KB L2 Boot ROM 2 */

    /* L2 Boot ROM 1 */
    { 0x00010000u, 0x00017FFFu, ADI_MMU_RO_CACHED           }, /* 32KB L2 Boot ROM 1 */

    /* L2 SRAM */
 #if defined(__ADSPSC844__) || defined(__ADSPSC844W__)
    { 0x20600000u, 0x2060ffffu, ADI_MMU_RW_UNCACHED         }, /* 64KB ARM0 uncached L2 RAM */   
    { 0x20610000u, 0x20610fffu, ADI_MMU_RW_UNCACHED         }, /* 4KB ICC */
    { 0x20611000u, 0x20614fffu, ADI_MMU_RW_UNCACHED         }, /* 16KB ARM0 shared */
    { 0x20615000u, 0x20618fffu, ADI_MMU_RO_UNCACHED         }, /* 16KB ARM1 shared */
    { 0x20619000u, 0x2062ffffu, ADI_MMU_RO_UNCACHED         }, /* 92KB SHARC0 shared  */
    { 0x20630000u, 0x2063ffffu, ADI_MMU_RO_UNCACHED         }, /* 64KB ARM1 uncached L2 RAM */
    { 0x20640000u, 0x2069ffffu, ADI_MMU_WB_CACHED           }, /* 384KB ARM0 cached L2 RAM */
    { 0x206A0000u, 0x206Fffffu, ADI_MMU_RO_CACHED           }, /* 384KB ARM1 cached L2 RAM */
    { 0x20700000u, 0x207fffffu, SHARC_L2                    }, /* 1024KB SHARC0 cached L2 RAM */
 #elif defined(__ADSPSC846__) || defined(__ADSPSC846W__)
    { 0x20400000u, 0x2040ffffu, ADI_MMU_RW_UNCACHED         }, /* 64KB ARM0 uncached L2 RAM */   
    { 0x20410000u, 0x20410fffu, ADI_MMU_RW_UNCACHED         }, /* 4KB ICC */
    { 0x20411000u, 0x20414fffu, ADI_MMU_RW_UNCACHED         }, /* 16KB ARM0 shared */
    { 0x20415000u, 0x20418fffu, ADI_MMU_RO_UNCACHED         }, /* 16KB ARM1 shared */
    { 0x20419000u, 0x2042ffffu, ADI_MMU_RO_UNCACHED         }, /* 92KB SHARC0 shared  */
    { 0x20430000u, 0x2043ffffu, ADI_MMU_RO_UNCACHED         }, /* 64KB ARM1 uncached L2 RAM */
    { 0x20440000u, 0x2049ffffu, ADI_MMU_WB_CACHED           }, /* 384KB ARM0 cached L2 RAM */
    { 0x204A0000u, 0x204Fffffu, ADI_MMU_RO_CACHED           }, /* 384KB ARM1 cached L2 RAM */
    { 0x20500000u, 0x207fffffu, SHARC_L2                    }, /* 3072KB SHARC0 cached L2 RAM */
 #else
  #error Target not supported
 #endif
    
    { 0x24000000u, 0x24000fffu, ADI_MMU_RW_DEVICE           }, /* 4KB OTP space */

    /* L1 of SHARC0 in MP space */
    { 0x28240000u, 0x282BFFFFu, ADI_MMU_RO_CACHED           }, /* 512KB SHARC0 D-RAM via MP space*/
    { 0x282C0000u, 0x282CFFFFu, ADI_MMU_RO_CACHED           }, /* 64KB SHARC0 I-RAM via MP space */

    /* System MMR space */
    { 0x30000000u, 0x3FFFFFFFu, ADI_MMU_RW_DEVICE           }, /* 256MB System MMRs */

    /* SPI Flash memory-mapped address space.  */
    { 0x50000000u, 0x5FFFFFFFu, ADI_MMU_RW_DEVICE           }, /* 256MB xSPI flash */
    { 0x60000000u, 0x7FFFFFFFu, ADI_MMU_RW_DEVICE           }, /* 512MB SPI flash */

    /* Dynamic Memory Controller 0 (DMC0) 512MB SDRAM */
    { 0x80000000u, 0x8FFFFFFFu, SHARC_L3                    }, /* 256MB DDR-A */
    { 0x90000000u, 0x97FFFFFFu, ADI_MMU_WB_CACHED           }, /* 128MB DDR-A : ARM0 */
    { 0x98000000u, 0x9FFFFFFFu, ADI_MMU_RO_CACHED           }, /* 128MB DDR-A : ARM1 */
};

/* ADI_CHANGES is defined for the default page table objects to ensure the
 * default symbols are weak.  Users should not define this macro when building
 * their application-specific page table.
 */
#ifdef ADI_CHANGES
const uint32_t _adi_mmu_absPageTableSize __attribute__ ((weak)) = sizeof(_adi_mmu_absPageTable) / sizeof(_adi_mmu_absPageTable[0]);
#else
const uint32_t _adi_mmu_absPageTableSize = sizeof(_adi_mmu_absPageTable) / sizeof(_adi_mmu_absPageTable[0]);
#endif
