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	This directory is associated with Rev 1 of the Application Note


    		ADSP-SC84x SHARC-FX Processors Optimization (EE-485)  


	that can be found at http://www.analog.com/ee-notes


	Date Created:    July 15th, 2026
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CONTENTS

                1. DESCRIPTION
                2. VERSION INFORMATION
                3. DIRECTORY STRUCTURE

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1. DESCRIPTION

	This application note discusses various system bandwidth optimization techniques for ADSP-SC84x SHARC-FX Processors.



Codes inside codes-appnote folder:

Test1_MDMA_Throughput: This code shows the actual throughput measured on the bench for various MDMA streams with different combinations of source and destination memories.

Test2_MDMA_1Dauto:This code optimises non 32-byte aligned MDMA transfers by splitting the single MDMA transfer into more than one transfer using a descriptor-based DMA. 

Test3_MDMA_BW_limit:This code shows how MDMA bandwidth limit feature can be used to limit the MDMA throughput to maximum value.

Test4_MDMA_BW_Monitor:This code shows how bandwidth monitor feature of MDMA can be used to measure/monitor MDMA bandwidth.

Test5_EMDMA_Throughput:This code can be used to measure EMDMA throughput for different EMDMA streams for different combination of source and destination memories.

Test6_MDMA_circularbuffer:This code illustrates how a MDMA descriptor-based mode can be used to emulate a circular buffer memory-to-memory DMA transfer mode.

Test8_MDMA_Throughput_L2: This code shows the actual throughput measured when both source and destination buffers are in different L2 memory banks by varying MSIZE.

Test9_MDMA_Throughput_L3: This code shows the actual throughput measured for L3 by varying MSIZE and buffcount. Macros for both can be selected in header file. For L3 read, Source memory is in L3 and for L3 write, destination memory is in L3.

Bandwidth optimisation: This example code involves the following conditions.
	CCLK = 1.2GHz, DCLK = 1GHz, SYSCLK = 500MHz, SCLK0 = 125 MHz
	
	- MDMA0 channel 8, required throughput =  500 MHz * 4 <= 2000 MB/s.
	- MDMA1 channel 18, required throughput = 500 MHz * 4 <= 2000 MB/s.
	- MDMA2 channel 39, required throughput = 500 MHz * 4 <= 2000 MB/s.
	- MDMA3 channel 43, required throughput = 500 MHz * 8 <= 4000 MB/s.
    - MDMA4 channel 45, required throughput = 500 MHz * 4 <= 2000 MB/s.
	- MDMA5 channel 47, required throughput = 500 MHz * 4 <= 2000 MB/s.
	- Throughout requirements depend upon the corresponding DMAx_BWLCNT register values. If not programmed, the MDMA channels request for the bandwidth with full throttle.

The code can be run under different conditions by commenting/uncommenting the corresponding conditions/optimization techniques in the header file.


MMR_latency: This code shows the measured MMR latency in core cycles for different peripherals on the ADSP-SC84x processor

IDMA_throughput_test:This code shows the actual throughput measured on the bench for IDMA with different combinations of source and destination memories by placing either of source or destination residing in L1 memory.

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2. VERSION INFORMATION

Tested with:
Analog Devices CrossCore Embedded Studio 3.1.0
EV-SC846-SOM
ICE-1000

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3. DIRECTORY STRUCTURE

Codes_appnote
Logs_appnote