/*****************************************************************************
 * Test1_MDMA_Throughput_Core1.h
 *****************************************************************************/

#ifndef __TEST1_MDMA_THROUGHPUT_CORE1_H__
#define __TEST1_MDMA_THROUGHPUT_CORE1_H__


/* Add your custom header content here */
/*=============  INCLUDES  =============*/
#include <services/dma/adi_dma.h>
#include <services/spu/adi_spu.h>
#include <services/tru/adi_tru.h>
#include <services/pwr/adi_pwr.h>
#include <stdio.h>
#include "adi_initialize.h"
#include <sys/platform.h>
#include "math.h"
#include "stdlib.h"
/*=============  DEFINES   =============*/
/* Enable macro to display debug information */
#define ENABLE_DEBUG_INFO

/* Comment out this macro if L3 is not used */
#define ENABLE_L3

/* Memory Copy time out value */
#define MEMCOPY_TIME_OUT_VAL        (0x7FFFFFFu)

#define MDMA0_SRC_DMA8_SPU_PID       (140u)
#define MDMA0_DST_DMA9_SPU_PID       (141u)
#define MDMA1_SRC_DMA18_SPU_PID      (142u)
#define MDMA1_DST_DMA19_SPU_PID      (143u)
#define MDMA2_SRC_DMA39_SPU_PID      (128u) /* Enhanced BW DMA 0 */
#define MDMA3_SRC_DMA43_SPU_PID      (129u) /* Max BW DMA 0 */

#define MDMA4_SRC_DMA45_SPU_PID      (144u)
#define MDMA4_DST_DMA46_SPU_PID      (145u)
#define MDMA5_SRC_DMA47_SPU_PID      (146u)
#define MDMA5_DST_DMA48_SPU_PID      (147u)
#define MDMA6_SRC_DMA49_SPU_PID      (152u) /* Enhanced BW DMA 1 */
#define MDMA7_SRC_DMA51_SPU_PID      (130u) /* Max BW DMA 1 */

#define SOFT0_TRIGGER_MASTER_ID		 (167u)

#define MDMA0_SRC_TRIGGER_SLAVE_ID		 (11u)
#define MDMA0_DST_TRIGGER_SLAVE_ID		 (12u)
#define MDMA1_SRC_TRIGGER_SLAVE_ID		 (13u)
#define MDMA1_DST_TRIGGER_SLAVE_ID		 (14u)
#define MDMA2_SRC_TRIGGER_SLAVE_ID		 (77u)
#define MDMA2_DST_TRIGGER_SLAVE_ID		 (78u)
#define MDMA3_SRC_TRIGGER_SLAVE_ID		 (79u)
#define MDMA3_DST_TRIGGER_SLAVE_ID		 (80u)
#define MDMA4_SRC_TRIGGER_SLAVE_ID		 (15u)
#define MDMA4_DST_TRIGGER_SLAVE_ID		 (16u)
#define MDMA5_SRC_TRIGGER_SLAVE_ID		 (17u)
#define MDMA5_DST_TRIGGER_SLAVE_ID		 (18u)
#define MDMA6_SRC_TRIGGER_SLAVE_ID		 (81u)
#define MDMA6_DST_TRIGGER_SLAVE_ID		 (82u)
#define MDMA7_SRC_TRIGGER_SLAVE_ID		 (83u)
#define MDMA7_DST_TRIGGER_SLAVE_ID		 (84u)

#define TRU0_SLV0_TRIGGER_SLAVE_ID		 (224u) /* SEC C1 - 161, SEC C2 - 165, Direct Int0 - 188 */

/* Maximum transfer size in bytes */
#define MAX_MEMCOPY_BUF_SIZE	16384

/* IF (Debug info enabled) */
#if defined(ENABLE_DEBUG_INFO)
#define DBG_MSG                     printf
#else
#define DBG_MSG(...)
#endif

/* Maximum number of test combinations */
#define MAX_TEST_COMBINATIONS 1000

/* Change the test parameter input file name here if required */
#define TEST_PARAM_INPUT_FILE "testparam.dat"

/* Enumeration for different type of memories */
typedef enum MEMTYPE
{
	L1MEM,
	L2MEM,
	L3MEM
} MEMTYPE;

typedef struct TEST_PARAM
{
	int32_t 			TestIndex;			/* Test index */
	ADI_DMA_STREAM_ID 	eStreamID;			/* Stream ID */
	MEMTYPE  			eSourceMem;			/* Source memory type (L1/L2/L3) or direct address */
	MEMTYPE 			eDestMem;			/* Destination memory type (L1/L2/L3) or direct address */
	uint32_t			BuffCount;			/* Buffer count in MSIZE unit */
	ADI_DMA_MSIZE		eMsizeCfg;			/* Element width or MSIZE configuration to be used */
} TEST_PARAM;

typedef struct FAILURE_INFO
{
	uint32_t		TestIndex;
	ADI_DMA_RESULT	ErrorCode;
}FAILURE_INFO;

typedef struct TEST_INFO
{
	TEST_PARAM 		*pTestParamList;
	uint32_t 		FailCount;
	FAILURE_INFO	FailedTestInfo[MAX_TEST_COMBINATIONS];
}TEST_INFO;


#endif /* __TEST1_MDMA_THROUGHPUT_CORE1_H__ */
