Version 4.1 SHEET 1 3364 2592 WIRE -592 -464 -672 -464 WIRE -480 -464 -592 -464 WIRE -384 -464 -480 -464 WIRE 192 -464 -384 -464 WIRE 864 -464 192 -464 WIRE -672 -432 -672 -464 WIRE -592 -416 -592 -464 WIRE -480 -416 -480 -464 WIRE -384 -416 -384 -464 WIRE -80 -416 -192 -416 WIRE 32 -416 -80 -416 WIRE 112 -416 32 -416 WIRE 192 -416 192 -464 WIRE -192 -400 -192 -416 WIRE -80 -368 -80 -416 WIRE 304 -352 288 -352 WIRE 384 -352 368 -352 WIRE 112 -336 112 -416 WIRE 192 -336 192 -416 WIRE 288 -336 288 -352 WIRE 368 -336 368 -352 WIRE -672 -304 -672 -352 WIRE -592 -304 -592 -352 WIRE -480 -304 -480 -352 WIRE -384 -288 -384 -336 WIRE -320 -288 -384 -288 WIRE -288 -288 -320 -288 WIRE -192 -288 -192 -336 WIRE -384 -256 -384 -288 WIRE -288 -256 -288 -288 WIRE -80 -240 -80 -288 WIRE 32 -240 -80 -240 WIRE -384 -144 -384 -176 WIRE -336 -144 -384 -144 WIRE -288 -144 -288 -192 WIRE -288 -144 -336 -144 WIRE 32 -144 -48 -144 WIRE -336 -112 -336 -144 WIRE 32 -32 -48 -32 WIRE 496 -32 448 -32 WIRE 592 -32 560 -32 WIRE 864 32 864 -464 WIRE 560 64 448 64 WIRE 720 64 640 64 WIRE 720 112 720 64 WIRE 816 112 720 112 WIRE 32 160 -48 160 WIRE 560 160 448 160 WIRE 720 160 720 112 WIRE 720 160 640 160 WIRE -144 256 -176 256 WIRE 32 256 -64 256 WIRE 864 256 864 128 WIRE 864 256 448 256 WIRE 1024 256 864 256 WIRE 1184 256 1104 256 WIRE 1200 256 1184 256 WIRE 1296 256 1280 256 WIRE 1360 256 1296 256 WIRE 1456 256 1360 256 WIRE 1568 256 1456 256 WIRE 1680 256 1568 256 WIRE 1456 288 1456 256 WIRE 1568 288 1568 256 WIRE 1680 288 1680 256 WIRE 864 320 864 256 WIRE 32 352 -48 352 WIRE 560 352 448 352 WIRE 720 352 640 352 WIRE 1456 384 1456 352 WIRE 1568 384 1568 352 WIRE 1680 384 1680 368 WIRE 720 400 720 352 WIRE 816 400 720 400 WIRE -48 448 -48 352 WIRE 32 448 -48 448 WIRE 560 448 448 448 WIRE 720 448 720 400 WIRE 720 448 640 448 WIRE 864 480 864 416 WIRE -48 544 -48 448 WIRE -48 544 -96 544 WIRE 32 544 -48 544 WIRE 576 544 448 544 WIRE 1184 544 1184 256 WIRE 1184 544 576 544 WIRE 576 560 576 544 WIRE -112 640 -144 640 WIRE 32 640 -48 640 WIRE 576 640 576 624 WIRE 576 640 448 640 WIRE 1296 640 1296 256 WIRE 1296 640 576 640 WIRE -48 736 -144 736 WIRE 32 736 -48 736 WIRE 576 736 448 736 WIRE 656 736 576 736 WIRE 1360 736 1360 256 WIRE 1360 736 736 736 WIRE -144 752 -144 736 WIRE 576 768 576 736 WIRE -48 816 -48 736 WIRE -144 864 -144 832 WIRE 144 864 144 832 WIRE 240 864 240 832 WIRE 336 864 336 832 WIRE 576 864 576 848 WIRE -144 944 -144 928 WIRE -96 944 -144 944 WIRE -48 944 -48 880 WIRE -48 944 -96 944 WIRE -96 976 -96 944 FLAG -672 -304 0 FLAG -672 -464 VIN FLAG -336 -112 0 FLAG -320 -288 RUN FLAG 288 -352 RUN FLAG 32 -416 INTVCC FLAG -80 -240 PGOOD FLAG -48 -144 0 FLAG -48 -32 INTVCC FLAG -48 160 0 FLAG -176 256 0 FLAG -96 544 INTVCC FLAG -144 640 0 FLAG -96 976 0 FLAG 144 864 0 FLAG 336 864 0 FLAG 576 864 0 FLAG 864 480 0 FLAG 1456 384 0 FLAG 1568 384 0 FLAG 1680 384 0 FLAG 1680 256 OUT FLAG -192 -288 0 FLAG 864 256 SW FLAG 368 -352 OUT FLAG 592 -32 SW FLAG -592 -304 0 FLAG -480 -304 0 FLAG 256 -416 0 FLAG 240 864 0 SYMBOL PowerProducts\\LTC7891 240 176 R0 SYMATTR InstName U1 SYMBOL voltage -672 -448 M0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V1 SYMATTR Value PWL(0 0 200u 48) SYMBOL res -400 -432 R0 SYMATTR InstName R1 SYMATTR Value 412k SYMBOL res -400 -272 R0 SYMATTR InstName R2 SYMATTR Value 36.5k SYMBOL cap -304 -256 R0 SYMATTR InstName C1 SYMATTR Value 100p SYMBOL res -96 -384 R0 SYMATTR InstName R3 SYMATTR Value 1000k SYMBOL res -48 240 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R4 SYMATTR Value 73.2k SYMBOL cap -48 624 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName C2 SYMATTR Value 10n SYMBOL res -160 736 R0 SYMATTR InstName R5 SYMATTR Value 10k SYMBOL res 656 48 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R6 SYMATTR Value 2.2 SYMBOL res 656 144 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R7 SYMATTR Value 1 SYMBOL res 656 432 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R8 SYMATTR Value 1 SYMBOL res 656 336 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R9 SYMATTR Value 1 SYMBOL cap -64 816 R0 SYMATTR InstName C3 SYMATTR Value 100p SYMBOL cap -160 864 R0 SYMATTR InstName C4 SYMATTR Value 4.7n SYMBOL res 752 720 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R10 SYMATTR Value 604k SYMBOL res 560 752 R0 SYMATTR InstName R11 SYMATTR Value 43.2k SYMBOL cap 560 560 R0 SYMATTR InstName C5 SYMATTR Value 1n SYMBOL ind 1008 272 R270 WINDOW 0 32 56 VTop 2 WINDOW 3 5 56 VBottom 2 SYMATTR InstName L1 SYMATTR Value 3.1µ SYMATTR SpiceLine Rser=0.0023 SYMBOL res 1296 240 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R12 SYMATTR Value 1.5m SYMBOL cap 560 -48 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName C6 SYMATTR Value 0.1µ SYMBOL polcap 1552 288 R0 WINDOW 3 24 56 Left 2 WINDOW 123 25 81 Left 2 SYMATTR Value 150µF SYMATTR Value2 x2 SYMATTR InstName Cout1 SYMATTR Description Capacitor SYMATTR Type cap SYMATTR SpiceLine Rser=0.05 SYMBOL res 1664 272 R0 SYMATTR InstName Rload SYMATTR Value 0.6 SYMBOL cap 1440 288 R0 WINDOW 123 24 84 Left 2 SYMATTR Value2 x4 SYMATTR InstName Cout2 SYMATTR Value 22µF SYMBOL cap -208 -400 R0 SYMATTR InstName C7 SYMATTR Value 4.7µ SYMBOL cap -496 -416 R0 WINDOW 123 24 84 Left 2 SYMATTR Value2 x4 SYMATTR InstName Cin2 SYMATTR Value 10µF SYMBOL polcap -608 -416 R0 WINDOW 3 24 56 Left 2 WINDOW 123 25 81 Left 2 SYMATTR Value 47µ SYMATTR Value2 x2 SYMATTR InstName Cin1 SYMATTR Description Capacitor SYMATTR Type cap SYMATTR SpiceLine Rser=0.05 SYMBOL cap 256 -432 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName C8 SYMATTR Value 0.1µ SYMBOL nmos 816 32 R0 SYMATTR InstName Q1 SYMATTR Value EPC2218 SYMATTR Prefix x SYMBOL nmos 816 320 R0 SYMATTR InstName Q2 SYMATTR Value EPC2218 SYMATTR Prefix x TEXT 240 -688 Center 5 ;LTC7891 - 100V GaN FET Buck Controller\nHIGH FREQUENCY, STEP-DOWN SUPPLY with EPC GaN FETs\nInput: 15V to 72V Output: 12V @ 20A Switching Frequency: 500kHz TEXT -184 1024 Left 3 ;Notes: \nSmaller values are used for SS capacitors to reduce simulation time. See datasheet for typical values.\nIf the simulation model is not found please update with the "Update components" command from the "Tools" menu.\nIt remains the customer's responsibility to verify proper and reliable operation in the actual application.\nThis circuit is distributed to customers only for use with Analog Devices parts. TEXT 464 920 Left 2 !.tran 1.2m startup TEXT 1312 -456 Left 0 !.subckt EPC2218 drainin gatein sourcein\n.param si={aWg*7.500e-04} so={aWg*3.900e-03} sr={aWg}\n.param aWg={Wg*1E-3} Wg=1545000 A1={4.555e-02*aWg} k2=1.824e+00 k3=9.000e-02 rpara=1.975e-03\n+ rpara_s_factor=3.229e-01 aITc=3.000e-03 arTc=-7.500e-03 k2Tc=6.000e-04\n+ x0_0=6.137e+00 x0_0_TC=-2.000e-03 x0_1=-2.623e-01 x0_1_TC=0.000e+00\n+ dgs1=4.3e-07 dgs2=2.6e-13 dgs3=0.8 dgs4=0.23\n+ ags1={1.023e-09*si} ags2={5.465e-10*si} ags3=1.604e+00 ags4=1.861e-01\n+ ags5={1.732e-10*si} ags6=7.480e+01 ags7=1.055e+01\n+ agd1={1.942e-15*sr} agd2={1.178e-13*sr} agd3=-5.000e+00 agd4=4.314e+00\n+ agd5={7.786e-15*sr} agd6=-1.726e+01 agd7=1.529e+01 agd8={1.742e-15*sr}\n+ agd9=-3.326e+01 agd10=8.900e-01\n+ asd1={8.330e-11*so} asd2={4.297e-11*so} asd3=-1.435e+01 asd4=1.287e+00\n+ asd5={1.155e-10*so} asd6=-2.014e+01 asd7=9.467e+00 asd8={4.647e-12*so}\n+ asd9=-8.125e+01 asd10=5.665e+00\n+ rg_value=0.4\n \nrd drainin drain {((1-rpara_s_factor)*rpara*(1-arTc*(Temp-25)))}\nrs sourcein source {(rpara_s_factor*rpara*(1-arTc*(Temp-25)))}\nrg gatein gate {(rg_value)}\n \nRcsdconv drain source {100000Meg/aWg}\nRcgsconv gate source {100000Meg/aWg}\nRcgdconv gate drain {100000Meg/aWg}\n \nbswitch drain source I=if(v(drain,source)>0,\n+ (A1*(1-aITc*(Temp-25))*log(1.0+exp((v(gate,source)-(k2*(1-k2Tc*(Temp-25))))/k3))* \n+ v(drain,source)/(1 + (x0_0*(1-x0_0_TC*(Temp-25))+x0_1*(1-x0_1_TC*(Temp-25))*v(gate,source))*v(drain,source))),\n+ (-A1*(1-aITc*(Temp-25))*log(1.0+exp((v(gate,drain)-(k2*(1-k2Tc*(Temp-25))))/k3))* \n+ v(source,drain)/(1 + (x0_0*(1-x0_0_TC*(Temp-25))+x0_1*(1-x0_1_TC*(Temp-25))*v(gate,drain))*v(source,drain))))\n \nbgsdiode gate source I=if( v(gate,source)>10,\n+ (0.125*aWg/1077*(dgs1*(exp((10.0)/dgs3)-1)+dgs2*(exp((10.0)/dgs4)-1))),\n+ (0.125*aWg/1077*(dgs1*(exp((v(gate,source))/dgs3)-1)+dgs2*(exp((v(gate,source))/dgs4)-1))))\n \nbgddiode gate drain I=if( v(gate,drain)>10,\n+ (0.125*aWg/1077*(dgs1*(exp((10.0)/dgs3)-1)+dgs2*(exp((10.0)/dgs4)-1))),\n+ (0.125*aWg/1077*(dgs1*(exp((v(gate,drain))/dgs3)-1)+dgs2*(exp((v(gate,drain))/dgs4)-1))))\n \n \nC_GS gate source {ags1} TC=0,0\nC_CGS1 gate source Q=(0.5*ags2*ags4*log(1+exp((v(gate,source)-ags3)/ags4))+\n+ ags5*ags7*log(1+exp((v(source,drain)-ags6)/ags7)))\n \nC_GD gate drain {agd1} TC=0,0 \nC_CGD1 gate drain Q=(0.5*ags2*ags4*log(1+exp((v(gate,drain)-ags3)/ags4))+\n+ agd2*agd4*log(1+exp((v(gate,drain)-agd3)/agd4))+\n+ agd5*agd7*log(1+exp((v(gate,drain)-agd6)/agd7))+ \n+ agd8*agd10*log(1+exp((v(gate,drain)-agd9)/agd10)))\n \nC_SD source drain {asd1} TC=0,0\nC_CSD1 source drain Q=(asd2*asd4*log(1+exp((v(source,drain)-asd3)/asd4))+\n+ asd5*asd7*log(1+exp((v(source,drain)-asd6)/asd7))+ \n+ asd8*asd10*log(1+exp((v(source,drain)-asd9)/asd10))) \n \n.ends TEXT 1320 -528 Left 3 ;Subcircuit below from EPC GaN Power Device Library\nFor more sub cicuit models go to: https://epc-co.com/epc/design-support/device-models TEXT -240 312 Left 2 ;73.2k for 500kHz Fsw TEXT -968 448 Left 2 ;DTCA and DTCB tied to INTVCC for Smart Near Zero delay\noptional connections: GND for adaptive 20ns dead time\n 10k© -200k© resistor to GND for 7ns - 60ns deadtime TEXT 472 -264 Left 2 ;VPRG floating to set output \nwith external feedback divider TEXT -968 56 Left 2 ;ILIM floating for 50mV max current sense threshold\nOptional connection: GND for 25mV, INTVCC for 75mV TEXT 32 896 Left 2 ;DRVset tied to GND to set INTVCC to 5V\noptional connection:\nINTVCC to set to 5.5V\n50k© - 110k© resistor to GND to set between 4V and 5.5V TEXT -968 320 Left 2 ;Mode tied to INTVCC for FCM operation at light loads\noptional connections: INTVCC through 100k© Resistor for Pulse skip Mode\n GND for Burst Mode TEXT -968 144 Left 2 ;PLLIN tied to GND to disable Spread Spectrum\noptional connection: INTVCC to enable Spread Spectrum\n Input for external clock syncronization