# |
NAME |
DIR |
[LSB:MSB] |
SIG |
ATTRIBUTES |
axi_gpio_LED
|
axi_gpio_LED_GPIO_IO_pin |
IO |
0:7 |
axi_gpio_LED_GPIO_IO |
|
axi_gpio_OLED
|
axi_gpio_OLED_GPIO_IO_O_pin |
O |
0:7 |
axi_gpio_OLED_GPIO_IO_O |
|
axi_millbrae_0
|
axi_millbrae_0_ADC_MISO1_pin |
I |
1 |
axi_millbrae_0_ADC_MISO1 |
|
axi_millbrae_0
|
axi_millbrae_0_ADC_MISO2_pin |
I |
1 |
axi_millbrae_0_ADC_MISO2 |
|
axi_millbrae_0
|
axi_millbrae_0_ADC_SCLKR1_pin |
I |
1 |
axi_millbrae_0_ADC_SCLKR1 |
|
axi_millbrae_0
|
axi_millbrae_0_ADC_SCLKR2_pin |
I |
1 |
axi_millbrae_0_ADC_SCLKR2 |
|
axi_millbrae_0
|
axi_millbrae_0_DAC_BUSY1_pin |
I |
1 |
axi_millbrae_0_DAC_BUSY1 |
|
axi_millbrae_0
|
axi_millbrae_0_DAC_BUSY2_pin |
I |
1 |
axi_millbrae_0_DAC_BUSY2 |
|
axi_millbrae_0
|
axi_millbrae_0_ADC_CONVST1_pin |
O |
1 |
axi_millbrae_0_ADC_CONVST1 |
|
axi_millbrae_0
|
axi_millbrae_0_ADC_CONVST2_pin |
O |
1 |
axi_millbrae_0_ADC_CONVST2 |
|
axi_millbrae_0
|
axi_millbrae_0_ADC_MOSI1_pin |
O |
1 |
axi_millbrae_0_ADC_MOSI1 |
|
axi_millbrae_0
|
axi_millbrae_0_ADC_MOSI2_pin |
O |
1 |
axi_millbrae_0_ADC_MOSI2 |
|
axi_millbrae_0
|
axi_millbrae_0_ADC_SCLK1_pin |
O |
1 |
axi_millbrae_0_ADC_SCLK1 |
|
axi_millbrae_0
|
axi_millbrae_0_ADC_SCLK2_pin |
O |
1 |
axi_millbrae_0_ADC_SCLK2 |
|
axi_millbrae_0
|
axi_millbrae_0_DAC_CS1_pin |
O |
1 |
axi_millbrae_0_DAC_CS1 |
|
axi_millbrae_0
|
axi_millbrae_0_DAC_CS2_pin |
O |
1 |
axi_millbrae_0_DAC_CS2 |
|
axi_millbrae_0
|
axi_millbrae_0_DAC_LDAC1_pin |
O |
1 |
axi_millbrae_0_DAC_LDAC1 |
|
axi_millbrae_0
|
axi_millbrae_0_DAC_LDAC2_pin |
O |
1 |
axi_millbrae_0_DAC_LDAC2 |
|
axi_millbrae_0
|
axi_millbrae_0_DAC_MOSI1_pin |
O |
1 |
axi_millbrae_0_DAC_MOSI1 |
|
axi_millbrae_0
|
axi_millbrae_0_DAC_MOSI2_pin |
O |
1 |
axi_millbrae_0_DAC_MOSI2 |
|
axi_millbrae_0
|
axi_millbrae_0_DAC_RST1_pin |
O |
1 |
axi_millbrae_0_DAC_RST1 |
|
axi_millbrae_0
|
axi_millbrae_0_DAC_RST2_pin |
O |
1 |
axi_millbrae_0_DAC_RST2 |
|
axi_millbrae_0
|
axi_millbrae_0_DAC_SCLK1_pin |
O |
1 |
axi_millbrae_0_DAC_SCLK1 |
|
axi_millbrae_0
|
axi_millbrae_0_DAC_SCLK2_pin |
O |
1 |
axi_millbrae_0_DAC_SCLK2 |
|
processing_system7_0
|
processing_system7_0_PS_CLK |
I |
1 |
processing_system7_0_PS_CLK |
CLK |
processing_system7_0
|
processing_system7_0_PS_PORB |
I |
1 |
processing_system7_0_PS_PORB |
|
processing_system7_0
|
processing_system7_0_PS_SRSTB |
I |
1 |
processing_system7_0_PS_SRSTB |
|
processing_system7_0
|
processing_system7_0_DDR_Addr |
IO |
0:14 |
processing_system7_0_DDR_Addr |
|
processing_system7_0
|
processing_system7_0_DDR_BankAddr |
IO |
0:2 |
processing_system7_0_DDR_BankAddr |
|
processing_system7_0
|
processing_system7_0_DDR_CAS_n |
IO |
1 |
processing_system7_0_DDR_CAS_n |
|
processing_system7_0
|
processing_system7_0_DDR_CKE |
IO |
1 |
processing_system7_0_DDR_CKE |
|
processing_system7_0
|
processing_system7_0_DDR_CS_n |
IO |
1 |
processing_system7_0_DDR_CS_n |
|
processing_system7_0
|
processing_system7_0_DDR_Clk |
IO |
1 |
processing_system7_0_DDR_Clk |
CLK |
processing_system7_0
|
processing_system7_0_DDR_Clk_n |
IO |
1 |
processing_system7_0_DDR_Clk_n |
CLK |
processing_system7_0
|
processing_system7_0_DDR_DM |
IO |
0:3 |
processing_system7_0_DDR_DM |
|
processing_system7_0
|
processing_system7_0_DDR_DQ |
IO |
0:31 |
processing_system7_0_DDR_DQ |
|
processing_system7_0
|
processing_system7_0_DDR_DQS |
IO |
0:3 |
processing_system7_0_DDR_DQS |
|
processing_system7_0
|
processing_system7_0_DDR_DQS_n |
IO |
0:3 |
processing_system7_0_DDR_DQS_n |
|
processing_system7_0
|
processing_system7_0_DDR_DRSTB |
IO |
1 |
processing_system7_0_DDR_DRSTB |
RESET |
processing_system7_0
|
processing_system7_0_DDR_ODT |
IO |
1 |
processing_system7_0_DDR_ODT |
|
processing_system7_0
|
processing_system7_0_DDR_RAS_n |
IO |
1 |
processing_system7_0_DDR_RAS_n |
|
processing_system7_0
|
processing_system7_0_DDR_VRN |
IO |
1 |
processing_system7_0_DDR_VRN |
|
processing_system7_0
|
processing_system7_0_DDR_VRP |
IO |
1 |
processing_system7_0_DDR_VRP |
|
processing_system7_0
|
processing_system7_0_MIO |
IO |
0:53 |
processing_system7_0_MIO |
|
processing_system7_0
|
processing_system7_0_DDR_WEB_pin |
O |
1 |
processing_system7_0_DDR_WEB |
|