MAXREFDES71# Code Documentation  V01.00
MAXREFDES71# 2-Channel Analog Input/Analog Output
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axi_millbrae.c
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1 
28 /*
29  * Copyright (C) 2012 Maxim Integrated Products, Inc., All Rights Reserved.
30  *
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32  * copy of this software and associated documentation files (the "Software"),
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36  * Software is furnished to do so, subject to the following conditions:
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59 
60 /***************************** Include Files *******************************/
61 
62 #include "axi_millbrae.h"
63 
64 /************************** Function Definitions ***************************/
65 
66 void AXI_MILLBRAE_Config_ADC(u32 BaseAddress, u32 Value)
76 {
77  Xil_Out32((BaseAddress) + (AXI_MILLBRAE_ADC_CONF_REG_OFFSET), Value);
78  Xil_Out32((BaseAddress) + (AXI_MILLBRAE_WRITE_ADC_CR_REG_OFFSET), (u32)(1));
79 }
80 
81  void AXI_MILLBRAE_Config_DAC(u32 BaseAddress, u32 Value)
91 {
92  Xil_Out32((BaseAddress) + (AXI_MILLBRAE_DAC_CONF_REG_OFFSET), Value);
93  Xil_Out32((BaseAddress) + (AXI_MILLBRAE_WRITE_DAC_CR_REG_OFFSET), (u32)(1));
94 }
95 
96  void AXI_MILLBRAE_Start_Conversion(u32 BaseAddress)
109  {
110  Xil_Out32((BaseAddress) + (AXI_MILLBRAE_MODE_REG_OFFSET), (u32)(0));
111  Xil_Out32((BaseAddress) + (AXI_MILLBRAE_START_OPERATION_REG_OFFSET), (u32)(1));
112  }
113 
114  void AXI_MILLBRAE_Stop_Operation(u32 BaseAddress)
125  {
126  Xil_Out32((BaseAddress) + (AXI_MILLBRAE_START_OPERATION_REG_OFFSET), (u32)(0));
127  }
128 
129  void AXI_MILLBRAE_Start_Replication(u32 BaseAddress)
142  {
143  Xil_Out32((BaseAddress) + (AXI_MILLBRAE_START_OPERATION_REG_OFFSET), (u32)(0));
144  AXI_MILLBRAE_Interrupt_Disable(BaseAddress);
145  Xil_Out32((BaseAddress) + (AXI_MILLBRAE_MODE_REG_OFFSET), (u32)(1));
146  Xil_Out32((BaseAddress) + (AXI_MILLBRAE_START_OPERATION_REG_OFFSET), (u32)(1));
147  }
148 
149  void AXI_MILLBRAE_Write_Timer_Reg(u32 BaseAddress, u32 Value)
162  {
163  Xil_Out32((BaseAddress) + (AXI_MILLBRAE_TIMER_REG_OFFSET), (u32)(Value));
164  }
165 
166  void AXI_MILLBRAE_Interrupt_Enable(u32 BaseAddress)
179  {
180  Xil_Out32((BaseAddress) + (AXI_MILLBRAE_IP_INTR_ENABLE_REG_OFFSET), (u32)(1));
181  }
182 
183  void AXI_MILLBRAE_Interrupt_Disable(u32 BaseAddress)
194  {
195  Xil_Out32((BaseAddress) + (AXI_MILLBRAE_IP_INTR_ENABLE_REG_OFFSET), (u32)(0));
196  }
197 
198  u32 AXI_MILLBRAE_Read_Data(u32 BaseAddress, u8 Channel)
210  {
211  return Xil_In32((BaseAddress) + 0x00000004*Channel);
212  }
213 
227  {
228  return Xil_In32((BaseAddress) + (AXI_MILLBRAE_IP_INTR_STATUS_REG_OFFSET));
229  }
230 
231  void AXI_MILLBRAE_Single_Convert(u32 BaseAddress, u8 Channel, u16 * uSample)
241  {
242  u32 temp;
243  AXI_MILLBRAE_Stop_Operation(BaseAddress);
244  AXI_MILLBRAE_Interrupt_Disable(BaseAddress);
245  temp=AXI_MILLBRAE_Read_Interrupt_Status(BaseAddress);
246  AXI_MILLBRAE_Write_Timer_Reg(BaseAddress, 25000000);
247  AXI_MILLBRAE_Start_Conversion(BaseAddress);
248 
249  while(AXI_MILLBRAE_Read_Interrupt_Status(BaseAddress)==0);
250  AXI_MILLBRAE_Stop_Operation(BaseAddress);
251  temp=AXI_MILLBRAE_Read_Interrupt_Status(BaseAddress);
252 
253  if(Channel<2)
254  uSample[0]=AXI_MILLBRAE_Read_Data(BaseAddress, Channel);
255  else
256  {
257  uSample[0]=AXI_MILLBRAE_Read_Data(BaseAddress, 0);
258  uSample[1]=AXI_MILLBRAE_Read_Data(BaseAddress, 1);
259  }
260  }