---
type: Analog Component
title: "MAX17795 — 3V to 80V, 5A, High-Efficiency, Synchronous Step-Down DC-DC Converter"
description: "3V to 80V, 5A, High-Efficiency, Synchronous Step-Down DC-DC Converter"
resource: "https://www.analog.com/en/products/max17795.html"
tags: ["datasheet", "okf-r12-batch1", "maxim"]
generated: { by: "agentforge/aa0b0641", at: "2026-09-29T20:23:52Z" }
status: draft
sources:
  - id: "datasheet"
    resource: "https://www.analog.com/media/en/technical-documentation/data-sheets/max17795.pdf"
    title: "MAX17795 data sheet"
    author: "team:analog-devices"
tables:
  - file: "max17795/tables/table-00-p3-data.csv"
    title: "Revision History"
    page: 3
  - file: "max17795/tables/table-01-p4-spec.csv"
    title: "Table 1. Electrical Characteristics"
    page: 4
  - file: "max17795/tables/table-02-p8-abs_max.csv"
    title: "Table 2. Absolute Maximum Ratings"
    page: 8
  - file: "max17795/tables/table-03-p9-pin.csv"
    title: "Pin Descriptions"
    page: 9
  - file: "max17795/tables/table-04-p18-data.csv"
    title: "Table 3. Switching Frequency vs. RRT Resistor"
    page: 18
  - file: "max17795/tables/table-05-p27-data.csv"
    title: "Table 4. Thermal Resistance of 18L FC2QFN"
    page: 27
  - file: "max17795/tables/table-06-p30-data.csv"
    title: "Ordering Guide"
    page: 30
figures:
  - file: "max17795/figures/max17795-eqx01.png"
    caption: "Equation as printed (p. 22)"
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    page: 22
  - file: "max17795/figures/max17795-f000.png"
    caption: ""
    type: "other"
    page: 1
  - file: "max17795/figures/max17795-f001.png"
    caption: "Figure 1. Typical Application Circuit"
    type: "application_circuit"
    page: 1
  - file: "max17795/figures/max17795-f002.png"
    caption: "Figure 2. Efficiency vs. load current (Figure 30 Circuit)"
    type: "characteristic_curve"
    page: 1
  - file: "max17795/figures/max17795-f003.png"
    caption: "Figure 3. MAX17795 Pin Configuration"
    type: "pinout"
    page: 9
  - file: "max17795/figures/max17795-f004.png"
    caption: "Figure 4. MAX17795 Functional Diagram"
    type: "block_diagram"
    page: 11
  - file: "max17795/figures/max17795-f005.png"
    caption: "Figure 5. Efficiency vs. Load Current (Figure 30 Circuit)"
    type: "characteristic_curve"
    page: 12
  - file: "max17795/figures/max17795-f006.png"
    caption: "Figure 8. Efficiency vs. Load Current (Figure 31 Circuit)"
    type: "characteristic_curve"
    page: 12
  - file: "max17795/figures/max17795-f007.png"
    caption: "Figure 11. Efficiency vs. Load Current (Figure 33 Circuit)"
    type: "characteristic_curve"
    page: 12
  - file: "max17795/figures/max17795-f008.png"
    caption: "Figure 6. Efficiency vs. Load Current (Figure 30 Circuit)"
    type: "characteristic_curve"
    page: 12
  - file: "max17795/figures/max17795-f009.png"
    caption: "Figure 7. Efficiency vs. Load Current (Figure 31 Circuit)"
    type: "characteristic_curve"
    page: 12
  - file: "max17795/figures/max17795-f010.png"
    caption: "Figure 9. Efficiency vs. Load Current (Figure 32 Circuit)"
    type: "characteristic_curve"
    page: 12
  - file: "max17795/figures/max17795-f011.png"
    caption: "Figure 12. Efficiency vs. Load Current (Figure 33 Circuit)"
    type: "characteristic_curve"
    page: 12
  - file: "max17795/figures/max17795-f012.png"
    caption: "Figure 10. Efficiency vs. Load Current (Figure 32 Circuit)"
    type: "characteristic_curve"
    page: 12
  - file: "max17795/figures/max17795-f013.png"
    caption: "Figure 13. Output Voltage vs. Load Current (Figure 30 Circuit)"
    type: "characteristic_curve"
    page: 12
  - file: "max17795/figures/max17795-f014.png"
    caption: "Figure 14. Output Voltage vs. Load Current (Figure 31 Circuit)"
    type: "characteristic_curve"
    page: 13
  - file: "max17795/figures/max17795-f015.png"
    caption: "Figure 15. Output Voltage vs. Load Current (Figure 32 Circuit)"
    type: "characteristic_curve"
    page: 13
  - file: "max17795/figures/max17795-f016.png"
    caption: "Figure 17. Start-up/Shutdown Through EN/UV (Figure 30 Circuit)"
    type: "scope_capture"
    page: 13
  - file: "max17795/figures/max17795-f017.png"
    caption: "Figure 19. Steady-State Switching Waveform (Figure 30 Circuit)"
    type: "scope_capture"
    page: 13
  - file: "max17795/figures/max17795-f018.png"
    caption: "Figure 16. Output Voltage vs. Load Current (Figure 33 Circuit)"
    type: "characteristic_curve"
    page: 13
  - file: "max17795/figures/max17795-f019.png"
    caption: "Figure 18. Steady-State Switching Waveform (Figure 30 Circuit)"
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    page: 13
  - file: "max17795/figures/max17795-f020.png"
    caption: "Figure 20. Steady-State Switching Waveform (Figure 30 Circuit)"
    type: "scope_capture"
    page: 13
  - file: "max17795/figures/max17795-f021.png"
    caption: "Figure 21. External Clock Synchronization (Figure 30 Circuit)"
    type: "scope_capture"
    page: 14
  - file: "max17795/figures/max17795-f022.png"
    caption: "Figure 23. Load Current Stepped from 10mA to 2A (Figure 30 Circuit)"
    type: "scope_capture"
    page: 14
  - file: "max17795/figures/max17795-f023.png"
    caption: "Figure 25. Gain/Phase vs. Frequency (Figure 30 Circuit)"
    type: "characteristic_curve"
    page: 14
  - file: "max17795/figures/max17795-f024.png"
    caption: "Figure 22. Load Current Stepped from 10mA to 2A (Figure 30 Circuit)"
    type: "scope_capture"
    page: 14
  - file: "max17795/figures/max17795-f025.png"
    caption: "Figure 24. Load Current Stepped from 3A to 5A (Figure 30 Circuit)"
    type: "scope_capture"
    page: 14
  - file: "max17795/figures/max17795-f026.png"
    caption: "Figure 26. Gain/Phase vs. Frequency (Figure 31 Circuit)"
    type: "characteristic_curve"
    page: 14
  - file: "max17795/figures/max17795-f027.png"
    caption: "Figure 27. Output Short (Figure 30 Circuit)"
    type: "scope_capture"
    page: 15
  - file: "max17795/figures/max17795-f028.png"
    caption: "Figure 28. CISPR32-Radiated Emission"
    type: "characteristic_curve"
    page: 15
  - file: "max17795/figures/max17795-f029.png"
    caption: "Figure 29. CISPR32-Conducted Emission"
    type: "characteristic_curve"
    page: 15
  - file: "max17795/figures/max17795-f030.png"
    caption: "Figure 30. Setting the Input Undervoltage Lockout"
    type: "application_circuit"
    page: 22
  - file: "max17795/figures/max17795-f031.png"
    caption: "Figure 31. Setting the Output Voltage"
    type: "application_circuit"
    page: 23
  - file: "max17795/figures/max17795-f032.png"
    caption: "Figure 32. 5V Output with 400kHz Switching Frequency"
    type: "application_circuit"
    page: 25
  - file: "max17795/figures/max17795-f033.png"
    caption: "Figure 33. 3.3V Output with 375kHz Switching Frequency"
    type: "application_circuit"
    page: 25
  - file: "max17795/figures/max17795-f034.png"
    caption: "Figure 34. 12V Output with 400kHz Switching Frequency"
    type: "application_circuit"
    page: 26
  - file: "max17795/figures/max17795-f035.png"
    caption: "Figure 35. 5V Output with 1.5MHz Switching Frequency"
    type: "application_circuit"
    page: 26
  - file: "max17795/figures/max17795-f036.png"
    caption: ""
    type: "layout_drawing"
    page: 28
  - file: "max17795/figures/max17795-f037.png"
    caption: "PACKAGE LAND PATTERN [F184A4F+1] FC2QFN"
    type: "layout_drawing"
    page: 29
  - file: "max17795/figures/max17795-eq01.png"
    caption: "Equation as printed (p. 17)"
    type: equation
    page: 17
  - file: "max17795/figures/max17795-eq02.png"
    caption: "Equation as printed (p. 17)"
    type: equation
    page: 17
  - file: "max17795/figures/max17795-eq03.png"
    caption: "Equation as printed (p. 18)"
    type: equation
    page: 18
  - file: "max17795/figures/max17795-eq04.png"
    caption: "Equation as printed (p. 18)"
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    page: 18
  - file: "max17795/figures/max17795-eq05.png"
    caption: "Equation as printed (p. 18)"
    type: equation
    page: 18
  - file: "max17795/figures/max17795-eq06.png"
    caption: "Equation as printed (p. 19)"
    type: equation
    page: 19
  - file: "max17795/figures/max17795-eq07.png"
    caption: "Equation as printed (p. 20)"
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  - file: "max17795/figures/max17795-eq08.png"
    caption: "Equation as printed (p. 20)"
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    page: 20
  - file: "max17795/figures/max17795-eq09.png"
    caption: "Equation as printed (p. 20)"
    type: equation
    page: 20
  - file: "max17795/figures/max17795-eq10.png"
    caption: "Equation as printed (p. 20)"
    type: equation
    page: 20
  - file: "max17795/figures/max17795-eq11.png"
    caption: "Equation as printed (p. 21)"
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    page: 21
  - file: "max17795/figures/max17795-eq12.png"
    caption: "Equation as printed (p. 21)"
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    page: 21
  - file: "max17795/figures/max17795-eq13.png"
    caption: "Equation as printed (p. 21)"
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    page: 21
  - file: "max17795/figures/max17795-eq14.png"
    caption: "Equation as printed (p. 21)"
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    page: 21
  - file: "max17795/figures/max17795-eq15.png"
    caption: "Equation as printed (p. 22)"
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    page: 22
  - file: "max17795/figures/max17795-eq16.png"
    caption: "Equation as printed (p. 22)"
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    page: 22
  - file: "max17795/figures/max17795-eq17.png"
    caption: "Equation as printed (p. 22)"
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  - file: "max17795/figures/max17795-eq18.png"
    caption: "Equation as printed (p. 23)"
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  - file: "max17795/figures/max17795-eq19.png"
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  - file: "max17795/figures/max17795-eq20.png"
    caption: "Equation as printed (p. 23)"
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  - file: "max17795/figures/max17795-eq21.png"
    caption: "Equation as printed (p. 23)"
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  - file: "max17795/figures/max17795-eq22.png"
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agentforge:
  part_number: "MAX17795"
  collection: "okf-r12-batch1"
---

# MAX17795 — 3V to 80V, 5A, High-Efficiency, Synchronous Step-Down DC-DC Converter

*Datasheet: [MAX17795 data sheet (PDF)](https://www.analog.com/media/en/technical-documentation/data-sheets/max17795.pdf)*

ANALOG

DEVICES

### FEATURES

-  Reduces Solution Size and Cost
-  No Schottky -Synchronous Operation
-  Internal Compensation Components
-  All-Ceramic Capacitors, Compact Layout
-  Adjustable Output Range from 0.6V to 90% of VIN
-  300kHz to 1.5MHz Adjustable Frequency with External Clock Synchronization
-  EMI with Symmetrical IN Pins
-  4mm x 4mm 18L-FC2QFN
-  Reduces Power Dissipation
-  Peak Efficiency of 92% (VIN = 48V and VOUT = 5V)
-  Enhanced Light-Load Efficiency with Switching Frequency Modulation (SFM) Mode
-  External Bias Input for Improved Efficiency
-  Die Temperature Monitoring
-  Operates Reliably in Adverse Industrial Environments
-  Built-In Hiccup-Mode Overload Protection
-  Programmable Soft-Start
-  Built-In Output-Voltage Monitoring with RESET /TJ Pin
-  Programmable EN/UVLO Threshold
-  Complies with CISPR32 (EN55032) Class B Conducted and Radiated Emissions
-  High Industrial -40°C to +125°C Ambient Operating Temperature Range/-40°C to +150°C Junction Temperature Range

### SIMPLIFIED APPLICATION DIAGRAM


### GENERAL DESCRIPTION

The MAX17795 is a high-efficiency, high-voltage, synchronous step-down DC-DC converter with integrated  MOSFETs  operating  over  an  input  voltage range  of  3V  to  80V.  The  device  can  deliver  up  to  5A current and generate output voltages ranging from 0.6V up to 90% of V IN .

The device features a MODE/SYNC pin that can be used to program the device in forced pulse-width modulation (PWM) or switching frequency modulation (SFM) modes of operation and to synchronize the internal clock to an external clock. The device offers an enable/input undervoltage  lockout  (EN/UVLO)  pin  to  program  the desired  input  voltage  at  which  the  converter  turns on/off. The device also has a soft-start (SS) pin to reduce inrush currents during startup. In addition, the device features a RESET /TJ pin, which can be used either to monitor the status of output voltage or die temperature. The die temperature monitor allows the user to directly measure the silicon die temperature instead of relying on theoretical estimation, thus enabling robust, reliable power supply design.

### APPLICATIONS

-  Industrial, Avionics and Heavy Equipment
-  Factory and Building Automation
-  Motor Control
-  General Purpose Power Supply


### TABLE OF CONTENTS

- Features
- General Description
- Applications
- Simplified Application Diagram
- Revision History
- Specifications
- Absolute Maximum Ratings
- Pin Configurations and Function Descriptions
- Pin Descriptions
- Functional Diagram
- Typical Performance Characteristics
- Detailed Description
- Mode Selection and External Clock Synchronization (MODE/SYNC)
- PWM Mode Operation
- SFM Mode Operation
- Linear Regulator (INTVCC and EXTVCC)
- Setting the Switching Frequency (RT)
- Operating Input Voltage Range
- Overcurrent Protection (OCP)/Hiccup Mode
- RESET Output and Die Temperature Monitor (RESET/TJ)
- Prebiased Output
- Thermal-Shutdown Protection
- Applications Information
- Input Capacitor Selection
- Inductor Selection
- Output Capacitor Selection
- Soft-Start capacitor selection
- Adjusting Output Voltage
- Power dissipation
- Printed Circuit Board (PCB) Layout Guidelines
- Typical Application Circuits
- Outline Dimensions
- <!-- image -->
- Ordering Guide

### REVISION HISTORY

**Revision History** ([table-00-p3-data.csv](max17795/tables/table-00-p3-data.csv), p. 3)

| REVISION NUMBER | REVISION DATE | DESCRIPTION | PAGES CHANGED |
|---|---|---|---|
| 0 | 11/25 | Initial Release | — |

### SPECIFICATIONS

### Table 1. Electrical Characteristics

(V IN = 24V, V EN/UVLO = 24V, C INTVCC = 2.2µF, V SGND = V PGND = V MODE/SYNC = V EXTVCC = 0V, V FB = 0.64V, LX = SS = RESET /TJ = R RT = Open, V BST to V LX = 1.8V, T A = -40°C to 125°C. Typical values are at T A = +25°C. All voltages are referenced to SGND, unless otherwise noted 1 . )

**Table 1. Electrical Characteristics** ([table-01-p4-spec.csv](max17795/tables/table-01-p4-spec.csv), p. 4)

| PARAMETER | SYMBOL | CONDITIONS | MIN | TYP | MAX | UNITS |
|---|---|---|---|---|---|---|
| **INPUT SUPPLY (IN)** |  |  |  |  |  |  |
| Input Voltage Range | V_IN |  | 3 |  | 80 | V |
| Input Shutdown Current | I_IN-SH | V_EN/UVLO = 0V (Shutdown mode) |  | 4.5 | 14 | µA |
| No Load IN Pin Current (See Figure 32) | I_IN_SFM | MODE/SYNC = Open, V_IN = 48V |  | 31 |  | µA |
| No Load IN Pin Current (See Figure 32) | I_IN_PWM | V_MODE/SYNC = 0V, V_IN = 48V |  | 12.5 |  | mA |
| Input UVLO | V_IN_UVLO_R | V_IN rising | 2.7 | 2.8 | 2.9 | V |
| Input UVLO | V_IN_UVLO_F | V_IN falling | 2.45 | 2.55 | 2.65 | V |
| **ENABLE/UNDERVOLTAGE LOCKOUT (EN/UVLO)** |  |  |  |  |  |  |
| EN/UVLO Threshold | V_ENR | V_EN/UVLO rising | 1.22 | 1.25 | 1.28 | V |
| EN/UVLO Threshold | V_ENF | V_EN/UVLO falling | 1.12 | 1.15 | 1.18 | V |
| EN/UVLO Input Leakage Current | I_EN | V_EN/UVLO = 0V, T_A = +25°C | -100 | 0 | +100 | nA |
| **LINEAR REGULATORS (INTVCC, EXTVCC)** |  |  |  |  |  |  |
| INTVCC Output Voltage Range | V_INTVCC | 3 ≤ V_IN ≤ 80V, I_INTVCC = 1mA | 1.74 | 1.8 | 1.86 | V |
| INTVCC Output Voltage Range | V_INTVCC | V_IN=3V, 1mA ≤ I_INTVCC ≤ 20mA | 1.74 | 1.8 | 1.86 | V |
| INTVCC Output Voltage Range | V_INTVCC | 2.35 ≤ V_EXTVCC ≤ 24V, I_INTVCC = 1mA | 1.74 | 1.8 | 1.86 | V |
| INTVCC Undervoltage Threshold | V_INTVCC_UVR | V_INTVCC rising | 1.61 | 1.64 | 1.69 | V |
| INTVCC Undervoltage Threshold | V_INTVCC_UVF | V_INTVCC falling | 1.545 | 1.58 | 1.625 | V |
| EXTVCC Voltage Range | V_EXTVCC |  | 2.35 |  | 25.5 | V |
| EXTVCC Switchover Threshold | V_EXTVCC_UVR | V_EXTVCC rising | 2.25 | 2.3 | 2.35 | V |
| EXTVCC Switchover Threshold | V_EXTVCC_UVF | V_EXTVCC falling | 2.15 | 2.2 | 2.25 | V |
| **HIGH-SIDE AND LOW-SIDE MOSFETS** |  |  |  |  |  |  |
| High-Side nMOS On-Resistance | R_DS-ONH | I_LX = 1A, sourcing |  | 80 | 150 | mΩ |
| Low-Side nMOS On-Resistance | R_DS-ONL | I_LX = 1A, sinking |  | 40 | 80 | mΩ |
| LX Leakage Current | I_LX_LKG | V_IN = 80V, V_LX = (V_PGND +1 )V to (V_IN -1)V, T_A = +25°C, V_EN = 0 | -5 |  | +5 | µA |
| **SOFT-START (SS)** |  |  |  |  |  |  |
| **SOFT-START (SS)** |  |  |  |  |  |  |
| Charging Current | I_SS | V_SS = 0.3V | 4.6 | 5 | 5.35 | µA |
| **FEEDBACK (FB)** |  |  |  |  |  |  |
| **FEEDBACK (FB)** |  |  |  |  |  |  |
| FB Regulation Voltage | V_FB-REG |  | 0.592 | 0.598 | 0.604 | V |
| FB Input Bias Current | I_FB | V_FB = 1V, T_A = +25°C | -50 |  | +50 | nA |
| MODE SELECTION AND EXTERNAL CLOCK SYNCHRONIZATION (MODE/SYNC) |  |  |  |  |  |  |
| MODE Threshold | V_M-SFM | SFM Mode | 1.3 |  |  | V |
| MODE Threshold | V_M-PWM | PWM Mode |  |  | 0.5 | V |
| SYNC Frequency Capture Range | f_SYNC | f_SW set by R_RT² | 1.1 x f_SW |  | 1.4 x f_SW | kHz |
| SYNC High Pulse Width | t_SYNC_H |  | 100 |  |  | ns |
| SYNC Low Pulse Width | t_SYNC_L |  | 100 |  |  | ns |
| SYNC Threshold | V_IH |  | 1.3 |  |  | V |
| SYNC Threshold | V_IL |  |  |  | 0.5 | V |
| **CURRENT LIMIT** |  |  |  |  |  |  |
| **CURRENT LIMIT** |  |  |  |  |  |  |
| Peak Current-Limit Threshold | I_PEAK-LIMIT |  | 6.25 | 7.1 | 7.95 | A |
| Valley Current-Limit Threshold | I_VALLEY-LIMIT | SFM Mode | 0 | 70 | 200 | mA |
| Valley Current-Limit Threshold | I_VALLEY-LIMIT | PWM Mode | -2.4 | -3 | -3.45 | A |
| **SWITCHING FREQUENCY (RT)** |  |  |  |  |  |  |
| **SWITCHING FREQUENCY (RT)** |  |  |  |  |  |  |
| Switching Frequency | f_SW | R_RT = 102kΩ | 280 | 300 | 320 | kHz |
| Switching Frequency | f_SW | R_RT = 16.9kΩ | 1330 | 1450 | 1570 | kHz |
| Switching Frequency | f_SW | R_RT = Open | 370 | 400 | 430 | kHz |
| V_FB Hiccup Threshold | V_FB-HICF | V_FB falling | 0.35 | 0.36 | 0.37 | V |
| Hiccup Timeout |  |  |  | 130 |  | ms |
| Minimum On-Time | t_ON-MIN |  |  | 80 | 110 | ns |
| Minimum Off-Time | t_OFF-MIN |  |  | 130 | 150 | ns |
| LX Dead Time | LX_DT |  |  | 3 |  | ns |
| OUTPUT VOLTAGE MONITOR AND DIE TEMPERATURE MONITOR (R̅E̅S̅E̅T̅/TJ) |  |  |  |  |  |  |
| R̅E̅S̅E̅T̅ Output Level Low | V_R̅E̅S̅E̅T̅L | I_R̅E̅S̅E̅T̅ = 10mA |  |  | 0.6 | V |
| R̅E̅S̅E̅T̅ Output leakage Current | I_R̅E̅S̅E̅T̅LKG | T_A = T_J = 25°C V_R̅E̅S̅E̅T̅ = 5V | -50 |  | 50 | nA |
| FB Threshold for R̅E̅S̅E̅T̅ Deassertion | V_FB-OKR | V_FB Rising | 93.3 | 95 | 96.7 | % |
| FB Threshold for R̅E̅S̅E̅T̅ Assertion | V_FB-OKF | V_FB Falling | 90 | 91.7 | 93.3 | % |
| R̅E̅S̅E̅T̅ Delay after FB Reaches V_FB-OKR |  |  |  | 2 |  | ms |
| R̅E̅S̅E̅T̅/TJ Pin Voltage | V_T25 | T_A = +25°C; R̅E̅S̅E̅T̅/TJ = 20kΩ connected to SGND | 580 | 595 | 610 | mV |
| R̅E̅S̅E̅T̅/TJ Pin Voltage Variation with respect to Die Temperature | dV_TJ/dt | 25°C to 125°C |  | 2 |  | mV/°C |
| **THERMAL SHUTDOWN (TEMPERATURE)** |  |  |  |  |  |  |
| **THERMAL SHUTDOWN (TEMPERATURE)** |  |  |  |  |  |  |
| Thermal Shutdown Threshold |  | Temperature rising |  | 165 |  | °C |
| Thermal Shutdown Hysteresis |  |  |  | 20 |  | °C |

- **Note 1:** Electrical specifications are production tested at T<sub>A</sub> = +25°C. Specifications over the entire operating temperature range are guaranteed by design and characterization.
- **Note 2:** The maximum allowable external clock frequency is 1.5MHz.

### ABSOLUTE MAXIMUM RATINGS

### Table 2. Absolute Maximum Ratings

**Table 2. Absolute Maximum Ratings** ([table-02-p8-abs_max.csv](max17795/tables/table-02-p8-abs_max.csv), p. 8)

| PARAMETER | RATING |
|---|---|
| IN to PGND | -0.3V to +85V |
| EN/UVLO to SGND | -0.3 to (V_IN + 0.3V) |
| LX to PGND | -0.3V to (V_IN + 0.3V) |
| EXTVCC to SGND | -14V to +26.5V |
| BST to PGND | -0.3V to +87V |
| BST to LX | -0.3V to +2.2V |
| BST to INTVCC | -0.3V to +85V |
| FB, SS, INTVCC, RT to SGND | -0.3V to +2.2V |
| R̅E̅S̅E̅T̅/TJ, MODE/SYNC, to SGND | -0.3V to +6V |
| PGND to SGND | -0.3V to +0.3V |
| LX Total RMS Current | 7A |
| Output Short-Circuit Duration | Continuous |
| Continuous Power Dissipation (Multilayer Board) (T_A = +70°C· derate 52.6mW/°C above +70°C) | 4210mW |
| Operating Temperature Range1 | -40°C to 125°C |
| Junction Temperature | +150°C |
| Storage Temperature Range | -65°C to +150°C |
| Lead Temperature (soldering, 10s) | +300°C |
| Soldering Temperature (reflow) | +260°C |

- **Note 1:** Junction temperature greater than +125°C degrades operating lifetimes.

### PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS


### PIN DESCRIPTIONS

**Pin Descriptions** ([table-03-p9-pin.csv](max17795/tables/table-03-p9-pin.csv), p. 9)

| NUMBER | NAME | TYPE | DESCRIPTION |
|---|---|---|---|
| 1 | BST |  | Boot Strap Capacitor Pin. Connect a 0.1µF ceramic capacitor between BST and LX (Pin 2). |
| 2, 6 | LX |  | Switching Node Pins. Connect LX (Pin 2) to the one end of the bootstrap capacitor. Connect LX (Pin 6) to the switching side of the inductor. |
| 3, 9 | IN |  | Power Supply Input Pins. The MAX17795 requires two 0.1µF input bypass capacitors. One 0.1µF capacitor should be placed between IN (Pin 3) and PGND (Pin 4, 5). A second 0.1µF capacitor should be placed between IN (Pin 9) and PGND (Pin 7, 8). These capacitors must be placed as close as possible to the MAX17795. The input capacitor (3 x 4.7µF or more) should be placed close to the MAX17795 across the input power traces. Connect the IN pins (3, 9) to EP using a plane. Refer to the MAX17795 evaluation board user guide for a layout example. |
| 4, 5, 7, 8 | PGND |  | Power Ground Pins. Connect PGND pins to the power ground plane. Refer to the MAX17795 evaluation board user guide for a layout example. |
| 10 | EN/UVLO |  | Enable/Undervoltage Lockout Pin. Drive the EN/UVLO pin high to enable the device. Connect to the center of the resistor-divider between IN and SGND pins to set the input voltage at which the part turns on. Pull low to disable the device. |
| 11 | EXTVCC |  | External Bias Input for EXT-LDO. Connect the EXTVCC pin to the converter output voltage node for output voltages ranging from 2.5V to 24V for improved efficiency. Connect the EXTVCC pin to the SGND pin when the EXTVCC feature is not used. |
| 12 | FB |  | Feedback Input Pin. Connect the FB pin to the center node of an external resistor divider from the output to the SGND pin to set the output voltage. |
| 13 | RT |  | Switching Frequency Programming Input Pin. Connect a resistor from RT to SGND pins to set the converter switching frequency between 300kHz and 1.5MHz. Leave the RT pin open for the default 400kHz frequency. |
| 14 | SS |  | Soft-Start Input Pin. Connect a capacitor from SS to SGND pins to set the soft-start time. |
| 15 | MODE/SYNC |  | Mode Selection Input/ External Clock Synchronization Input Pin. MODE/SYNC pin configures the device to operate in PWM or SFM modes of operation. Connect MODE/SYNC to SGND for constant-frequency PWM operation at all loads. Leave the MODE/SYNC pin open for SFM operation at light loads. The MODE/SYNC pin can also be used to synchronize the converter to an external clock. |
| 16 | R̅E̅S̅E̅T̅/TJ |  | Open-Drain Status Output/ Die Temperature Monitor Output Pin. This pin can be used to monitor either the status of the output voltage or the die temperature. The two functions cannot be used at the same time. Output voltage status can be monitored by connecting the R̅E̅S̅E̅T̅/TJ pin to a power supply through a pull-up resistor. The R̅E̅S̅E̅T̅/TJ output is driven low if FB node voltage drops below 92% of its set value. R̅E̅S̅E̅T̅/TJ goes high 2ms after FB rises above 95% of its set value. Die temperature can be monitored by connecting a 20kΩ resistor from the R̅E̅S̅E̅T̅/TJ pin to SGND. |
| 17 | SGND |  | Signal Ground. |
| 18 | INTVCC |  | 1.8V Linear Regulator Output Pin. Connect a minimum of 2.2µF ceramic capacitor between INTVCC and SGND. The linear regulator does not support the external loading on the INTVCC pin. |
| — | EP |  | Exposed pad, internally connected to IN Pins (3, 9). Always connect EP to the IN pins on the PCB using a plane. Refer to the MAX17795 evaluation board user guide for a layout example. |

### FUNCTIONAL DIAGRAM


### TYPICAL PERFORMANCE CHARACTERISTICS

(V IN = V EN/UV = 48V, C INTVCC = 2.2µF, V SGND = V PND = 0V, V EXTVCC = V OUT , C SS = 8.2nF, C BST = 0.1µF, T A = +25°C, unless otherwise noted.)

(V IN = V EN/UV = 48V, C INTVCC = 2.2µF, V SGND = V PND = 0V, V EXTVCC = V OUT , C SS = 8.2nF, C BST = 0.1µF, T A = +25°C, unless otherwise noted.)

(V IN = V EN/UV = 48V, C INTVCC = 2.2µF, V SGND = V PND = 0V, V EXTVCC = V OUT , C SS = 8.2nF, C BST = 0.1µF, T A = +25°C, unless otherwise noted.)

(V IN = V EN/UV = 48V, C INTVCC = 2.2µF, V SGND = V PND = 0V, V EXTVCC = V OUT , C SS = 8.2nF, C BST = 0.1µF, T A = +25°C, unless otherwise noted.)


### DETAILED DESCRIPTION

The MAX17795 is a high-efficiency, high-voltage, synchronous step-down DC-DC converter with integrated MOSFETs operating over an input voltage range of 3V to 80V. The device can deliver up to 5A current and generate output voltages ranging from 0.6V up to 90% of V IN . Built-in compensation across the output-voltage range eliminates the need for external compensation components. The feedback-voltage regulation accuracy is ±1% over -40°C to +125°C junction temperature range.

The  device  features  a  peak-current-mode  control  architecture.  An  internal  transconductance  error  amplifier produces an integrated error voltage at an internal node, which sets the duty cycle using a PWM comparator, a highside current-sense amplifier, and a slope-compensation generator. At each rising edge of the clock, the high-side MOSFET turns on and remains on until the appropriate or maximum duty cycle is reached or the peak current limit is detected. During the highside MOSFET's on -time, the inductor current ramps up and stores energy in the inductor, and also provides current to the output. During the rest of the switching cycle, the high-side MOSFET turns off, and the low-side MOSFET turns on. The inductor releases the stored energy as its current ramps down and provides current to the output.

The device features a MODE/SYNC pin that can be used to program the device in forced pulse-width modulation (PWM) or switching frequency modulation (SFM) modes of operation and to synchronize the internal clock to an external clock. The device offers an enable/input undervoltage lockout (EN/UVLO) pin to program the desired input voltage at which the converter turns on/off. The device also has a soft-start (SS) pin to reduce inrush currents during startup. In addition, the device features a RESET /TJ pin, which can be used either to monitor the status of output voltage  or  die  temperature.  The  die  temperature  monitor  allows  the  user  to  directly  measure  the  silicon  die temperature instead of relying on theoretical estimation, thus enabling robust, reliable power supply design. The device offers low minimum on-time and low minimum off-time allowing the converter to operate with a wider input voltage range for a given switching frequency.

### Mode Selection and External Clock Synchronization (MODE/SYNC)

The MAX17795 supports PWM and SFM modes of operation. The device enters the programmed mode of operation based on the setting of the MODE/SYNC pin. If the MODE/SYNC pin is low (< 0.5V), the device operates in a constantfrequency PWM mode at all loads. If the MODE/SYNC pin is left open (> 1.3V), the device operates in SFM mode at light loads. The device also supports on-the-fly mode change among PWM and SFM modes. When there is a state transition on the MODE/SYNC pin, the device waits for a period of 40µs (typ) and transitions into the mode based on the MODE/SYNC pin voltage at the end of 40µs (typ) period.

The MODE/SYNC pin can be used to synchronize the internal oscillator of the device to an external clock in all three modes  of  operation.  The  external  clock  frequency  must  be  between  1.1  x  fSW  and  1.4  x  fSW,  where  fSW  is  the programmed switching frequency. When an external clock is applied to the MODE/SYNC pin, if eight or more external clock rising edges are detected in a period of 40µs (typ), the device operates in PWM mode only and the internal oscillator frequency changes to the external clock frequency at the end of the 40µs (typ) period. When the external clock is removed, the device continues to operate in PWM mode for a period of 40µs (typ) with the frequency set by RT and enters a mode based on the MODE/SYNC pin status. The external clock logic high and low pulse widths should be more than 100ns.

### PWM Mode Operation

In PWM mode, the inductor current is allowed to go negative. PWM operation provides constant frequency operation at all loads and is useful in applications sensitive to switching frequency. However, the PWM mode of operation gives lower efficiency at light loads compared to the SFM mode of operation.

### SFM Mode Operation

In SFM mode, the inductor current is discontinuous at light loads. SFM mode provides reduced frequency operation at light loads and allows the device to hibernate, enabling higher efficiency.

At light loads, the inductor peak current is forced to the SFM peak current (I PK-SFM ) by turning on the high-side MOSFET. After the inductor current reaches I PK-SFM , the high-side MOSFET is turned off, and the low-side MOSFET is turned on.

The low-side MOSFET is turned off when the inductor current reaches zero, and the device enters a high-impedance state. Consequently, the output voltage rises above the set voltage. The next switching cycle is initiated when the output voltage falls to the set voltage. As a result, the switching frequency decreases linearly as the load current reduces.

The device enters SFM mode when the inductor peak current demanded by the load is less than I PK-SFM ,  and the inductor  valley  current  reaches  zero  for  32  consecutive  switching  cycles.  The  device  exits  SFM  mode  when  the inductor peak current demanded by the load exceeds I PK-SFM .

For a programmed switching frequency (f SW )  and  the  inductance per the formula given in the Inductor Selection section, at any given input voltage (V IN ), the SFM peak current (I PK-SFM ) is calculated as follows:

![Equation as printed (p. 17)](max17795/figures/max17795-eq01.png)

$$I_{PK \text{-SFM}} \cong 1.86 - 2.22 \times \left( \frac{V_{\text{OUT}}}{V_{\text{IN}}} \right) - 0.34 \times \left( \frac{V_{\text{OUT}}}{V_{\text{IN}}} \right)^{2} + 0.3 \times f_{SW}$$

*LaTeX transcription of the equation above, checked against the symbols printed on the page.*

where:

VOUT = Output voltage (V), fSW is in MHz.

For load currents less than half of I PK-SFM , the output voltage ripple in SFM mode ( Δ VOUT-RIPPLE ) is calculated as follows:

![Equation as printed (p. 17)](max17795/figures/max17795-eq02.png)

$$\Delta V_{OUT \cdot RIPPLE} = \frac{1}{2} \times \frac{L_{SEL} \times ( I_{PK \cdot SFM} - I_{OUT} )^{2}}{C_{OUT \, SEL}} \times \left( \frac{1}{V_{IN} - V_{OUT}} + \frac{1}{V_{OUT}} \right)$$

*LaTeX transcription of the equation above, checked against the symbols printed on the page.*

where:

I OUT = Load current (A),

COUT\_SEL = Selected output capacitance (F) (calculated in the Output Capacitor Selection section),

LSEL = Selected inductance (H) (calculated in the Inductor Selection section).

In SFM mode, when the device stays in a high-impedance state in each switching cycle for more than 7.5µs, in eight consecutive switching cycles, the device enters hibernate mode from the subsequent switching cycle. In hibernate mode, whenever the device enters a high-impedance state between two MOSFET switching cycles, most of the internal blocks are turned off to minimize quiescent current. When the hibernate period reduces below 6.5µs, the device exits hibernate mode.

SFM mode offers better efficiency compared to PWM mode at light load conditions. However, the output-voltage ripple is higher than PWM mode due to reduced switching frequency at light loads. The output capacitance may be adjusted to achieve a desired steady-state output voltage ripple.

### Linear Regulator (INTVCC and EXTVCC)

The MAX17795 has two internal low-dropout linear regulators, IN-LDO and EXT-LDO, that powers INTVCC. IN-LDO is powered from the IN pin, and EXT-LDO is powered from the EXTVCC pin. IN-LDO is enabled during V IN power-up or EN/UVLO power-up. Only one of these two linear regulators operates depending on the voltage at the EXTVCC pin. During power-up, the switchover from IN-LDO to EXT-LDO occurs at the end of the programmed soft-start time if the EXTVCC pin voltage is greater than 2.3V (V EXTVCC\_UVR ). Powering INTVCC from EXT-LDO reduces on-chip dissipation and

### where:

The MAX17795 starts switching only when the voltage at INTVCC is greater than 1.64V (V INTVCC-UVR ). The device employs an undervoltage lockout circuit that forces the converter off when the INTVCC voltage falls below 1.58V (V INTVCC\_UVF ). The hysteresis of 65mV prevents chattering on power-up/power-down.

In applications where the converter output is connected to the EXTVCC pin, if the output is shorted to ground, the transfer  from  EXT-LDO  to  IN-LDO  happens  seamlessly  without  impacting  the  normal  functionality.  Connect  the EXTVCC pin to SGND when not in use.

### Setting the Switching Frequency (RT)

The switching frequency of the device can be programmed from 300kHz to 1.5MHz by using a resistor connected from the RT pin to SGND. The switching frequency (f SW ) is related to the resistor (R RT ) connected at the RT pin by the following equation:

![Equation as printed (p. 18)](max17795/figures/max17795-eq03.png)

$$R_{RT} \cong \frac{31914}{f_{sw}} - 4.36$$

*LaTeX transcription of the equation above, checked against the symbols printed on the page.*

where RRT is in k Ω and f SW is in kHz. Leave the RT pin open for a default switching frequency of 400kHz. See Table 3 for R RT resistor values for a few common switching frequencies.

**Table 3. Switching Frequency vs. RRT Resistor** ([table-04-p18-data.csv](max17795/tables/table-04-p18-data.csv), p. 18)

| SWITCHING FREQUENCY (kHz) | RRT RESISTOR (kΩ) |
|---|---|
| 400 | Open |
| 300 | 102 |
| 400 | 75 |
| 1500 | 16.9 |

### Operating Input Voltage Range

The minimum and maximum operating input voltages for a given output voltage setting should be calculated as follows:

![Equation as printed (p. 18)](max17795/figures/max17795-eq04.png)

$$V_{\text{IN} ( \min )} = \frac{V_{\text{OUT}} + I_{\text{OUT} ( \max )} \times \left( R_{\text{DCR} ( \max )} + R_{\text{DS-ONL} ( \max )} \right)}{1 {\text{f-sw} ( \max )} \times t_{\text{OFF-MIN} ( \max )}} + I_{\text{OUT} ( \max )} \times \left( R_{\text{DS-ONH} ( \max )} - R_{\text{DS-ONL} ( \max )} \right)$$

*LaTeX transcription of the equation above, checked against the symbols printed on the page.*

![Equation as printed (p. 18)](max17795/figures/max17795-eq05.png)

$$V_{IN ( MAX )} = \frac{V_{OUT}}{f_{SW ( MAX )} \times t_{ON \text{-MIN} ( MAX )}}$$

*LaTeX transcription of the equation above, checked against the symbols printed on the page.*

VOUT = Output voltage (V),

I OUT(MAX) = Maximum load current (A),

RDCR(MAX) = Worstcase DC resistance (Ω) of the inductor,

f SW(MAX) = Worst-case switching frequency (Hz),

t OFF-MIN(MAX) = Worst-case minimum switch off-time (s),

t ON-MIN(MAX) = Worst-case minimum switch on-time (s),

RDS-ONL(MAX) and R DS-ONH(MAX) = Worst-case onstate resistances (Ω) of low -side and high-side internal MOSFETs, respectively.

increases efficiency at higher input voltages. Connect the EXTVCC pin to the converter output voltage node for output voltages ranging from 2.5V to 24V for improved efficiency. The typical INTVCC output voltage is 1.8V. Bypass INTVCC to SGND with a 2.2 µF low-ESR ceramic capacitor. INTVCC powers the internal blocks, the low-side MOSFET driver and recharges the external bootstrap capacitor.

### Overcurrent Protection (OCP)/Hiccup Mode

The MAX17795 provides a robust overcurrent protection (OCP) scheme that protects the device under overload and output short-circuit conditions. The OCP scheme protects the device by using a hysteretic control of the inductor current  that  avoids  the  inductor  current  run-away  condition.  In  hysteretic  control,  whenever  the  inductor  peak current exceeds an internal peak current limit of 7.1A (I PEAK-LIMIT ), the high-side MOSFET is turned off, and the low-side MOSFET is turned on. When the inductor current reduces by 3.3A, the low-side MOSFET is turned off, and the highside MOSFET is turned on. In addition, if the FB node voltage drops below 0.36V (V FB\_HICF ) due to a fault condition any time after soft-start is completed, hiccup mode is activated.

In hiccup mode, the converter is protected by suspending switching for a hiccup timeout period of 130ms. Once the hiccup  timeout  period  expires,  a  soft-start  is  attempted  again.  Note  that  when  a  soft-start  is  attempted  under overload conditions if the FB node voltage does not exceed 0.41V, the device continues in hysteretic control for the total time duration of the programmed soft-start time and 2ms. The hiccup mode of operation ensures low power dissipation under output short-circuit conditions.

The  device  provides  a  valley  current  protection  scheme  that  protects  itself  in  PWM  mode  from  large  negative currents. Under strong external output bias conditions, when the inductor valley current falls below -3A (I VALLEY-LIMIT ), the device enters a high-impedance state where both the MOSFETs are turned off and the inductor current reaches 0A. The device recovers from a high-impedance state and starts switching when the output voltage falls below the regulation point when the external output bias is removed.

### RESET Output and Die Temperature Monitor ( RESET /TJ)

The MAX17795 offers a RESET /TJ pin that can be used to monitor either the status of the output voltage or the die temperature. The two functions cannot be used at the same time.

To monitor the status of the converter output voltage, the open-drain RESET /TJ output requires an external pullup resistor to a bias supply voltage. During startup, RESET /TJ goes high (high impedance) with a delay of 2ms after the feedback voltage (V FB )  increases above 95% (V FB-OKR ). RESET /TJ is pulled low when V FB drops below 92% (V FB-OKF ). RESET /TJ is also pulled low during thermal shutdown or when the EN/UVLO pin goes below 1.15V (V ENF ).

To monitor the die temperature, connect a 20k Ω resistor from RESET /TJ to SGND. The die temperature monitor feature is functional only when the output voltage is above 95% (V FB-OKR ) of its set point. During fault conditions like thermal shutdown, VIN UVLO, and VCC UVLO, this pin is pulled low and die temperature monitoring is not supported. Die temperature monitoring is also not supported during hibernation in SFM mode.

The die temperature (T J ) in °C is calculated as follows:

![Equation as printed (p. 19)](max17795/figures/max17795-eq06.png)

$$T_{J} = \frac{( V_{TJ} \cdot V_{T 25} )}{( 2 \times 10^{-3} )} + 25$$

*LaTeX transcription of the equation above, checked against the symbols printed on the page.*

where V TJ is the RESET /TJ pin voltage in V when the converter is loaded.

### Prebiased Output

When the MAX17795 starts into a prebiased output, the high-side and the low-side switches remain turned off so that the converter does not sink current from the output. The switching of the MOSFETs commences only after the voltage at the SS pin (V SS ) crosses the voltage at the feedback pin (V FB ). V FB then smoothly ramps up to V FB-REG in alignment with the V SS , and the output voltage reaches its target value.

### Thermal-Shutdown Protection

The MAX17795 offers internal thermal shutdown protection to limit the junction temperature. When the junction temperature of the device exceeds +165°C, an on-chip thermal sensor shuts down the device, allowing the device to cool down. The device turns on with soft-start after the junction temperature cools down by 20°C. Carefully evaluate the total power dissipation (see the Power Dissipation section) to avoid unwanted triggering of the thermal shutdown in normal operation.

### APPLICATIONS INFORMATION

### Input Capacitor Selection

The input filter capacitor reduces peak currents drawn from the power source, reducing noise and voltage ripple on the  input  caused  by  the  circuit's  switching.  The  following  equation  defines  the  input  capacitor  RMS  current requirement (I RMS ):

![Equation as printed (p. 20)](max17795/figures/max17795-eq07.png)

$$I_{RMS} = I_{OUT(MAX)} \times \frac{\sqrt{(V_{IN} - V_{OUT}) \times V_{OUT}}}{V_{IN}}$$

*LaTeX transcription of the equation above, checked against the symbols printed on the page.*

where I OUT(MAX) is the maximum load current,

I RMS has a maximum value when the input voltage equals twice the output voltage (V IN = 2 x V OUT ), so

![Equation as printed (p. 20)](max17795/figures/max17795-eq08.png)

$$I_{RMS(MAX)} = \frac{I_{OUT(MAX)}}{2}$$

*LaTeX transcription of the equation above, checked against the symbols printed on the page.*

Choose an input capacitor that exhibits less than +10°C temperature rise at the RMS input current for optimal longterm reliability. Use low-ESR ceramic capacitors with high-ripple-current capability at the input. X7R capacitors are recommended in industrial applications for their temperature stability. Calculate the input capacitance using the following equation:

![Equation as printed (p. 20)](max17795/figures/max17795-eq09.png)

$$C_{IN} = \frac{I_{OUT ( \max )} \times D \times ( 1 - D )}{\eta \times f_{SW} \times \Delta V_{IN}}$$

*LaTeX transcription of the equation above, checked against the symbols printed on the page.*

where:

D = V OUT /V IN is the duty ratio of the converter,

f SW = the switching frequency,

Δ VIN = the allowable input voltage ripple,

η = the efficiency.

Actual derating of ceramic capacitors with DC-bias voltage must be considered while selecting the input capacitor. Derating curves are available from all major ceramic capacitor manufacturers.

In  applications  where  the  source  is  located  distant  from  the  device  input,  an  appropriate  electrolytic  capacitor should be added in parallel to the ceramic capacitor to provide necessary damping for potential oscillations caused by the inductance of the longer input power path and input ceramic capacitor.

### Inductor Selection

Three  key  inductor  parameters  must  be  specified  for  operation  with  the  device:  inductance  value  (L),  inductor saturation  current  (I SAT )  and  DC  resistance  (R DCR ).  The  switching  frequency  and  output  voltage  determine  the inductance value as follows:

![Equation as printed (p. 20)](max17795/figures/max17795-eq10.png)

$$L = \frac{0.45 \times V_{OUT}}{f_{SW}}$$

*LaTeX transcription of the equation above, checked against the symbols printed on the page.*

where:

I STEP = Load current step,

t RESPONSE = Response time of the controller,

Δ VOUT = Allowable output-voltage deviation,

f C = Target closed-loop crossover frequency,

f SW = Switching frequency.

where  V OUT and f SW are  nominal  values  and  f SW is  in  Hz.  Select  an  inductor  whose  value  is  nearest  to  the  value calculated by the previous formula. Select a low-loss inductor with acceptable dimensions and the lowest possible DC resistance. The saturation current rating (I SAT ) of the inductor must be high enough to ensure that saturation can occur only above  I PEAK\_LIMIT .

X7R ceramic output capacitors are preferred due to their stability over temperature in industrial applications. The output capacitors are usually sized to support a step load of 40% of the maximum output current in the application, so the output-voltage deviation is contained to 3% of the output voltage. The minimum required output capacitance can be calculated as follows:

Select f C to be 1/9th of f SW for the switching frequencies less than or equal to 500kHz. If the switching frequency is more than 500kHz, select f C to be 60kHz.

The minimum required output capacitance required to meet the output voltage ripple specification ( Δ VOUT-RIPPLE ) in SFM mode at a particular load (I O ) is calculated as follows:

![Equation as printed (p. 21)](max17795/figures/max17795-eq11.png)

$$C_{OUT 2} = \frac{1}{2} \times \frac{L_{SEL} \times ( I_{PK \cdot SFM^{-} O} )^{2}}{\Delta V_{OUT \cdot RIPPLE}} \times \left( \frac{1}{V_{IN} \cdot V_{OUT}} + \frac{1}{V_{OUT}} \right)$$

*LaTeX transcription of the equation above, checked against the symbols printed on the page.*

where I O is less than or equal to half of I PK-SFM . See the SFM Mode section for more details on the calculation of I PK-SFM .

Select the output capacitance to be the higher of C OUT1 and C OUT2 . Actual derating of ceramic capacitors with DC bias voltage  must  be  considered  while  selecting  the  output  capacitor.  Derating  curves  are  available  from  all  major ceramic capacitor manufacturers.

### Soft-Start capacitor selection

The MAX17795 implements an adjustable soft-start operation to reduce inrush current. A capacitor connected from the SS pin to SGND programs the soft-start time. The selected output capacitance (C OUT\_SEL ) and the output voltage (V OUT ) determine the minimum required soft-start capacitance (C ss ) as follows:

![Equation as printed (p. 21)](max17795/figures/max17795-eq12.png)

$$C_{ss} \geq 33 \times 10^{-6} \times C_{OUT_{-SEL}} \times V_{OUT}$$

*LaTeX transcription of the equation above, checked against the symbols printed on the page.*

where COUT\_SEL and C ss are in Farad.

The soft-start time (t SS ) is related to the capacitor connected at SS (C SS ) by the following equation:

![Equation as printed (p. 21)](max17795/figures/max17795-eq13.png)

$$t_{SS} = \frac{C_{SS}}{8.33 \times 10^{-6}}$$

*LaTeX transcription of the equation above, checked against the symbols printed on the page.*

### Output Capacitor Selection

![Equation as printed (p. 21)](max17795/figures/max17795-eq14.png)

$$C_{OUT 1} = \frac{1}{2} \times \frac{I_{STEP} \times t_{RESPONSE}}{\Delta V_{OUT}} \\ t_{RESPONSE} \cong \frac{0.35}{f_{C}}$$

*LaTeX transcription of the equation above, checked against the symbols printed on the page.*

where:

f C = Crossover frequency (Hz),

COUT\_SEL = Actual capacitance (F) of selected output capacitor at DC-bias voltage.

Calculate resistor R FB\_BOT (kΩ) connected from the FB pin to SGND as follows:

![Equation as printed (p. 22)](max17795/figures/max17795-eq15.png)

$$R_{FB \, BOT} = \frac{R_{FB \, TOP} \times 0.6}{V_{OUT} - 0.6}$$

*LaTeX transcription of the equation above, checked against the symbols printed on the page.*

Where CSS is in Farad and t SS is in seconds. For example, to program a 1ms soft-start time, an 8.2nF capacitor should be connected from the SS pin to SGND. The MAX17795 offers a minimum programmable soft-start time of 1ms. Note that, during startup, the device operates at a variable switching frequency until the output voltage reaches 95% of the set output nominal voltage.

### Setting the Input Undervoltage-Lockout Level

The MAX17795 offers an adjustable input undervoltage-lockout level. Set the voltage at which the device turns on with a resistive voltage-divider connected from V IN to SGND (see Figure 30 ). Connect the center node of the divider to the EN/UVLO pin. Choose R UVL\_TOP to be 3.3MΩ and then calculate R UVL\_BOTTOM as follows:

![Equation as printed (p. 22)](max17795/figures/max17795-eqx01.png)

$$R_{UVL\_BOTTOM} = \frac{R_{UVL\_TOP} \times V_{ENR}}{V_{INU} - V_{ENR}}$$

*LaTeX transcription of the equation above, checked against the symbols printed on the page.*

![Equation as printed (p. 22)](max17795/figures/max17795-eq16.png)

$$R_{UVL_{-} BOTTOM} = \frac{R_{UVL_{-} TOP} \times V_{ENR}}{V_{INU} - V_{ENR}}$$

*LaTeX transcription of the equation above, checked against the symbols printed on the page.*

where VINU is the voltage at which the device is required to turn on. It is recommended that V INU is higher than 0.8 x VOUT to avoid hiccups during slow power up (slower than soft start) / power down. If the EN/UVLO pin is driven from an external signal source, a series resistance of a minimum 1k Ω is recommended to be placed between the output pin of signal source and the EN/UVLO pin to reduce voltage ringing on the line.

### Adjusting Output Voltage

Set the output voltage with a resistive voltage-divider connected from the output-voltage node (V OUT ) to SGND (see Figure 31 ). Connect the center node of the resistive divider to the FB pin. Use the following procedure to choose the resistive voltage-divider values:

Calculate resistor R FB\_TOP (kΩ) from the output to the FB pin as follows:

![Equation as printed (p. 22)](max17795/figures/max17795-eq17.png)

$$R_{FB\_TOP} = \frac{280}{f_C \times C_{OUT\_SEL}}$$

*LaTeX transcription of the equation above, checked against the symbols printed on the page.*

Add a capacitor (C FF ) across R FB\_TOP when the part is used in SFM mode or when dynamic mode change is used in an application. C FF is not needed when the part is used in PWM mode alone.

Calculate the capacitance (C FF ) value using the following equation:

where RFB\_TOP = top side feedback resistance (kΩ), CFF = feedforward capacitance (pF).  CFF must be chosen to withstand output voltage.

At a particular operating condition, the power losses that lead to temperature rise of the part are estimated as follows:

where:

POUT is the output power (W),

η is the efficiency of the converter,

RDCR is the DC resistance ( Ω ) of the inductor (see the Typical Performance Characteristics for more information on efficiency at typical operating conditions).

The die temperature (T J ) of the device may also be estimated at any given maximum ambient temperature (T AMB ) from the following equation, when the die temperature monitor ( RESET /TJ) feature is not used.

![Equation as printed (p. 23)](max17795/figures/max17795-eq18.png)

$$T_{J} = T_{AMB} + \left( \theta_{JA} \times P_{LOSS} \right)$$

*LaTeX transcription of the equation above, checked against the symbols printed on the page.*

Note: Junction temperatures greater than +125°C degrade operating lifetimes.

### Printed Circuit Board (PCB) Layout Guidelines

All traces carrying pulsed currents must be very short and as wide as possible. The inductance of these traces must be kept to an absolute minimum due to the high di/dt of the currents. Since the inductance of a current-carrying loop is proportional to the area enclosed by the loop, if the loop area is made very small, inductance is reduced. Additionally,  small-current loop areas reduce radiated EMI. When routing the circuitry around the IC, the signal ground (SGND), and the power ground (PGND) for switching currents must be kept separate. PCB layout also affects the thermal performance of the design.

![Equation as printed (p. 23)](max17795/figures/max17795-eq19.png)

$$\frac{550}{R_{FB_{TOP}}} < C_{FF} < \frac{850}{R_{FB_{TOP}}}$$

*LaTeX transcription of the equation above, checked against the symbols printed on the page.*

### Power dissipation

![Equation as printed (p. 23)](max17795/figures/max17795-eq20.png)

$$P_{LOSS} = P_{OUT} \times \left( \frac{1}{\eta}{\cdot} 1 \right) {\,} - \left( I_{OUT}^{2} \times R_{D} \right)$$

*LaTeX transcription of the equation above, checked against the symbols printed on the page.*

![Equation as printed (p. 23)](max17795/figures/max17795-eq21.png)

$$P_{OUT} = V_{OUT} \times I_{OUT}$$

*LaTeX transcription of the equation above, checked against the symbols printed on the page.*

![Equation as printed (p. 23)](max17795/figures/max17795-eq22.png)

-  Place the input capacitors as close to the IN and PGND pins as possible.
-  Connect the INTVCC capacitor close to the INTVCC pin and connect the other terminal to the SGND plane.
-  Place the BST capacitor close to the BST and LX pins.
-  Place the inductor as close as possible to the LX pin. Minimize the length and area of the trace connection from the LX pin to the inductor.
-  Place the output capacitors as close as possible to the non-switching side of the inductor.
-  Place the PGND terminals of the input capacitor and output capacitor as close as possible to the PGND pins and connect them to the PGND plane.
-  Place the RT resistor, SS capacitor, and FB resistors as close as possible to their respective pins. Connect their other terminals to the SGND plane.
-  Keep all the power and load connections short to keep inductances at minimum levels.
-  Connect the PGND and SGND nodes at a point where the switching activity is at its minimum, at the negative terminal of the INTVCC bypass capacitor.
-  Several thermal throughputs (vias) that connect to a large plane should be provided under IN, PGND, and LX pins for efficient heat dissipation.

Refer to the MAX17795 evaluation board user guide for recommended PCB layout and routing.

### TYPICAL APPLICATION CIRCUITS


### OUTLINE DIMENSIONS

**Table 4. Thermal Resistance of 18L FC2QFN** ([table-05-p27-data.csv](max17795/tables/table-05-p27-data.csv), p. 27)

| PARAMETER | RATING |
|---|---|
| **THERMAL RESISTANCE, FOUR-LAYER BOARD (Note 1)** |  |
| **THERMAL RESISTANCE FOUR-LAYER BOARD (Note 1)** |  |
| Junction to Ambient (θ_JA) | 19°C/W |
| Junction-to-Case Thermal Resistance (θ_JC) | 2.02°C/W |

- **Note 1:** Package thermal resistances were obtained using the MAX17795 evaluation kit with no airflow.

For the latest package outline information and land patterns (footprints), refer to package index at www.analog.com. Note that a '+', '#', or ' -' in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.

### Land Pattern

Si n d m n ,n  nn n n  nn   on   d  s This document (including dimensions, notes & specs) is a recommendaton based on typical circuit board manufacturing parameters. determine suitability for use. This document is subject to change without notice.

### ORDERING GUIDE

**Ordering Guide** ([table-06-p30-data.csv](max17795/tables/table-06-p30-data.csv), p. 30)

| PART NUMBER | TEMP RANGE | PIN PACKAGE |
|---|---|---|
| MAX17795AFN+ | -40°C to 125°C | 18-FC2QFN (4mm x 4mm) |
| MAX17795AFN+T | -40°C to 125°C | 18-FC2QFN (4mm x 4mm) |

- +: Denotes a lead (Pb)-free/RoHS-compliant package.
- T: Tape-and-reel.

ALL  INFORMATION  CONTAINED  HEREIN  IS  PROVIDED  'AS  IS'  WITHOUT  REPRESENTATION  OR  WARRANTY.  NO  RESPONSIBILITY  IS ASSUMED BY ANALOG DEVICES FOR ITS USE, NOR FOR ANY INFRINGEMENTS OF PATENTS OR OTHER RIGHTS OF THIRD PARTIES THAT MAY  RESULT  FROM  ITS  USE.  SPECIFICATIONS  ARE  SUBJECT  TO  CHANGE  WITHOUT  NOTICE.  NO  LICENCE,  EITHER  EXPRESSED  OR IMPLIED, IS GRANTED UNDER ANY ADI PATENT RIGHT, COPYRIGHT, MASK WORK RIGHT, OR ANY OTHER ADI INTELLECTUAL PROPERTY RIGHT RELATING TO ANY COMBINATION, MACHINE, OR PROCESS, IN WHICH ADI PRODUCTS OR SERVICES ARE USED. TRADEMARKS AND REGISTERED TRADEMARKS ARE THE PROPERTY OF THEIR RESPECTIVE OWNERS. ALL ANALOG DEVICES PRODUCTS CONTAINED HEREIN ARE SUBJECT TO RELEASE AND AVAILABILITY.

## Additional Figures

![other (p. 1)](max17795/figures/max17795-f000.png)

![Figure 1. Typical Application Circuit](max17795/figures/max17795-f001.png)

*Figure 1. Typical Application Circuit*

![Figure 2. Efficiency vs. load current (Figure 30 Circuit)](max17795/figures/max17795-f002.png)

*Figure 2. Efficiency vs. load current (Figure 30 Circuit)*

![Figure 3. MAX17795 Pin Configuration](max17795/figures/max17795-f003.png)

*Figure 3. MAX17795 Pin Configuration*

![Figure 4. MAX17795 Functional Diagram](max17795/figures/max17795-f004.png)

*Figure 4. MAX17795 Functional Diagram*

![Figure 5. Efficiency vs. Load Current (Figure 30 Circuit)](max17795/figures/max17795-f005.png)

*Figure 5. Efficiency vs. Load Current (Figure 30 Circuit)*

![Figure 8. Efficiency vs. Load Current (Figure 31 Circuit)](max17795/figures/max17795-f006.png)

*Figure 8. Efficiency vs. Load Current (Figure 31 Circuit)*

![Figure 11. Efficiency vs. Load Current (Figure 33 Circuit)](max17795/figures/max17795-f007.png)

*Figure 11. Efficiency vs. Load Current (Figure 33 Circuit)*

![Figure 6. Efficiency vs. Load Current (Figure 30 Circuit)](max17795/figures/max17795-f008.png)

*Figure 6. Efficiency vs. Load Current (Figure 30 Circuit)*

![Figure 7. Efficiency vs. Load Current (Figure 31 Circuit)](max17795/figures/max17795-f009.png)

*Figure 7. Efficiency vs. Load Current (Figure 31 Circuit)*

![Figure 9. Efficiency vs. Load Current (Figure 32 Circuit)](max17795/figures/max17795-f010.png)

*Figure 9. Efficiency vs. Load Current (Figure 32 Circuit)*

![Figure 12. Efficiency vs. Load Current (Figure 33 Circuit)](max17795/figures/max17795-f011.png)

*Figure 12. Efficiency vs. Load Current (Figure 33 Circuit)*

![Figure 10. Efficiency vs. Load Current (Figure 32 Circuit)](max17795/figures/max17795-f012.png)

*Figure 10. Efficiency vs. Load Current (Figure 32 Circuit)*

![Figure 13. Output Voltage vs. Load Current (Figure 30 Circuit)](max17795/figures/max17795-f013.png)

*Figure 13. Output Voltage vs. Load Current (Figure 30 Circuit)*

![Figure 14. Output Voltage vs. Load Current (Figure 31 Circuit)](max17795/figures/max17795-f014.png)

*Figure 14. Output Voltage vs. Load Current (Figure 31 Circuit)*

![Figure 15. Output Voltage vs. Load Current (Figure 32 Circuit)](max17795/figures/max17795-f015.png)

*Figure 15. Output Voltage vs. Load Current (Figure 32 Circuit)*

![Figure 17. Start-up/Shutdown Through EN/UV (Figure 30 Circuit)](max17795/figures/max17795-f016.png)

*Figure 17. Start-up/Shutdown Through EN/UV (Figure 30 Circuit)*

![Figure 19. Steady-State Switching Waveform (Figure 30 Circuit)](max17795/figures/max17795-f017.png)

*Figure 19. Steady-State Switching Waveform (Figure 30 Circuit)*

![Figure 16. Output Voltage vs. Load Current (Figure 33 Circuit)](max17795/figures/max17795-f018.png)

*Figure 16. Output Voltage vs. Load Current (Figure 33 Circuit)*

![Figure 18. Steady-State Switching Waveform (Figure 30 Circuit)](max17795/figures/max17795-f019.png)

*Figure 18. Steady-State Switching Waveform (Figure 30 Circuit)*

![Figure 20. Steady-State Switching Waveform (Figure 30 Circuit)](max17795/figures/max17795-f020.png)

*Figure 20. Steady-State Switching Waveform (Figure 30 Circuit)*

![Figure 21. External Clock Synchronization (Figure 30 Circuit)](max17795/figures/max17795-f021.png)

*Figure 21. External Clock Synchronization (Figure 30 Circuit)*

![Figure 23. Load Current Stepped from 10mA to 2A (Figure 30 Circuit)](max17795/figures/max17795-f022.png)

*Figure 23. Load Current Stepped from 10mA to 2A (Figure 30 Circuit)*

![Figure 25. Gain/Phase vs. Frequency (Figure 30 Circuit)](max17795/figures/max17795-f023.png)

*Figure 25. Gain/Phase vs. Frequency (Figure 30 Circuit)*

![Figure 22. Load Current Stepped from 10mA to 2A (Figure 30 Circuit)](max17795/figures/max17795-f024.png)

*Figure 22. Load Current Stepped from 10mA to 2A (Figure 30 Circuit)*

![Figure 24. Load Current Stepped from 3A to 5A (Figure 30 Circuit)](max17795/figures/max17795-f025.png)

*Figure 24. Load Current Stepped from 3A to 5A (Figure 30 Circuit)*

![Figure 26. Gain/Phase vs. Frequency (Figure 31 Circuit)](max17795/figures/max17795-f026.png)

*Figure 26. Gain/Phase vs. Frequency (Figure 31 Circuit)*

![Figure 27. Output Short (Figure 30 Circuit)](max17795/figures/max17795-f027.png)

*Figure 27. Output Short (Figure 30 Circuit)*

![Figure 28. CISPR32-Radiated Emission](max17795/figures/max17795-f028.png)

*Figure 28. CISPR32-Radiated Emission*

![Figure 29. CISPR32-Conducted Emission](max17795/figures/max17795-f029.png)

*Figure 29. CISPR32-Conducted Emission*

![Figure 30. Setting the Input Undervoltage Lockout](max17795/figures/max17795-f030.png)

*Figure 30. Setting the Input Undervoltage Lockout*

![Figure 31. Setting the Output Voltage](max17795/figures/max17795-f031.png)

*Figure 31. Setting the Output Voltage*

![Figure 32. 5V Output with 400kHz Switching Frequency](max17795/figures/max17795-f032.png)

*Figure 32. 5V Output with 400kHz Switching Frequency*

![Figure 33. 3.3V Output with 375kHz Switching Frequency](max17795/figures/max17795-f033.png)

*Figure 33. 3.3V Output with 375kHz Switching Frequency*

![Figure 34. 12V Output with 400kHz Switching Frequency](max17795/figures/max17795-f034.png)

*Figure 34. 12V Output with 400kHz Switching Frequency*

![Figure 35. 5V Output with 1.5MHz Switching Frequency](max17795/figures/max17795-f035.png)

*Figure 35. 5V Output with 1.5MHz Switching Frequency*

![layout drawing (p. 28)](max17795/figures/max17795-f036.png)

![PACKAGE LAND PATTERN [F184A4F+1) FC2QFN](max17795/figures/max17795-f037.png)

*PACKAGE LAND PATTERN [F184A4F+1] FC2QFN*