---
type: Analog Component
title: "LTC3636 — Dual Channel 6A, 20V Monolithic Synchronous Step-Down Regulator"
description: "Dual Channel 6A, 20V Monolithic Synchronous Step-Down Regulator"
resource: "https://www.analog.com/en/products/ltc3636.html"
tags: ["datasheet", "okf-r12-batch1", "linear"]
generated: { by: "agentforge/aa0b0641", at: "2026-09-29T20:23:52Z" }
status: draft
sources:
- id: "datasheet"
resource: "https://www.analog.com/media/en/technical-documentation/data-sheets/ltc3636-3636-1.pdf"
title: "LTC3636 data sheet"
author: "team:analog-devices"
tables:
- file: "ltc3636/tables/table-00-p2-spec.csv"
title: "Table 1. Electrical Characteristics"
page: 2
- file: "ltc3636/tables/table-01-p5-abs_max.csv"
title: "Table 2. Absolute Maximum Ratings"
page: 5
- file: "ltc3636/tables/table-02-p5-data.csv"
title: "Table 3. LTC3636 28-Lead (4mm × 5mm) Plastic QFN (Electrostatic Discharge Ratings)"
page: 5
- file: "ltc3636/tables/table-03-p6-pin.csv"
title: "Table 4. Pin Descriptions"
page: 6
- file: "ltc3636/tables/table-04-p15-data.csv"
title: "Table 5. Inductor Selection Table"
page: 15
- file: "ltc3636/tables/table-05-p31-data.csv"
title: "Table 6. Ordering Guide"
page: 31
- file: "ltc3636/tables/table-06-p31-data.csv"
title: "Selection Table"
page: 31
- file: "ltc3636/tables/table-07-p32-data.csv"
title: "Revision History"
page: 32
- file: "ltc3636/tables/table-08-p33-data.csv"
title: "Related Parts"
page: 33
figures:
- file: "ltc3636/figures/ltc3636-f038-01.png"
caption: "Figure 34.Design Example Circuit"
type: "layout_drawing"
page: 25
- file: "ltc3636/figures/ltc3636-f038-02.png"
caption: "Figure 35.Recommended PCB Layouts -Example of Power Component Layout for QFN Package"
type: "layout_drawing"
page: 25
- file: "ltc3636/figures/ltc3636-f000.png"
caption: ""
type: "other"
page: 1
- file: "ltc3636/figures/ltc3636-f001.png"
caption: ""
type: "characteristic_curve"
page: 1
- file: "ltc3636/figures/ltc3636-f002.png"
caption: "Figure 1. Efficiency vs Load Current"
type: "other"
page: 1
- file: "ltc3636/figures/ltc3636-f003.png"
caption: "ESD caution symbol"
type: "other"
page: 5
- file: "ltc3636/figures/ltc3636-f004.png"
caption: ""
type: "pinout"
page: 6
- file: "ltc3636/figures/ltc3636-f005.png"
caption: ""
type: "block_diagram"
page: 9
- file: "ltc3636/figures/ltc3636-f006.png"
caption: "Figure 2. Efficiency vs Load Current Burst Mode Operation"
type: "characteristic_curve"
page: 10
- file: "ltc3636/figures/ltc3636-f007.png"
caption: "Figure 5. Efficiency vs Load Current Burst Mode Operation"
type: "characteristic_curve"
page: 10
- file: "ltc3636/figures/ltc3636-f008.png"
caption: "Figure 8. Load Regulation"
type: "characteristic_curve"
page: 10
- file: "ltc3636/figures/ltc3636-f009.png"
caption: "Figure 11.Internal MOSFET RDS(ON) vs Temperature"
type: "characteristic_curve"
page: 10
- file: "ltc3636/figures/ltc3636-f010.png"
caption: "Figure 3. Efficiency vs Load Current Forced Continuous Mode Operation"
type: "characteristic_curve"
page: 10
- file: "ltc3636/figures/ltc3636-f011.png"
caption: "Figure 6. Efficiency vs Input Voltage Burst Mode Operation"
type: "characteristic_curve"
page: 10
- file: "ltc3636/figures/ltc3636-f012.png"
caption: "Figure 9. Oscillator Frequency vs Temperature"
type: "characteristic_curve"
page: 10
- file: "ltc3636/figures/ltc3636-f013.png"
caption: "Figure 12.Temperature Monitor vs Temperature"
type: "characteristic_curve"
page: 10
- file: "ltc3636/figures/ltc3636-f014.png"
caption: "Figure 4. Efficiency vs Load Current"
type: "characteristic_curve"
page: 10
- file: "ltc3636/figures/ltc3636-f015.png"
caption: "Figure 7. Reference Voltage vs Temperature"
type: "characteristic_curve"
page: 10
- file: "ltc3636/figures/ltc3636-f016.png"
caption: "Figure 10.Oscillator Internal Set Frequency vs Temperature"
type: "characteristic_curve"
page: 10
- file: "ltc3636/figures/ltc3636-f017.png"
caption: "Figure 13.Quiescent Current vs VIN Burst Mode Operation"
type: "characteristic_curve"
page: 10
- file: "ltc3636/figures/ltc3636-f018.png"
caption: "Figure 14.Switch Leakage vs Temperature"
type: "characteristic_curve"
page: 11
- file: "ltc3636/figures/ltc3636-f019.png"
caption: "Figure 17.Shutdown Current vs VIN"
type: "characteristic_curve"
page: 11
- file: "ltc3636/figures/ltc3636-f020.png"
caption: "Figure 20.Load Step (Internal Compensation)"
type: "characteristic_curve"
page: 11
- file: "ltc3636/figures/ltc3636-f021.png"
caption: "Figure 23.Start-Up into Prebiased Output (Burst Mode Operation)"
type: "scope_capture"
page: 11
- file: "ltc3636/figures/ltc3636-f022.png"
caption: "Figure 15.Valley Current Limit vs Temperature"
type: "characteristic_curve"
page: 11
- file: "ltc3636/figures/ltc3636-f023.png"
caption: "Figure 18.Burst Mode Operation"
type: "scope_capture"
page: 11
- file: "ltc3636/figures/ltc3636-f024.png"
caption: "Figure 21.Start-Up (Burst Mode Operation)"
type: "scope_capture"
page: 11
- file: "ltc3636/figures/ltc3636-f025.png"
caption: "Figure 24.Start-Up into Prebiased Output (Forced Continuous Mode)"
type: "characteristic_curve"
page: 11
- file: "ltc3636/figures/ltc3636-f026.png"
caption: "Figure 16.TRACKSS Pull-Up Current vs Temperature"
type: "characteristic_curve"
page: 11
- file: "ltc3636/figures/ltc3636-f027.png"
caption: "Figure 19.Load Step"
type: "characteristic_curve"
page: 11
- file: "ltc3636/figures/ltc3636-f028.png"
caption: "Figure 22.Start-Up (Forced Continuous Mode)"
type: "scope_capture"
page: 11
- file: "ltc3636/figures/ltc3636-f029.png"
caption: "Figure 25.Short-Circuit and Soft-Start"
type: "characteristic_curve"
page: 11
- file: "ltc3636/figures/ltc3636-f030.png"
caption: "Figure 26.Switching Frequency vs RT"
type: "characteristic_curve"
page: 13
- file: "ltc3636/figures/ltc3636-f031.png"
caption: "Figure 27.Setting the Output Voltage"
type: "application_circuit"
page: 17
- file: "ltc3636/figures/ltc3636-f032.png"
caption: "Figure 28.Compensation Component"
type: "application_circuit"
page: 18
- file: "ltc3636/figures/ltc3636-f033.png"
caption: "Figure 29.Two Different Modes of Output Voltage Tracking Coincident Tracking"
type: "characteristic_curve"
page: 20
- file: "ltc3636/figures/ltc3636-f034.png"
caption: "Figure 30.Two Different Modes of Output Voltage Tracking Ratiometric Tracking"
type: "characteristic_curve"
page: 20
- file: "ltc3636/figures/ltc3636-f035.png"
caption: "Figure 31.Setup for Coincident and Ratiometric Tracking"
type: "application_circuit"
page: 20
- file: "ltc3636/figures/ltc3636-f036.png"
caption: "Figure 32.PGOOD Pin Behavior"
type: "timing_diagram"
page: 21
- file: "ltc3636/figures/ltc3636-f037.png"
caption: "Figure 33.Temperature Derating Curve for DC2335 Demo Circuit"
type: "thermal"
page: 23
- file: "ltc3636/figures/ltc3636-f039.png"
caption: "Figure 36.Recommended PCB Layouts -Alternative Layout with GNDT Pins Connected to GND"
type: "layout_drawing"
page: 26
- file: "ltc3636/figures/ltc3636-f040.png"
caption: "Figure 37.Recommended PCB Layouts -Alternative Layout with Pins 29 to 34 Unconnected"
type: "layout_drawing"
page: 26
- file: "ltc3636/figures/ltc3636-f043.png"
caption: "Figure 42.12A 1MHz 2-Phase Buck Regulator"
type: "application_circuit"
page: 29
- file: "ltc3636/figures/ltc3636-f044.png"
caption: ""
type: "other"
page: 30
- file: "ltc3636/figures/ltc3636-f045.png"
caption: "RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED"
type: "other"
page: 30
- file: "ltc3636/figures/ltc3636-f046.png"
caption: "Figure 38.1.8V/2.5V 3MHz Buck Regulator"
type: "application_circuit"
page: 27
- file: "ltc3636/figures/ltc3636-f047.png"
caption: "Figure 39.3.3V/1.8V Sequenced Regulator with 8V Input UVLO (VOUT1 Enabled After VOUT2)"
type: "application_circuit"
page: 27
- file: "ltc3636/figures/ltc3636-f048.png"
caption: "Figure 40.1.2V/1.8V Buck Regulator with Coincident Tracking and 6V Input UVLO"
type: "application_circuit"
page: 28
- file: "ltc3636/figures/ltc3636-f049.png"
caption: "Figure 41.Dual Output Regulator from Multiple Input Supplies (Powers VIN1 Before VIN2)"
type: "application_circuit"
page: 28
- file: "ltc3636/figures/ltc3636-eq01.png"
caption: "Equation as printed (p. 13)"
type: equation
page: 13
- file: "ltc3636/figures/ltc3636-eq02.png"
caption: "Equation as printed (p. 14)"
type: equation
page: 14
- file: "ltc3636/figures/ltc3636-eq03.png"
caption: "Equation as printed (p. 14)"
type: equation
page: 14
- file: "ltc3636/figures/ltc3636-eq04.png"
caption: "Equation as printed (p. 15)"
type: equation
page: 15
- file: "ltc3636/figures/ltc3636-eq05.png"
caption: "Equation as printed (p. 16)"
type: equation
page: 16
- file: "ltc3636/figures/ltc3636-eq06.png"
caption: "Equation as printed (p. 16)"
type: equation
page: 16
- file: "ltc3636/figures/ltc3636-eq07.png"
caption: "Equation as printed (p. 17)"
type: equation
page: 17
- file: "ltc3636/figures/ltc3636-eq08.png"
caption: "Equation as printed (p. 17)"
type: equation
page: 17
- file: "ltc3636/figures/ltc3636-eq09.png"
caption: "Equation as printed (p. 17)"
type: equation
page: 17
- file: "ltc3636/figures/ltc3636-eq10.png"
caption: "Equation as printed (p. 18)"
type: equation
page: 18
- file: "ltc3636/figures/ltc3636-eq11.png"
caption: "Equation as printed (p. 20)"
type: equation
page: 20
- file: "ltc3636/figures/ltc3636-eq12.png"
caption: "Equation as printed (p. 21)"
type: equation
page: 21
- file: "ltc3636/figures/ltc3636-eq13.png"
caption: "Equation as printed (p. 21)"
type: equation
page: 21
- file: "ltc3636/figures/ltc3636-eq14.png"
caption: "Equation as printed (p. 21)"
type: equation
page: 21
- file: "ltc3636/figures/ltc3636-eq15.png"
caption: "Equation as printed (p. 22)"
type: equation
page: 22
- file: "ltc3636/figures/ltc3636-eq16.png"
caption: "Equation as printed (p. 22)"
type: equation
page: 22
- file: "ltc3636/figures/ltc3636-eq17.png"
caption: "Equation as printed (p. 22)"
type: equation
page: 22
- file: "ltc3636/figures/ltc3636-eq18.png"
caption: "Equation as printed (p. 22)"
type: equation
page: 22
- file: "ltc3636/figures/ltc3636-eq19.png"
caption: "Equation as printed (p. 22)"
type: equation
page: 22
- file: "ltc3636/figures/ltc3636-eq20.png"
caption: "Equation as printed (p. 23)"
type: equation
page: 23
- file: "ltc3636/figures/ltc3636-eq21.png"
caption: "Equation as printed (p. 24)"
type: equation
page: 24
- file: "ltc3636/figures/ltc3636-eq22.png"
caption: "Equation as printed (p. 24)"
type: equation
page: 24
- file: "ltc3636/figures/ltc3636-eq23.png"
caption: "Equation as printed (p. 24)"
type: equation
page: 24
- file: "ltc3636/figures/ltc3636-eq24.png"
caption: "Equation as printed (p. 24)"
type: equation
page: 24
- file: "ltc3636/figures/ltc3636-eq25.png"
caption: "Equation as printed (p. 24)"
type: equation
page: 24
agentforge:
part_number: "LTC3636"
collection: "okf-r12-batch1"
---
# LTC3636 — Dual Channel 6A, 20V Monolithic Synchronous Step-Down Regulator
*Datasheet: [LTC3636 data sheet (PDF)](https://www.analog.com/media/en/technical-documentation/data-sheets/ltc3636-3636-1.pdf)*
ANALOG
### LTC3636/LTC3636-1
### FEATURES
- Wide VIN Range: 3.1V to 20V
- Wide VOUT Range:
- 0.6V to 5V (LTC3636)
- 1.8V to 12V (LTC3636-1)
- Output Current per Channel: 6A
- High Efficiency: Up to 95%
- Die Temperature Monitor
- Adjustable Switching Frequency: 500kHz to 4MHz
- External Frequency Synchronization
- Current Mode Operation for Excellent Line and Load Transient Response
- 0.6V Reference Allows Low Output Voltages
- User Selectable Burst Mode® Operation or Forced Continuous Operation
- Output Voltage Tracking and Soft-Start Capability
- Short-Circuit Protected
- Overvoltage Input and Overtemperature Protection
- Power Good Status Outputs
- Low Profile 4mm × 5mm 28-Lead QFN Package
- AEC-Q100 Qualified for Automotive Applications
### APPLICATIONS
- Distributed Power Systems
- Battery-Powered Instruments
- Point-of-Load Power Supplies
### TYPICAL APPLICATION
### GENERAL DESCRIPTION
The LTC®3636/LTC3636-1 is a high efficiency, dual channel monolithic synchronous buck regulator using a controlled on-time current mode architecture, with phase lockable switching frequency. The operating supply voltage range is from 3.1V to 20V, making it suitable for lithium-ion battery stacks as well as point of load power supply applications from a 12V or 5V input.
The operating frequency is programmable from 500kHz to 4MHz with an external resistor and may be synchronized to an external clock signal. The high frequency capability allows the use of small surface mount inductors and capacitors. The unique constant frequency/controlled on-time architecture is ideal for high step-down ratio applications that operate at high frequency while demanding fast transient response.
The LTC3636/LTC3636-1 can select between forced continuous mode and high efficiency Burst Mode operation. The LTC3636 and LTC3636-1 differ in their output voltage sense range.
All registered trademarks and trademarks are the property of their respective owners. Protected by U.S. Patents including 5481178, 5847554, 6580258, 6304066, 6476589, 6774611.
### SPECIFICATIONS
### Table 1. Electrical Characteristics
(Specifications are at T J = 25°C ( 2 ). V IN1 = V IN2 = 12V unless otherwise noted.)
**Table 1. Electrical Characteristics** ([table-00-p2-spec.csv](ltc3636/tables/table-00-p2-spec.csv), p. 2)
| PARAMETER | SYMBOL | CONDITIONS | COMMENTS | MIN | TYP | MAX | UNITS |
|---|---|---|---|---|---|---|---|
| Supply Range | V_IN1 | | -40°C ≤ T_J ≤ 150°C | 3.1 | | 20 | V |
| V_IN1 Supply Range | | | -40°C ≤ T_J ≤ 150°C | 3.1 | | 20 | V |
| V_IN2 Supply Range | | 3.1V < V_IN1 < 20V | -40°C ≤ T_J ≤ 150°C | 1.5 | | 20 | V |
| Output Voltage Range (4) | | LTC3636 | | 0.6 | | 5 | V |
| Output Voltage Range (4) | | LTC3636-1 | | 1.8 | | 12 | V |
| **Input DC Supply Current (V_IN1 + V_IN2)** | I_Q | | | | | | |
| Both Channels Active (5) | I_Q | MODE = 0V | | | 1.3 | | mA |
| Sleep Current | I_Q | MODE = INTV_CC, V_FB1, V_FB2 > 0.6 | | | 600 | | µA |
| Shutdown | I_Q | RUN1 = RUN2 = 0V | | | 13 | | µA |
| Feedback Reference Voltage | V_FB | | -40°C ≤ T_J ≤ 150°C | 0.594 | 0.6 | 0.606 | V |
| Reference Voltage Line Regulation | ΔV_LINE_REG | V_IN = 3.1V to 20V | | | 0.002 | | %/V |
| Output Voltage Load Regulation | ΔV_LOAD_REG | ITH = 0.8V to 1.6V | | | 0.05 | | % |
| Feedback Pin Input Current | I_FB | | | −30 | | 30 | nA |
| Error Amplifier Transconductance | g_m(EA) | ITH = 1.2V | | | 1.8 | | mS |
| Minimum On-Time | t_ON | LTC3636 | | | 30 | 35 | ns |
| Minimum On-Time | t_ON | LTC3636-1 | | | 30 | | |
| Minimum Off-Time | t_OFF | | | | 100 | | ns |
| Oscillator Frequency | f_OSC | V_RT = INTV_CC | | 1.4 | 2 | 2.6 | MHz |
| Oscillator Frequency | f_OSC | RT = 162k | | 1.7 | 2 | 2.3 | MHz |
| Oscillator Frequency | f_OSC | RT = 80.6k | | 3.4 | 4 | 4.6 | MHz |
| Valley Switch Current Limit | I_LIM | ITH = 1.8V | | 6 | 6.6 | 7.2 | A |
| Negative Valley Switch Current Limit | I_LIM | | | | -4.2 | | A |
| Top Switch On-Resistance | R_DS(ON) | | | | 32 | | mΩ |
| Bottom Switch On-Resistance | R_DS(ON) | | | | 18 | | mΩ |
| Switch Leakage Current | I_SW(LKG) | V_IN = 20V, V_RUN = 0V | | -1 | 0.01 | 1 | µA |
| Internal Temperature Monitor | | T_A = 25°C | | | 1.5 | | V |
| Internal Temperature Monitor Slope (6) | | | | | 200 | | °C/V |
| V_IN Overvoltage Lockout Threshold | V_VIN-OV | V_IN Rising | | | 22.5 | | V |
| V_IN Overvoltage Lockout Threshold | V_VIN-OV | V_IN Falling | | 20.3 | 21.5 | 22.5 | V |
| INTV_CC Voltage | | 3.6V < V_IN < 20V, 0mA Load, QFN | | 3.1 | 3.3 | 3.5 | V |
| INTV_CC Load Regulation | | 0mA to 50mA Load, V_IN = 4V to 20V | | | 1.3 | | % |
| INTV_CC Undervoltage Lockout Threshold | | INTV_CC Rising, V_IN = INTV_CC | | | 2.7 | 2.9 | V |
| INTV_CC Undervoltage Lockout Threshold | | INTV_CC Falling, V_IN = INTV_CC | | | 2.55 | | V |
| RUN Threshold Rising | | | -40°C ≤ T_J ≤ 150°C | 1.16 | 1.22 | 1.28 | V |
| RUN Threshold Falling | | | -40°C ≤ T_J ≤ 150°C | 0.96 | 1.01 | 1.06 | V |
| RUN Leakage Current | | | | -3 | 0 | 3 | µA |
| PGOOD Good-to-Bad Threshold | | V_FB Rising | | | 8 | 10 | % |
| PGOOD Good-to-Bad Threshold | | V_FB Falling | | -10 | -8 | | % |
| PGOOD Bad-to-Good Threshold | | V_FB Rising | | | -5 | -3 | % |
| PGOOD Bad-to-Good Threshold | | V_FB Falling | | 3 | 5 | | % |
| PGOOD Pull-Down Resistance | R_PGOOD | 10mA Load | | | 25 | | Ω |
| Power Good Filter Time | t_PGOOD | | | 20 | 40 | | µs |
| Internal Soft-Start Time | t_SS | 10% to 90% Rise Time | | | 1000 | 1500 | µs |
| V_FB During Tracking QFN | | TRACKSS = 0.3V | | 0.28 | 0.3 | 0.315 | V |
| TRACKSS Pull-Up Current | I_TRACKSS | | | | 1.4 | | µA |
| MODE/SYNC Threshold Voltage | V_MODE/SYNC | MODE V_IH | | 1 | | | V |
| MODE/SYNC Threshold Voltage | V_MODE/SYNC | MODE V_IL | | | | 0.4 | V |
| SYNC Threshold Voltage | | SYNC V_IH | | 0.95 | | | V |
| MODE/SYNC Input Current | I_MODE | MODE = 0V | | | 1.5 | | µA |
| MODE/SYNC Input Current | I_MODE | MODE = INTV_CC | | | −1.5 | | µA |
- **Note 1:** Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime.
- **Note 2:** The LTC3636 is tested under pulsed load conditions such that TJ ≈ TA. The LTC3636E is guaranteed to meet specifications from 0°C to 125°C junction temperature. Specifications over the –40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LTC3636I is guaranteed over the –40°C to 125°C operating junction temperature range. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. The junction temperature (TJ, in °C) is calculated from the ambient temperature (TA, in °C) and power dissipation (PD, in Watts) according to the formula: TJ = TA + (PD • θ_JA), where θ_JA (in °C/W) is the package thermal impedance.
- **Note 3:** This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125°C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability.
- **Note 4:** Output voltages outside the specified range are not optimized for controlled on-time operation. Refer to the Applications Information section for further discussions related to the output voltage range.
- **Note 5:** Dynamic supply current is higher due to the internal gate charge being delivered at the switching frequency.
- **Note 6:** Guaranteed by design.
- **Note 7:** Human body model (HBM) per ANSI/ESDA/JEDEC JS-001. Field induced charged device model (FICDM) per ANSI/ESDA/JEDEC JS-002.
### ABSOLUTE MAXIMUM RATINGS
TA = 25°C unless otherwise specified.
**Table 2. Absolute Maximum Ratings** ([table-01-p5-abs_max.csv](ltc3636/tables/table-01-p5-abs_max.csv), p. 5)
| PARAMETER | RATING |
|---|---|
| V_IN1, V_IN2 | −0.3V to 22V |
| PGOOD1, PGOOD2 | −0.3V to 22V |
| BOOST1-SW1, BOOST2-SW2 | −0.3V to 3.6V |
| TRACKSS1, TRACKSS2 | −0.3V to 3.6V |
| ITH1, ITH2, RT, MODE/SYNC | −0.3V to INTV_CC + 0.3V |
| VFB1, VFB2, TMON | −0.3V to INTV_CC + 0.3V |
| RUN1 | −0.3V to V_IN1 + 0.3V |
| RUN2 | -0.3V to V_IN2 + 0.3V |
| Operating Junction Temperature Range (3, 4) | −40°C to 125°C |
| Storage Temperature Range | −65°C to 150°C |
| Maximum Reflow (Package Body) Temperature | 260°C |
### ELECTROSTATIC DISCHARGE RATINGS (Note 7)
**Table 3. LTC3636 28-Lead (4mm × 5mm) Plastic QFN (Electrostatic Discharge Ratings)** ([table-02-p5-data.csv](ltc3636/tables/table-02-p5-data.csv), p. 5)
| ESD MODEL | WITHSTAND THRESHOLD (V) | CLASS |
|---|---|---|
| HBM | ±1500 | 1C |
| FICDM | ±1250 | C3 |
### ESD Caution
ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality.
### PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
### Pin Descriptions
### Table 4. Pin Descriptions
**Table 4. Pin Descriptions** ([table-03-p6-pin.csv](ltc3636/tables/table-03-p6-pin.csv), p. 6)
| NUMBER | NAME | TYPE | DESCRIPTION |
|---|---|---|---|
| Pin 1 | ITH1 | | Channel 1 Error Amplifier Output and Switching Regulator Compensation Pin. Connect this pin to appropriate external components to compensate the regulator loop frequency response. Connect this pin to INTV_CC to use the default internal compensation. |
| Pin 2 | RUN1 | | Channel 1 Regulator Enable Pin. Enables channel 1 operation by tying RUN above 1.25V. Tying it below 1V places the part into shutdown. Do not float this pin. |
| Pin 3 | MODE/SYNC | | Mode Select and External Synchronization Input. Tie this pin to ground to force continuous synchronous operation. Floating this pin or tying it to INTV_CC enables high efficiency Burst Mode operation at light loads. Drive this pin with a clock to synchronize the LTC3636/LTC3636-1 switching frequency. An internal phase-locked loop will force the bottom power NMOS's turn on signal to be synchronized with the rising edge of the CLKIN signal. When this pin is driven with a clock, forced continuous mode is automatically selected. |
| Pin 4 | RT | | Oscillator Frequency Program Pin. Connect an external resistor (between 80k to 640k) from this pin to GND in order to program the frequency from 500kHz to 4MHz. When RT is tied to INTV_CC, the switching frequency will default to 2MHz. |
| Pin 5 | INTV_CC | | Internal 3.3V Regulator Output. The internal power drivers and control circuits are powered from this voltage. Decouple this pin to power ground with a minimum of 4.7µF low ESR ceramic capacitor. |
| Pin 6 | TMON | | Temperature Monitor Output. A voltage proportional to the measured on-die temperature will appear at this pin. The voltage-to-temperature scaling factor is 200°K/V. See the Applications Information section for detailed information on the TMON function. Tie this pin to INTV_CC to disable the temperature monitor circuit. |
| Pin 7 | RUN2 | | Channel 2 Regulator Enable Pin. Enables channel 2 operation by tying RUN above 1.22V. Tying it below 1V places the part into shutdown. Do not float this pin. |
| Pin 8 | ITH2 | | Channel 2 Error Amplifier Output and Switching Regulator Compensation Pin. Connect this pin to appropriate external components to compensate the regulator loop frequency response. Connect this pin to INTV_CC to use the default internal compensation. |
| Pin 9 | V_FB2 | | Channel 2 Output Feedback Voltage Pin. Input to the error amplifier that compares the feedback voltage to the internal 0.6V reference voltage. Connect this pin to a resistor divider network to program the desired output voltage. |
| Pin 10 | PGOOD2 | | Channel 2 Open-Drain Power Good Output Pin. PGOOD2 is pulled to ground when the voltage on the V_FB2 pin is not within ±8% (typical) of the internal 0.6V reference. PGOOD2 becomes high impedance once the V_FB2 pin returns to within ±5% (typical) of the internal reference. |
| Pin 11 | TRACKSS2 | | Output Tracking and Soft-Start Input Pin for Channel 2. Forcing a voltage below 0.6V on this pin bypasses the internal reference input to the error amplifier. The LTC3636/LTC3636-1 will servo the FB pin to the TRACK voltage. Above 0.6V, the tracking function stops and the internal reference resumes control of the error amplifier. An internal 1.4µA pull up current from INTV_CC allows a soft-start function to be implemented by connecting a capacitor between this pin and PGND. |
| Pins 12, 18, 19, 25 | GND | | Power and Signal Ground. These pins must be tied together and soldered to PCB ground. |
| Pins 13, 17 | SW2 | | Channel 2 Switch Node Connection to External Inductor. Voltage swing of SW is from a diode voltage drop below ground to V_IN. |
| Pin 14 | BOOST2 | | Boosted Floating Driver supply for Channel 2. The (+) terminal of the bootstrap capacitor connects to this pin while the (−) terminal connects to the SW pin. The normal operational voltage swing of this pin ranges from a diode voltage drop below INTV_CC up to V_IN+INTV_CC. |
| Pins 15, 16 | V_IN2 | | Power Supply Input for Channel 2. This input is capable of operating from a separate supply voltage than V_IN1. |
| Pins 20, 24 | SW1 | | Channel 1 Switch Node Connection to External Inductor. Voltage swing of SW is from a diode voltage drop below ground to V_IN. |
| Pins 21, 22 | V_IN1 | | Power Supply Input for Channel 1. Input voltage to the on chip power MOSFETs on channel 1. The internal LDO for INTV_CC is powered off of this pin. |
| Pin 23 | BOOST1 | | Boosted Floating Driver Supply for Channel 1. The (+) terminal of the bootstrap capacitor connects to this pin while the (–) terminal connects to the SW pin. The normal operational voltage swing of this pin ranges from a diode voltage drop below INTV_CC up to V_IN + INTV_CC. |
| Pin 26 | TRACKSS1 | | Output Tracking and Soft-Start Input Pin for Channel 1. Forcing a voltage below 0.6V on this pin bypasses the internal reference input to the error amplifier. The LTC3636/LTC3636-1 will servo the FB pin to the TRACK voltage. Above 0.6V, the tracking function stops and the internal reference resumes control of the error amplifier. An internal 1.4µA pull up current from INTV_CC allows a soft-start function to be implemented by connecting a capacitor between this pin and PGND. |
| Pin 27 | PGOOD1 | | Channel 1 Open-Drain Power Good Output Pin. PGOOD1 is pulled to ground when the voltage on the V_FB1 pin is not within ±8% (typical) of the internal 0.6V reference. PGOOD1 becomes high impedance once the V_FB1 pin returns to within ±5% (typical) of the internal reference. |
| Pin 28 | V_FB1 | | Channel 1 Output Feedback Voltage Pin. Input to the error amplifier that compares the feedback voltage to the internal 0.6V reference voltage. Connect this pin to a resistor divider network to program the desired output voltage. |
| Pin 29 | INTV_CCT | | Additional INTV_CC pin. Not required to be connected to INTV_CC pin for operation. |
| Pins 30, 31, 32 | GNDT | | Power Ground. Additional power ground pins for improved thermal dissipation when connected to the GND pins. Not required to be connected to GND pins for operation. |
| Pin 33 | SWT1T | | Additional SW1 pin. Not required to be connected to SW1 pins 20 and 24 for operation. |
| Pins 34 | SWT2T | | Additional SW2 pin. Not required to be connected to SW2 pins 13 and 17 for operation |
### BLOCK DIAGRAM
### TYPICAL PERFORMANCE CHARACTERISTICS
TJ = 25°C, V IN1 = V IN2 = 12V, f SW = 1MHz, L = 0.55µH unless otherwise noted.
### THEORY OF OPERATION
The LTC3636/LTC3636-1 is a dual-channel, current mode monolithic step down regulator capable of providing 6A of output current from each channel. Its unique controlled on-time architecture allows extremely low step-down ratios while maintaining a constant switching frequency. Both channels share the same clock and run 180° out of phase. Each channel is enabled by raising the voltage on the RUN pin above 1.22V nominally.
### Main Control Loop
In normal operation, the internal top power MOSFET is turned on for a fixed interval determined by a fixed one-shot timer ('ON' signal in Block Diagram). When the top power MOSFET turns off, the bottom power MOSFET turns on until the current comparator I CMP trips, thus restarting the one shot timer and initiating the next cycle. Inductor current is measured by sensing the voltage drop across the SW and GND nodes of the bottom power MOSFET. The voltage on the ITH pin sets the comparator threshold corresponding to inductor valley current. The error amplifier EA adjusts this ITH voltage by comparing an internal 0.6V reference to the feedback signal V FB derived from the output voltage. If the load current increases, it causes a drop in the feedback voltage relative to the internal reference. The ITH voltage then rises until the average inductor current matches that of the load current.
The operating frequency is determined by the value of the RT resistor, which programs the current for the internal oscillator. An internal phase-locked loop servos the switching regulator on-time to track the internal oscillator edge and force a constant switching frequency. A clock signal can be applied to the MODE/SYNC pin to synchronize the switching frequency to an external source. The regulator defaults to forced continuous operation once the clock signal is applied.
At light load currents, the inductor current can drop to zero and become negative. In Burst Mode operation, a current reversal comparator (I REV ) detects the negative inductor current and shuts off the bottom power MOSFET, resulting in discontinuous operation and increased efficiency. Both power MOSFETs will remain off until the ITH voltage rises above the zero current level to initiate another cycle. During this time, the output capacitor supplies the load current and the part is placed into a low current sleep mode. Discontinuous mode operation is disabled by tying the MODE/SYNC pin to ground, which forces continuous synchronous operation regardless of output load current.
### 'Power Good' Status Output
The PGOOD open-drain output will be pulled low if the regulator output exits a ±8% window around the regulation point. This condition is released once regulation within a ±5% window is achieved. To prevent unwanted PGOOD glitches during transients or dynamic V OUT changes, the LTC3636/LTC3636-1 PGOOD falling edge includes a filter time of approximately 40µs.
### VIN Overvoltage Protection
In order to protect the internal power MOSFET devices against transient input voltage spikes, the LTC3636/ LTC36361 constantly monitors each V IN pin for an overvoltage condition. When V IN rises above 22.5V, the regulator suspends operation by shutting off both power MOSFETs on the corresponding channel. Once V IN drops below 21.5V, the regulator immediately resumes normal operation. The regulator executes its soft-start function when exiting an overvoltage condition.
### Overcurrent and Short-Circuit Protection
The LTC3636 protects itself against output overcurrent and short-circuits by sensing the inductor valley current. When the current limit is reached, the output begins to fall, resulting in decreased on-time of the top power MOSFET. If the short is prolonged enough for the on-time to reach its minimum, the off-time will lengthen, lowering the switching frequency and preventing excess current from being drawn from V IN . After the overcurrent or short is removed, the regulator executes its soft-start function to prevent the output voltage from overshooting.
### APPLICATIONS INFORMATION
A general LTC3636/LTC3636-1 application circuit is shown on the first page of this data sheet. External component selection is largely driven by the load requirement and switching frequency. Component selection typically begins with the selection of the inductor L and resistor R T . Once the inductor is chosen, the input capacitor, C IN , and the output capacitor, C OUT , can be selected. Next, the feedback resistors are selected to set the desired output voltage. Finally, the remaining optional external components can be selected for functions such as external loop compensation, tracking/soft-start, input UVLO, and PGOOD.
### Programming Switching Frequency
Selection of the switching frequency is a trade-off between efficiency and component size. High frequency operation allows the use of smaller inductor and capacitor values. Operation at lower frequencies improves efficiency by reducing internal gate charge losses but requires larger inductance values and/or capacitance to maintain low output ripple voltage.
Connecting a resistor from the RT pin to GND programs the switching frequency (f) between 500kHz and 4MHz according to the following formula:
$$R_{RT} = \frac{3.2 E^{11}}{f}$$
*LaTeX transcription of the equation above, checked against the symbols printed on the page.*
where RRT is in Ω and f is in Hz.
When RT is tied to INTV CC , the switching frequency will default to approximately 2MHz, as set by an internal resistor. This internal resistor is more sensitive to process
and temperature variations than an external resistor (see Typical Performance Characteristics) and is best used for applications where switching frequency accuracy is not critical.
### Dual-Phase Single V OUT Operation
For output loads that demand more than 6A of current, the two channels can be configured in parallel as a single output to provide more output current. During dual-phase operation, it is recommended to set the switching frequency above 800kHz to ensure stability over a wide input voltage range.
With dual-phase operation, the two channels of the LTC3636 are operated 180 degrees out of phase. This effectively interleaves the current pulses coming from the switches, greatly reducing the overlap time when they add together. The result is a significant reduction in total RMS input current, which in turn allows less expensive input capacitors to be used and reduces the voltage noise on the supply line.
The two channels in parallel will inherently share current well, because the LTC3636 is a current mode controlled regulator. When operating the channels in parallel, tie the respective RUN, TRACKSS, V FB , and ITH pins together; do not tie ITH pins to INTV CC . Use external compensation on the combined ITH pins. Good current sharing balances the thermals on the design.
### Inductor Selection
For a given input and output voltage, the inductor value and operating frequency determine the inductor ripple current. More specifically, the inductor ripple current decreases with higher inductor value or higher operating frequency according to the following equation:
$$\Delta I_{L} = \left( \frac{V_{OUT}}{f \cdot L} \right) \left( 1 - \frac{V_{OUT}}{V_{IN}} \right)$$
*LaTeX transcription of the equation above, checked against the symbols printed on the page.*
Where ∆I L = inductor ripple current, f = operating frequency L = inductor value and V IN is the input power supply voltage applied to the V IN inputs. A trade-off between component size, efficiency and operating frequency can be seen from this equation. Accepting larger values of ∆I L allows the use of lower value inductors but results in greater inductor core loss; greater ESR loss in the output capacitor; and larger output voltage ripple. Generally, highest efficiency operation is obtained at low operating frequency with small ripple current.
A reasonable starting point is to choose a ripple current of 2.4A which is about 40% of I OUT(MAX) . Exceeding 60% of I OUT(MAX) is not recommended. Note that the largest ripple current occurs at the highest V IN . To guarantee that ripple current does not exceed a specified maximum, the inductance should be chosen according to:
$$L = \left( \frac{V_{OUT}}{f \cdot \Delta I_{L(MAX)}} \right) \left( 1 - \frac{V_{OUT}}{V_{IN(MAX)}} \right)$$
*LaTeX transcription of the equation above, checked against the symbols printed on the page.*
Once the value for L is known, the type of inductor must be selected. Actual core loss is independent of core size for a fixed inductor value, but is very dependent on the inductance selected. As the inductance increases, core losses decrease. Unfortunately, increased inductance requires more turns of wire, leading to increased DCR and copper loss.
Ferrite designs exhibit very low core loss and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite core material saturates 'hard', which means that inductance collapses abruptly when the peak design current is exceeded. This results in an abrupt increase in inductor ripple current, so it is important to ensure that the core will not saturate.
Different core materials and shapes will change the size/ current and price/current relationship of an inductor. Toroid or shielded pot cores in ferrite or permalloy materials are small and don't radiate much energy, but generally cost more than powdered iron core inductors with similar characteristics. The choice of which style inductor to use mainly depends on the price versus size requirements and any radiated field/EMI requirements. Table 5 gives a sampling of available surface mount inductors.
**Table 5. Inductor Selection Table** ([table-04-p15-data.csv](ltc3636/tables/table-04-p15-data.csv), p. 15)
| INDUCTANCE (µH) | DCR (mΩ) | MAX CURRENT (A) | DIMENSIONS (mm) | HEIGHT (mm) |
|---|---|---|---|---|
| **Wurth Electronik WE-HC 744312 Series** | | | | |
| 0.25 | 2.5 | 18 | 7 × 7.7 | 3.8 |
| 0.47 | 3.4 | 16 | | |
| 0.72 | 7.5 | 12 | | |
| 1.0 | 9.5 | 11 | | |
| 1.5 | 10.5 | 9 | | |
| **Vishay IHLP-2020BZ-01 Series** | | | | |
| 0.22 | 5.2 | 15 | 5.2 × 5.5 | 2 |
| 0.33 | 8.2 | 12 | | |
| 0.47 | 8.8 | 11.5 | | |
| 0.68 | 12.4 | 10 | | |
| 1 | 20 | 7 | | |
| **Toko FDVE0603 Series** | | | | |
| 0.33 | 2.7 | 15.9 | 7.4 × 6.7 | 3.0 |
| 0.47 | 3.7 | 15.6 | | |
| 0.68 | 6 | 10.4 | | |
| 0.75 | 6.2 | 10.9 | | |
| 1 | 8.5 | 9.5 | | |
| **Coilcraft XAL6030 Series** | | | | |
| 0.20 | 3.04 | 17.2 | 6.4 × 6.6 | 3 |
| 0.33 | 5.18 | 15.4 | | |
| 0.56 | 8 | 13.8 | | |
| 0.82 | 11.8 | 11.5 | | |
| 1.0 | 13.25 | 9.6 | | |
| **TDK SPM 5030 Series** | | | | |
| 0.2 | 2.31 | 21 | 5.2 × 5 | 3 |
| 0.35 | 4.29 | 14.9 | | |
| 0.75 | 9.35 | 9.7 | | |
| 1 | 11.44 | 8.5 | | |
### CIN and C OUT Selection
The input capacitance, C IN , is needed to filter the trapezoidal wave current at the drain of the top power MOSFET. To prevent large voltage transients from occurring, a low ESR input capacitor sized for the maximum RMS current is recommended. The maximum RMS current is given by:
$$I_{RMS} = I_{OUT(MAX)} \frac{\sqrt{V_{OUT}(V_{IN} - V_{OUT})}}{V_{IN}}$$
*LaTeX transcription of the equation above, checked against the symbols printed on the page.*
This formula has a maximum at V IN = 2V OUT , where I RMS ≅ I OUT /2. This simple worst case condition is commonly used for design because even significant deviations do not offer much relief. Note that ripple current ratings from capacitor manufacturers are often based on only 2000 hours of life which makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required.
Several capacitors may also be paralleled to meet size or height requirements in the design. For low input voltage applications, sufficient bulk input capacitance is needed to minimize transient effects during output load changes. Even though the LTC3636/LTC3636-1 design includes an overvoltage protection circuit, care must always be taken to ensure input voltage transients do not pose an overvoltage hazard to the part.
The selection of C OUT is determined by the effective series resistance (ESR) that is required to minimize voltage ripple and load step transients as well as the amount of bulk capacitance that is necessary to ensure that the control loop is stable. Loop stability can be checke d by viewing the load transient response. The output ripple, ∆V OUT , is approximated by:
$$\Delta V_{OUT} < \Delta I_{L} \left( ESR + \frac{1}{8 \cdot f \cdot C_{OUT}} \right)$$
*LaTeX transcription of the equation above, checked against the symbols printed on the page.*
When using low-ESR ceramic capacitors, it is more useful to choose the output capacitor value to fulfill a charge storage requirement. During a load step, the output capacitor must instantaneously supply the current to support the load until the feedback loop raises the switch current enough to support the load. The time required for the feedback loop to respond is dependent on the compensation and the output capacitor size. Typically, 3 to 4 cycles are required to respond to a load step, but only in the first cycle does the output drop linearly. The output droop, VDROOP , is usually about 3 times the linear drop of the first cycle. Thus, a good place to start is with the output capacitor of approximately:
$$C_{OUT} \approx \frac{3 \cdot \Delta I_{OUT}}{f \cdot V_{DROOP}}$$
*LaTeX transcription of the equation above, checked against the symbols printed on the page.*
Though this equation provides a good approximation, more capacitance may be required depending on the duty cycle and load step requirements. The actual V DROOP should be verified by applying a load step to the output.
### Using Ceramic Input and Output Capacitors
Higher values, lower cost ceramic capacitors are available in small case sizes. Their high ripple current, high voltage rating and low ESR make them ideal for switching regulator applications. However, due to the self-resonant and highQ characteristics of some types of ceramic capacitors, care must be taken when these capacitors are used at the input. When a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the V IN input. At best, this ringing can couple to the output and be mistaken as loop instability. At worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at V IN large enough to damage the part. For a more detailed discussion, refer to Application Note 88.
When choosing the input and output ceramic capacitors, choose the X5R and X7R dielectric formulations. These dielectrics have the best temperature and voltage characteristics of all the ceramics for a given value and size.
### INTV CC Regulator Bypass Capacitor
An internal low dropout (LDO) regulator draws power from the V IN1 input and produces the 3.3V supply that powers the internal bias circuitry and drives the gate of the internal MOSFET switches. The INTV CC pin connects to the output of this regulator and must have a minimum of 4.7µF ceramic decoupling capacitance to ground. The decoupling capacitor should have low impedance electrical connections to the INTV CC and GND pins to provide the transient currents required by the LTC3636/LTC3636- 1. High input voltage and high switching frequency will increase die temperature because of the higher power dissipation across the LDO. Connecting any external load to the INTV CC pin is not recommended since it may impact LTC3636/LTC3636-1 operation while increasing power dissipation and die temperature.
### Boost Capacitor
The LTC3636/LTC36361 uses a 'bootstrap' circuit to create a voltage rail above the applied input voltage V IN . Specifically, a boost capacitor, C BOOST , is charged to a voltage approximately equal to INTV CC each time the bottom power MOSFET is turned on. The charge on this capacitor is then used to supply the required transient current during the remainder of the switching cycle. When the top MOSFET is turned on, the BOOST pin voltage will be equal to approximately V IN + 3.3V. For most applications, a 0.1µF ceramic capacitor closely connected between the BOOST and SW pins will provide adequate performance.
### Output Voltage Programming
Each regulator's output voltage is set by an external resistive divider according to the following equation:
$$V_{OUT} = 0.6 V \left( 1 + \frac{R 2}{R 1} \right)$$
*LaTeX transcription of the equation above, checked against the symbols printed on the page.*
The desired output voltage is set by appropriate selection of resistors R1 and R2 as shown in Figure 27 . Choosing large values for R1 and R2 will result in improved zeroload efficiency but may lead to undesirable noise coupling or phase margin reduction due to stray capacitances at the V FB node. Care should be taken to route the V FB trace away from any noise source, such as the SW trace. To improve the frequency response of the main control loop, a feedforward capacitor, C F , may be used as shown in Figure 27 .
If the output voltage is outside the V ON sense range (0.6V -5V for the LTC3636, 1.8V -12V for the LTC3636-1), the output voltage will stay in regulation, but the switching frequency may deviate from the programmed frequency
### Minimum Off-Time/On-Time Considerations
The minimum off-time is the smallest amount of time that the LTC3636/LTC3636-1 can turn on the bottom power MOSFET, trip the current comparator and turn the power MOSFET back off. This time is typically 100ns. For the controlled on-time architecture, the minimum off-time limit imposes a maximum duty cycle of:
$$DC_{( MAX )} = 1 - f \cdot ( t_{OFF ( MIN )} + 2 \cdot t_{DEAD} )$$
*LaTeX transcription of the equation above, checked against the symbols printed on the page.*
where f is the switching frequency, t DEAD is the non overlap time, or 'dead time' (typically 5ns) and t OFF(MIN) is the minimum off-time. If the maximum duty cycle is surpassed, due to a dropping input voltage for example, the output will drop out of regulation. The minimum input voltage to avoid this dropout condition is:
$$V_{IN(MIN)} = \frac{V_{OUT}}{1 - f \cdot (t_{OFF(MIN)} + 2 \cdot t_{DEAD})}$$
*LaTeX transcription of the equation above, checked against the symbols printed on the page.*
Conversely, the minimum ontime is the smallest duration of time in which the top power MOSFET can be in its 'on' state. This time is typically 30ns. In continuous mode operation, the minimum on-time limit imposes a minimum duty cycle of:
$$DC_{(MIN)} = \left( f \cdot t_{ON(MIN)} \right)$$
*LaTeX transcription of the equation above, checked against the symbols printed on the page.*
where t ON(MIN) is the minimum on-time. As the equation shows, reducing the operating frequency will alleviate the minimum duty cycle constraint.
In the rare cases where the minimum duty cycle is surpassed, the output voltage will still remain in regulation, but the switching frequency will decrease from its programmed value. This constraint may not be of critical importance in most cases, so high switching frequencies may be used in the design without any fear of severe consequences. As the sections on Inductor and Capacitor selection show, high switching frequencies allow the use of smaller board components, thus reducing the footprint of the application circuit.
### Internal/External Loop Compensation
The LTC3636/LTC3636-1 provides the option to use a fixed internal loop compensation network to reduce both the required external component count and design time. The internal loop compensation network can be selected by connecting the ITH pin to the INTV CC pin. To ensure stability it is recommended that internal compensation only be used with applications with f SW > 1MHz. Alternatively, the user may choose specific external loop compensation components to optimize the main control loop transient response as desired. External loop compensation is chosen by simply connecting the desired network to the ITH pin.
Suggested compensation component values are shown in Figure 28 . For a 2MHz application, an R-C network of 220pF and 13kΩ provides a good starting point. The bandwidth of the loop increases with decreasing C. If R is increased by the same factor that C is decreased, the zero frequency will be kept the same, thereby keeping the phase the same in the most critical frequency range of the feedback loop. A 10pF bypass capacitor on the ITH pin is recommended for the purposes of filtering out high frequency coupling from stray board capacitance. In addition, a feedforward capacitor C F can be added to improve the high frequency response, as previously shown in Figure 27 . Capacitor C F provides phase lead by creating a high frequency zero with R2 which improves the phase margin.
### Checking Transient Response
The regulator loop response can be checked by observing the response of the system to a load step. When configured for external compensation, the availability of the ITH pin not only allows optimization of the control loop behavior but also provides a DC-coupled and AC filtered closed loop response test point. The DC step, rise time, and settling behavior at this test point reflect the closed loop response. Assuming a predominantly second order system, phase margin and/or damping factor can be estimated using the percentage of overshoot seen at this pin.
The ITH external components shown in Figure 28 circuit will provide an adequate starting point for most applications. The series R-C filter sets the dominant pole-zero loop compensation. The values can be modified slightly (from 0.5 to 2 times their suggested values) to optimize transient response once the final PC layout is done and the particular output capacitor type and value have been determined. The output capacitors need to be selected because their various types and values determine the loop gain and phase. An output current pulse of 20% to 100% of full load current having a rise time of ~1µs will produce output voltage and ITH pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop.
Switching regulators take several cycles to respond to a step in load current. When a load step occurs, V OUT immediately shifts by an amount equal to ∆I LOAD · ESR, where ESR is the effective series resistance of C OUT . ∆I LOAD also begins to charge or discharge C OUT generating a feedback error signal used by the regulator to return V OUT to its steady-state value. During this recovery time, V OUT can be monitored for overshoot or ringing that would indicate a stability problem.
When observing the response of V OUT to a load step, the initial output voltage step may not be within the bandwidth of the feedback loop. In this case, the standard second order overshoot/DC ratio cannot be used to determine phase margin. The output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. For a detailed explanation of optimizing the compensation components, including a review of control loop theory, refer to Linear Technology Application Note 76.
In some applications, a more severe transient can be caused by switching in loads with large (>10µF) input capacitors. The discharged input capacitors are effectively put in parallel with C OUT , causing a rapid drop in V OUT . No regulator can deliver enough current to prevent this problem, if the switch connecting the load has low resistance and is driven quickly. The solution is to limit the turn-on speed of the load switch driver. A hot swap controller is designed specifically for this purpose and usually incorporates current limiting, short-circuit protection, and soft starting.
### On-Die Temperature Monitor
The LTC3636/LTC3636-1 produces a voltage at the TMON pin proportional to the measured junction temperature. The junction temperature-to-voltage scaling factor is 200°K/V. Thus, to obtain the junction temperature in degrees Kelvin, simply multiply the voltage provided at the TMON pin by the scaling factor. To obtain the junction temperature in degrees Celsius, subtract 273 from the value obtained in degrees Kelvin.
The temperature monitor function uses a chopping technique to achieve high precision. As a result, a small periodic ripple may be seen at the TMON pin, the average of which is the measured value of interest. The ripple frequency will be the operating frequency divided by 32. If required, a 1µF or greater capacitor to GND may be placed on the output to reduce the magnitude of the ripple.
### MODE/SYNC Operation
The MODE/SYNC pin is a multipurpose pin allowing both mode selection and operating frequency synchronization. Floating this pin or connecting it to INTV CC enables Burst Mode operation for superior efficiency at low load currents at the expense of slightly higher output voltage ripple. When the MODE/SYNC pin is tied to ground, forced continuous mode operation is selected, creating the lowest fixed output ripple at the expense of light load efficiency.
The LTC3636/LTC3636-1 will detect the presence of the external clock signal on the MODE/SYNC pin and synchronize the internal oscillator to the phase and frequency of the incoming clock. The presence of an external clock will place both regulators into forced continuous mode operation.
### Output Voltage Tracking and Soft-Start
The LTC3636/LTC3636-1 allows the user to control the output voltage ramp rate by means of the TRACKSS pin. From 0 to 0.6V, the TRACKSS voltage will override the internal 0.6V reference input to the error amplifier, thus regulating the feedback voltage to that of the TRACKSS pin. When TRACKSS is above 0.6V, tracking is disabled and the feedback voltage will regulate to the internal reference voltage.
The voltage at the TRACKSS pin may be driven from an external source, or alternatively, the user may leverage the internal 1.4µA pull-up current source to implement a soft-start function by connecting an external capacitor (C SS ) from the TRACKSS pin to ground. The relationship between output rise time and TRACKSS capacitance is given by:
$$t_{ss} = 430000 \Omega \cdot C_{ss}$$
*LaTeX transcription of the equation above, checked against the symbols printed on the page.*
A default internal soft-start ramp forces a minimum soft-start time of 1000µs by overriding the TRACKSS pin input during this time period. Hence, capacitance values less than approximately 2200pF will not significantly affect softstart behavior.
When driving the TRACKSS pin from another source, each channel's output can be set up to either coincidentally or ratiometrically track another supply's output, as shown in Figure 29 , Figure 30 . In the following discussions, V OUT1 refers to the LTC3636/LTC3636-1 output 1 as a master channel and V OUT2 refers to output 2 as a slave channel. In practice, either channel can be used as the master.
To implement the coincident tracking in Figure 29 connect an additional resistive divider to V OUT1 and connect its midpoint to the TRACKSS pin of the slave channel. The ratio of this divider should be the same as that of the slave channel's feedback divider shown in Figure 31a . In
(b) RATIOMETRIC TRACKING 033
this tracking mode, V OUT1 must be set higher than V OUT2 . To implement the ratiometric tracking, the feedback pin of the master channel should connect to the TRACKSS pin of the slave channel (as in Figure 31b ). By selecting different resistors, the LTC3636/LTC3636-1 can achieve different modes of tracking including the two in Figure 29, Figure 30 .
Upon start-up, the regulator defaults to Burst Mode operation until the output exceeds 80% of its final value (V FB > 0.48V). Once the output reaches this voltage, the operating mode of the regulator switches to the mode selected by the MODE/SYNC pin as described above. During normal operation, if the output drops below 10% of its final value (as it may when tracking down, for instance), the regulator will automatically switch to Burst Mode operation to prevent inductor saturation and improve TRACKSS pin accuracy.
### Output Power Good
The PGOOD output of the LTC3636/LTC36361 is driven by a 25Ω (typical) open -drain pull-down device. This device will be turned off once the output voltage is within 5% (typical) of the target regulation point, allowing the voltage at PGOOD to rise via an external pull-up resistor. If the output voltage exits an 8% (typical) regulation window around the target regulation point, the opendrain output will pull down with 20Ω output resistance to ground, thus dropping the PGOOD pin voltage. This behavior is described in Figure 32 .
A filter time of 40µs (typical) acts to prevent unwanted PGOOD output changes during V OUT transient events. As a result, the output voltage must be within the target regulation window of 5% for 40µs before the PGOOD pin pulls high. Conversely, the output voltage must exit the 8% regulation window for 40µs before the PGOOD pin pulls to ground.
### Efficiency Considerations
The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Percent efficiency can be expressed as:
$$\% \text{Efficiency} = 100 \% - ( \lfloor 1 + \lfloor 2 + \lfloor 3 + \dots \rfloor \rfloor )$$
*LaTeX transcription of the equation above, checked against the symbols printed on the page.*
where L1, L2, etc. are the individual losses as a percentage of input power.
Although all dissipative elements in the circuit produce losses, three main sources usually account for most of the losses in LTC3636/LTC3636-1 circuits: 1) I 2 R losses, 2) switching losses and quiescent power loss 3) transition losses and other losses.
1. I 2 R losses are calculated from the DC resistances of the internal switches, R SW , and external inductor, R L . In continuous mode, the average output current flows through inductor L but is 'chopped' between the internal top and bottom power MOSFETs. Thus, the series resistance looking into the SW pin is a function of both top and bottom MOSFET RDS(ON) and the duty cycle (DC) as follows:
$$R_{SW} = ( R_{DS ( ON ) TOP )} ( DC ) + ( R_{DS ( ON ) BOT} ) ( 1 - DC )$$
*LaTeX transcription of the equation above, checked against the symbols printed on the page.*
The RDS(ON) for both the top and bottom MOSFETs can be obtained from the Typical Performance Characteristics curves. Thus to obtain I 2 R losses:
$$I^2R \text{ losses} = I_{OUT}^2(R_{SW} + R_L)$$
*LaTeX transcription of the equation above, checked against the symbols printed on the page.*
2. The internal LDO draws power from the V IN input to regulate the INTV CC rail. The total power loss here is the sum of the switching losses and quiescent current losses from the control circuitry.
Each time a power MOSFET gate is switched from low to high to low again, a packet of charge dQ moves from V IN to ground. The resulting dQ/dt is a current out of INTV CC that is typically much larger than the DC control bias current.
In continuous mode, I GATECHG = f(Q T + Q B ), where Q T and Q B are the gate charges of the internal top and bottom power MOSFETs and f is the switching frequency. For estimation purposes, the gate charges (Q T + Q B ) on each LTC3636/LTC3636-1 regulator channel are approximately 7.5nC.
To calculate the total power loss from the LDO load, simply add the gate charge current and quiescent current and multiply by the voltage applied to V IN :
$$P_{LDO} = ( I_{GATECHG} + I_{Q} ) \cdot V_{IN}$$
*LaTeX transcription of the equation above, checked against the symbols printed on the page.*
3. Other 'hidden' losses such as transition loss, copper trace resistances, and internal load currents can account for additional efficiency degradations in the overall power system. Transition loss arises from the brief amount of time the top power MOSFET spends in the saturated region during switch node transitions. The LTC3636/LTC3636-1 internal power devices switch quickly enough that these losses are not significant compared to other sources.
Other losses, including diode conduction losses during dead-time and inductor core losses, generally account for less than 2% total additional loss.
### Thermal Considerations
The LTC3636/LTC3636-1 requires the ground pins to be well soldered to the PC board to provide good thermal contact. This gives the QFN package exceptional thermal properties, which is necessary to prevent excessive self heating of the part in normal operation.
In a majority of applications, the LTC3636/LTC3636-1 does not dissipate much heat due to its high efficiency and low thermal resistance of its QFN package. However, in applications where the LTC3636/LTC3636-1 is running at high ambient temperature, high input supply voltage, high switching frequency, and maximum output current load, the heat dissipated may exceed the maximum junction temperature of the part. If the junction temperature reaches approximately 160°C, both power switches will be turned off until temperature returns to 150°C.
To prevent the LTC3636/LTC3636-1 from exceeding the maximum junction temperature of 125°C, the user will need to do some thermal analysis. The goal of the thermal analysis is to determine whether the power dissipated exceeds the maximum junction temperature of the part. The temperature rise is given by:
$$T_{RISE} = P_{D} \cdot \theta_{JA}$$
*LaTeX transcription of the equation above, checked against the symbols printed on the page.*
As an example, consider the case when one of the regulators is used in an application where V IN = 12V, I OUT = 6A, frequency = 1MHz, V OUT = 1.8V. From the R DS(ON) graphs in the Typical Performance Characteristics section, the top switch onresistance is nominally 36mΩ and the bottom switch on -resistance is nominally 19mΩ at 50°C ambient. The equivalent power MOSFET resistance R SW is:
$$R_{DS ( ON ) \text{ROP}} \cdot \frac{1.8 V}{12 V} + R_{DS ( ON ) BOT} \cdot \frac{10.2 V}{12 V} = 21.6 M \omega$$
*LaTeX transcription of the equation above, checked against the symbols printed on the page.*
From the previous section's discussion on gate drive, we estimate the total gate drive current through the LDO to be 1MHz · 7.5nC = 7.5mA, and I Q of one channel is 0.65mA (see Electrical Characteristics ). Therefore, the total power dissipated by a single regulator is:
$$P_{_{D}} = I_{_{OUT}} \,^{2} \cdot R_{_{SW}} + V_{_{IN}} \,^{*} \left( I_{_{GATECHG}} + I_{_{Q}} \right)$$
*LaTeX transcription of the equation above, checked against the symbols printed on the page.*
$$P_{_{D}} = ( 6 A )^{2} \ast ( 0.0216 \Omega ) + ( 12 V ) \cdot ( 7.5 mA + 0.65 mA ) = 0.874 W$$
*LaTeX transcription of the equation above, checked against the symbols printed on the page.*
Running two regulators under the same conditions would result in a power dissipation of 1.748W. The QFN 5mm × 4mm package junction-toambient thermal resistance, θ JA , is around 21°C/W. Therefore, the junction temperature of the regulator operating in a 50°C ambient temperature is approximately:
$$T_{_{J}} = 1.748 W \cdot 21^{\circ} C / W + 50^{\circ} C = 87^{\circ} C$$
*LaTeX transcription of the equation above, checked against the symbols printed on the page.*
which is below the maximum junction temperature of 125°C. With higher ambient temperatures, a heat sink or cooling fan should be considered to drop the junction-to ambient thermal resistance.
Remembering that the above junction temperature is obtained from an R DS(ON) at 50°C, we might recalculate the junction temperature based on a higher R DS(ON) since it increases with temperature. Redoing the calculation assuming that R SW increased 15% at 87°C yields a new junction temperature of 92°C. If the application calls for a higher ambient temperature and/or higher load currents, care should be taken to reduce the temperature rise of the part by using a heat sink or air flow.
Figure 33 is a temperature derating curve based on the DC2335 demo board (QFN package). It can be used to estimate the maximum allowable ambient temperature for given DC load currents in order to avoid exceeding the maximum operating junction temperature of 125°C.
### Board Layout Considerations
When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC3636/LTC3636-1.Check the following in your layout:
1. Do the input capacitors connect to the V IN and GND pins as close as possible? These capacitors provide the AC current to the internal power MOSFETs and their drivers.
2. The output capacitor, C OUT , and inductor L should be closely connected to minimize loss. The ( -) plate of C OUT should be closely connected to both GND and the ( -) plate of C IN .
3. The resistive divider, (e.g. R1 to R4 in Figure 34 ) must be connected between the (+) plate of C OUT and a ground line terminated near GND. The feedback signal V FB should be routed away from noisy components and traces, such as the SW line, and its trace length should be minimized. Keep R1 and R2 close to the IC.
4. Keep sensitive components away from the SW pin. The R T resistor, the compensation components, the feedback resistors, and the INTV CC bypass capacitor should all be routed away from the SW trace and the inductor L.
5. A ground plane is preferred.
6. Flood all unused areas on all layers with copper in order to reduce the temperature rise of power components. These copper areas should be connected to the exposed backside of the package (GND).
Refer to Figure 35 for board layout examples.
### Design Example
As a design example, consider using the LTC3636/ LTC3636-1 in an application with the following specifications: VIN(MAX) = 13.2V, V OUT1 = 1.8V, V OUT2 = 3.3V, I OUT(MAX) = 6A, I OUT(MIN) = 10mA, f = 2MHz, V DROOP ~ (5% · V OUT ). The following discussion will use equations from the previous sections.
Because efficiency is important at both high and low load current, Burst Mode operation will be utilized.
First, the correct R T resistor value for 2MHz switching frequency must be chosen. Based on the equation discussed earlier, R T should be 160k; the closest standard value is 162k. R T can be tied to INTV CC if switching frequency accuracy is not critical.
Next, determine the channel 1 inductor value for about 40% ripple current at maximum V IN :
$$L 1 = \left( \frac{1.8 V}{2 MJz \cdot 2.4 A} \right) \left( 1 - \frac{1.8 V}{13.2 V} \right) = 0.32 \mu H$$
*LaTeX transcription of the equation above, checked against the symbols printed on the page.*
A standard value of 0.33µH should work well here. Solving the same equation for channel 2 results in a 0.47µH inductor.
COUT will be selected based on the charge storage requirement. For a V DROOP of 90mV for a 6A load step:
$$C_{OUT 1} \approx \frac{3 \cdot \Delta I_{OUT}}{f \cdot V_{DROOP}} = \frac{3 \cdot ( 6 A )}{( 2 MHz ) ( 90 mV )} = 100 \mu F$$
*LaTeX transcription of the equation above, checked against the symbols printed on the page.*
Two 47µF ceramic capacitor should be used for channel 1. Solving the same equation for channel 2 (using 5% of VOUT for V DROOP ) results in 55µF of capacitance (47µF is the closest standard value).
CIN should be sized for a maximum current rating of:
$$I_{RMS} = 6 A \frac{\sqrt{1.8 V ( 13.2 V - 1.8 V )}}{13.2 V} = 2.1 A$$
*LaTeX transcription of the equation above, checked against the symbols printed on the page.*
Solving this equation for channel 2 results in an RMS input current of 2.8A. Decoupling each V IN input with a 47µF ceramic capacitor should be adequate for most applications.
Lastly, the feedback resistors must be chosen. Picking R1 and R3 to be 13.7k, R2 and R4 are calculated to be:
$$R 2 = ( 13.7 k ) \cdot \left( \frac{1.8 V}{0.6 V} - 1 \right) = 27.4 k$$
*LaTeX transcription of the equation above, checked against the symbols printed on the page.*
$$R 4 = ( 13.7 k ) \cdot \left( \frac{3.3 V}{0.6 V} - 1 \right) = 61.9 k$$
*LaTeX transcription of the equation above, checked against the symbols printed on the page.*
The final circuit is shown in Figure 34 .
### TYPICAL APPLICATIONS
### PACKAGE DESCRIPTION
### NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
### ORDER INFORMATION
### Table 6. Ordering Guide
**Table 6. Ordering Guide** ([table-05-p31-data.csv](ltc3636/tables/table-05-p31-data.csv), p. 31)
| LEAD FREE FINISH | TAPE AND REEL | PART MARKING* | PACKAGE DESCRIPTION | TEMPERATURE RANGE |
|---|---|---|---|---|
| LTC3636IUFD#PBF | LTC3636IUFD#TRPBF | 3636 | 28-Lead (4mm × 5mm) Plastic QFN | –40°C to 125°C |
| LTC3636EUFD#PBF | LTC3636EUFD#TRPBF | 3636 | 28-Lead (4mm × 5mm) Plastic QFN | –40°C to 125°C |
| LTC3636IUFD-1#PBF | LTC3636IUFD-1#TRPBF | 36361 | 28-Lead (4mm × 5mm) Plastic QFN | –40°C to 125°C |
| LTC3636EUFD-1#PBF | LTC3636EUFD-1#TRPBF | 36361 | 28-Lead (4mm × 5mm) Plastic QFN | –40°C to 125°C |
| **AUTOMOTIVE PRODUCTS**** | | | | |
| LTC3636IUFD#WPBF | LTC3636IUFD#WTRPBF | 3636 | 28-Lead (4mm × 5mm) Plastic QFN | –40°C to 125°C |
| LTC3636EUFD#WPBF | LTC3636EUFD#WTRPBF | 3636 | 28-Lead (4mm × 5mm) Plastic QFN | –40°C to 125°C |
| LTC3636IUFD-1#WPBF | LTC3636IUFD-1#WTRPBF | 36361 | 28-Lead (4mm × 5mm) Plastic QFN | –40°C to 125°C |
| LTC3636EUFD-1#WPBF | LTC3636EUFD-1#WTRPBF | 36361 | 28-Lead (4mm × 5mm) Plastic QFN | –40°C to 125°C |
- **\*:** The temperature grade is identified by a label on the shipping container.
- **\*\*:** Versions of this part are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. These models are designated with a #W suffix. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models.
Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Tape and reel specifications . Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
### SELECTION TABLE
**Selection Table** ([table-06-p31-data.csv](ltc3636/tables/table-06-p31-data.csv), p. 31)
| PART NUMBER | V_OUT SENSE RANGE |
|---|---|
| LTC3636 | 0.6V to 5V |
| LTC3636-1 | 1.8V to 12V |
### REVISION HISTORY
**Revision History** ([table-07-p32-data.csv](ltc3636/tables/table-07-p32-data.csv), p. 32)
| REV | DATE | DESCRIPTION | PAGE NUMBER |
|---|---|---|---|
| A | 07/17 | Revised thermal resistance values in Pin Configurations and Function Descriptions. | 2 |
| A | 07/17 | Revised Thermal Considerations section. | 19, 20 |
| B | 02/18 | Clarified Minimum On-Time. | 3 |
| C | 10/19 | Updated Electrical Characteristics table and Note 2. | 3, 4 |
| C | 10/19 | Edited Dual-Phase Single V_OUT Operation section. | 12 |
| C | 10/19 | Corrected TDK inductor part number. | 13 |
| D | 06/21 | Added AEC-Q100 Qualified for automotive applications. | 1 |
| D | 06/21 | Added W flow part numbers and footnote. | 2 |
| E | 11/22 | AEC-Q100 Qualified for Automotive Applications | 1 |
| E | 11/22 | Added Maximum Reflow Temperature | 2 |
| E | 11/22 | Added LQFN thermal ratings | 2 |
| E | 11/22 | Updated the Order Information | 2 |
| E | 11/22 | Updated INTVCC Voltage and Vfb During Tracking in Electrical Characteristics table | 3, 4 |
| F | 9/24 | Updated Table 1. Electrical Characteristics | 3, 4 |
| F | 9/24 | Updated Absolute Maximum Ratings and Electrostatic Discharge Ratings | 5 |
| F | 9/24 | Updated Pin Configurations and Function Descriptions | 6 |
| F | 9/24 | Updated Figure 4 | 10 |
| F | 9/24 | Updated Order Information | 31 |
### RELATED PARTS
**Related Parts** ([table-08-p33-data.csv](ltc3636/tables/table-08-p33-data.csv), p. 33)
| PART NUMBER | DESCRIPTION | COMMENTS |
|---|---|---|
| LTC3633/ LTC3633A | 15V/20V, Dual 3A (I_OUT), 4MHz Synchronous Step- Down DC/DC Converter | 95% Efficiency, V_IN: 3.6V to 15V, V_OUT(MIN) = 0.6V, I_Q = 500µA, I_SD < 13µA, 4mm × 5mm QFN-28, TSSOP-28E |
| LTC3605/ LTC3605A | 15V/20V, 5A (I_OUT), 4MHz, Synchronous Step-Down DC/DC Converter | 95% Efficiency, V_IN: 4V to 15V, V_OUT(MIN) = 0.6V, I_Q = 2mA, I_SD < 15µA, 4mm × 4mm QFN-24 |
| LTC3603 | 15V, 2.5A (I_OUT), 3MHz, Synchronous Step-Down DC/ DC Converter | 95% Efficiency, V_IN: 4.5V to 15V, V_OUT(MIN) = 0.6V, I_Q = 75µA, I_SD < 1µA, 4mm × 4mm QFN-20, MSOP-16E |
| LTC3601 | 15V, 1.5A (I_OUT), 4MHz, Synchronous Step-Down DC/ DC Converter | 95% Efficiency, V_IN: 4.5V to 15V, V_OUT(MIN) = 0.6V, I_Q = 300µA, I_SD < 1µA, 4mm × 4mm QFN-20, MSOP-16E |
| LTC3604 | 15V, 2.5A (I_OUT), 4MHz, Synchronous Step-Down DC/ DC Converter | 95% Efficiency, V_IN: 3.6V to 15V, V_OUT(MIN) = 0.6V, I_Q = 300µA, I_SD < 15µA, 3mm × 3mm QFN-16, MSOP-16E |
| LTC3626 | 20V, 2.5A Synchronous Monolithic Step- Down Regulator with Current and Temperature Monitoring | 95% Efficiency, V_IN: 3.6V to 20V, V_OUT(MIN) = 0.6V, I_Q = 300µA, I_SD < 15µA, 3mm × 4mm QFN-20 |
| LTC7124 | 17V, Dual 3.5A Synchronous Step-Down Regulator with Ultralow Quiescent Current | 95% Efficiency, V_IN: 3.1V to 17V, V_OUT(MIN) = 0.6V, I_Q < 8µA (Both Channels Enabled), I_SD < 1µA, 3mm × 5mm QFN-24 Package |
| LTC3622 | 17V, Dual 1A Synchronous Step-Down Regulator with Ultralow Quiescent Current | 95% Efficiency, V_IN: 2.7V to 17V, V_OUT(MIN) = 0.6V, I_Q < 5µA (Both Channels Enabled), I_SD < 1µA, 3mm × 4mm DFN-14 and MSOP-16 Packages |
ALL INFORMATION CONTAINED HEREIN IS PROVIDED 'AS IS' WITHOUT REPRESENTATION OR WARRANTY. NO RESPONSIBILITY IS ASSUMED BY ANALOG DEVICES FOR ITS USE, NOR FOR ANY INFRINGEMENTS OF PATENTS OR OTHER RIGHTS OF THIRD PARTIES THAT MAY RESULT FROM ITS USE. SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE. NO LICENCE, EITHER EXPRESSED OR IMPLIED, IS GRANTED UNDER ANY ADI PATENT RIGHT, COPYRIGHT, MASK WORK RIGHT, OR ANY OTHER ADI INTELLECTUAL PROPERTY RIGHT RELATING TO ANY COMBINATION, MACHINE, OR PROCESS, IN WHICH ADI PRODUCTS OR SERVICES ARE USED. TRADEMARKS AND REGISTERED TRADEMARKS ARE THE PROPERTY OF THEIR RESPECTIVE OWNERS. ALL ANALOG DEVICES PRODUCTS CONTAINED HEREIN ARE SUBJECT TO RELEASE AND AVAILABILITY.
## Additional Figures
*Figure 1. Efficiency vs Load Current*
*ESD caution symbol*
*Figure 2. Efficiency vs Load Current Burst Mode Operation*
*Figure 5. Efficiency vs Load Current Burst Mode Operation*
*Figure 8. Load Regulation*
*Figure 11.Internal MOSFET RDS(ON) vs Temperature*
*Figure 3. Efficiency vs Load Current Forced Continuous Mode Operation*
*Figure 6. Efficiency vs Input Voltage Burst Mode Operation*
*Figure 9. Oscillator Frequency vs Temperature*
*Figure 12.Temperature Monitor vs Temperature*
*Figure 4. Efficiency vs Load Current*
*Figure 7. Reference Voltage vs Temperature*
*Figure 10.Oscillator Internal Set Frequency vs Temperature*
*Figure 13.Quiescent Current vs VIN Burst Mode Operation*
*Figure 14.Switch Leakage vs Temperature*
*Figure 17.Shutdown Current vs VIN*
*Figure 20.Load Step (Internal Compensation)*
*Figure 23.Start-Up into Prebiased Output (Burst Mode Operation)*
*Figure 15.Valley Current Limit vs Temperature*
*Figure 18.Burst Mode Operation*
*Figure 21.Start-Up (Burst Mode Operation)*
*Figure 24.Start-Up into Prebiased Output (Forced Continuous Mode)*
*Figure 16.TRACKSS Pull-Up Current vs Temperature*
*Figure 19.Load Step*
*Figure 22.Start-Up (Forced Continuous Mode)*
*Figure 25.Short-Circuit and Soft-Start*
*Figure 26.Switching Frequency vs RT*
*Figure 27.Setting the Output Voltage*
*Figure 28.Compensation Component*
*Figure 29.Two Different Modes of Output Voltage Tracking Coincident Tracking*
*Figure 30.Two Different Modes of Output Voltage Tracking Ratiometric Tracking*
*Figure 31.Setup for Coincident and Ratiometric Tracking*
*Figure 32.PGOOD Pin Behavior*
*Figure 33.Temperature Derating Curve for DC2335 Demo Circuit*
*Figure 34.Design Example Circuit*
*Figure 35.Recommended PCB Layouts -Example of Power Component Layout for QFN Package*
*Figure 36.Recommended PCB Layouts -Alternative Layout with GNDT Pins Connected to GND*
*Figure 37.Recommended PCB Layouts -Alternative Layout with Pins 29 to 34 Unconnected*
*Figure 42.12A 1MHz 2-Phase Buck Regulator*
*RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED*
*Figure 38.1.8V/2.5V 3MHz Buck Regulator*
*Figure 39.3.3V/1.8V Sequenced Regulator with 8V Input UVLO (VOUT1 Enabled After VOUT2)*
*Figure 40.1.2V/1.8V Buck Regulator with Coincident Tracking and 6V Input UVLO*
*Figure 41.Dual Output Regulator from Multiple Input Supplies (Powers VIN1 Before VIN2)*