---
type: Analog Component
title: "LT8350 — 40VIN, 18VOUT, 6A Synchronous Buck-Boost Silent Switcher"
description: "40VIN, 18VOUT, 6A Synchronous Buck-Boost Silent Switcher"
resource: "https://www.analog.com/en/products/lt8350.html"
tags: ["datasheet", "okf-r12-batch1", "linear"]
generated: { by: "agentforge/aa0b0641", at: "2026-09-29T20:23:52Z" }
status: draft
sources:
  - id: "datasheet"
    resource: "https://www.analog.com/media/en/technical-documentation/data-sheets/lt8350.pdf"
    title: "LT8350 data sheet"
    author: "team:analog-devices"
tables:
  - file: "lt8350/tables/table-00-p2-abs_max.csv"
    title: "Absolute Maximum Ratings"
    page: 2
  - file: "lt8350/tables/table-01-p2-data.csv"
    title: "Order Information"
    page: 2
  - file: "lt8350/tables/table-02-p3-spec.csv"
    title: "Electrical Characteristics"
    page: 3
  - file: "lt8350/tables/table-03-p16-data.csv"
    title: "Table 1. Switching Frequency vs RT Value (1% Resistor)"
    page: 16
  - file: "lt8350/tables/table-04-p24-data.csv"
    title: "Revision History"
    page: 24
  - file: "lt8350/tables/table-05-p25-data.csv"
    title: "Related Parts"
    page: 25
figures:
  - file: "lt8350/figures/lt8350-eqx03.png"
    caption: "Equation as printed (p. 20)"
    type: equation
    page: 20
  - file: "lt8350/figures/lt8350-f000.png"
    caption: ""
    type: "application_circuit"
    page: 1
  - file: "lt8350/figures/lt8350-f001.png"
    caption: "Efficiency vs VIN"
    type: "characteristic_curve"
    page: 1
  - file: "lt8350/figures/lt8350-f002.png"
    caption: ""
    type: "pinout"
    page: 2
  - file: "lt8350/figures/lt8350-f003.png"
    caption: "Efficiency vs Load Current (Buck Region)"
    type: "characteristic_curve"
    page: 5
  - file: "lt8350/figures/lt8350-f004.png"
    caption: "Switching Waveforms (Buck Region)"
    type: "scope_capture"
    page: 5
  - file: "lt8350/figures/lt8350-f005.png"
    caption: "VIN  Shutdown Current"
    type: "characteristic_curve"
    page: 5
  - file: "lt8350/figures/lt8350-f006.png"
    caption: "Efficiency vs Load Current (Buck-Boost Region)"
    type: "characteristic_curve"
    page: 5
  - file: "lt8350/figures/lt8350-f007.png"
    caption: "Switching Waveforms (Buck-Boost Region)"
    type: "characteristic_curve"
    page: 5
  - file: "lt8350/figures/lt8350-f008.png"
    caption: "VIN Active Current"
    type: "characteristic_curve"
    page: 5
  - file: "lt8350/figures/lt8350-f009.png"
    caption: "Efficiency vs Load Current (Boost Region)"
    type: "characteristic_curve"
    page: 5
  - file: "lt8350/figures/lt8350-f010.png"
    caption: "Switching Waveforms (Boost Region)"
    type: "characteristic_curve"
    page: 5
  - file: "lt8350/figures/lt8350-f011.png"
    caption: "VREF  Voltage vs Temperature"
    type: "characteristic_curve"
    page: 5
  - file: "lt8350/figures/lt8350-f012.png"
    caption: "EN/UVLO Enable Threshold"
    type: "characteristic_curve"
    page: 6
  - file: "lt8350/figures/lt8350-f013.png"
    caption: "V(ISP-ISN) Regulation vs VCTRL"
    type: "characteristic_curve"
    page: 6
  - file: "lt8350/figures/lt8350-f014.png"
    caption: "V(ISP-ISN) Regulation vs V(FB)"
    type: "characteristic_curve"
    page: 6
  - file: "lt8350/figures/lt8350-f016.png"
    caption: "EN/UVLO Hysteresis Current"
    type: "characteristic_curve"
    page: 6
  - file: "lt8350/figures/lt8350-f017.png"
    caption: "CTRL Off Threshold"
    type: "characteristic_curve"
    page: 6
  - file: "lt8350/figures/lt8350-f018.png"
    caption: "V(ISP-ISN) Regulation vs VISP"
    type: "characteristic_curve"
    page: 6
  - file: "lt8350/figures/lt8350-f019.png"
    caption: "FB Regulation vs Temperature"
    type: "characteristic_curve"
    page: 6
  - file: "lt8350/figures/lt8350-f020.png"
    caption: "V(ISP-ISN) Regulation vs Temperature"
    type: "characteristic_curve"
    page: 6
  - file: "lt8350/figures/lt8350-f021.png"
    caption: "Power Switch RDS(ON)"
    type: "characteristic_curve"
    page: 6
  - file: "lt8350/figures/lt8350-f022.png"
    caption: "Peak Current vs Temperature"
    type: "characteristic_curve"
    page: 7
  - file: "lt8350/figures/lt8350-f023.png"
    caption: "FB Short-Circuit Threshold"
    type: "characteristic_curve"
    page: 7
  - file: "lt8350/figures/lt8350-f024.png"
    caption: "ISMON vs V(ISP-ISN)"
    type: "characteristic_curve"
    page: 7
  - file: "lt8350/figures/lt8350-f025.png"
    caption: "Min On-Time vs Temperature"
    type: "characteristic_curve"
    page: 7
  - file: "lt8350/figures/lt8350-f026.png"
    caption: "Max On-Time vs Temperature"
    type: "characteristic_curve"
    page: 7
  - file: "lt8350/figures/lt8350-f027.png"
    caption: "PGOOD Thresholds"
    type: "characteristic_curve"
    page: 7
  - file: "lt8350/figures/lt8350-f028.png"
    caption: "SS Current vs Temperature"
    type: "characteristic_curve"
    page: 7
  - file: "lt8350/figures/lt8350-f029.png"
    caption: "ISMON vs Temperature"
    type: "characteristic_curve"
    page: 7
  - file: "lt8350/figures/lt8350-f030.png"
    caption: "Frequency vs Temperature"
    type: "characteristic_curve"
    page: 7
  - file: "lt8350/figures/lt8350-f032.png"
    caption: ""
    type: "block_diagram"
    page: 10
  - file: "lt8350/figures/lt8350-f034.png"
    caption: "Figure 1. Power Stage Schematic"
    type: "block_diagram"
    page: 11
  - file: "lt8350/figures/lt8350-f035.png"
    caption: "Figure 2. Current Mode vs V IN /V OUT  Ratio"
    type: "characteristic_curve"
    page: 11
  - file: "lt8350/figures/lt8350-f036.png"
    caption: "Figure 3. Operation Region vs V IN /V OUT  Ratio"
    type: "characteristic_curve"
    page: 11
  - file: "lt8350/figures/lt8350-f037.png"
    caption: "Figure 4. Peak-Buck in Buck Region (V IN  >> V OUT )"
    type: "timing_diagram"
    page: 12
  - file: "lt8350/figures/lt8350-f038.png"
    caption: "Figure 5. Peak-Buck in Buck-Boost Region (V IN  ~> V OUT )"
    type: "timing_diagram"
    page: 12
  - file: "lt8350/figures/lt8350-f039.png"
    caption: "Figure 6. Peak-Boost in Buck-Boost Region (V IN  <~ V OUT )"
    type: "timing_diagram"
    page: 12
  - file: "lt8350/figures/lt8350-f040.png"
    caption: "Figure 7. Peak-Boost in Boost Region (V IN  << V OUT )"
    type: "timing_diagram"
    page: 13
  - file: "lt8350/figures/lt8350-f041.png"
    caption: "Figure 8. Start-Up and Fault Sequence"
    type: "other"
    page: 15
  - file: "lt8350/figures/lt8350-f042.png"
    caption: "Figure 9. Conducted Average EMI (CISPR25)"
    type: "characteristic_curve"
    page: 16
  - file: "lt8350/figures/lt8350-f043.png"
    caption: "Figure 10. Conducted Peak EMI (CISPR25)"
    type: "characteristic_curve"
    page: 16
  - file: "lt8350/figures/lt8350-f044.png"
    caption: "Figure 11. LT8350 Output Currents Resulting 60°C Case Temperature Increase"
    type: "thermal"
    page: 17
  - file: "lt8350/figures/lt8350-f045.png"
    caption: "Figure 12. V IN  Undervoltage Lockout (UVLO)"
    type: "application_circuit"
    page: 19
  - file: "lt8350/figures/lt8350-f046.png"
    caption: "Figure 13. Feedback Resistor Connection"
    type: "application_circuit"
    page: 20
  - file: "lt8350/figures/lt8350-f047.png"
    caption: ""
    type: "application_circuit"
    page: 22
  - file: "lt8350/figures/lt8350-f048.png"
    caption: "Figure 14. 96% Efficient 30W (12V 2.5A), 350kHz Buck-Boost Voltage Regulator"
    type: "characteristic_curve"
    page: 22
  - file: "lt8350/figures/lt8350-f049.png"
    caption: ""
    type: "other"
    page: 23
  - file: "lt8350/figures/lt8350-f052.png"
    caption: "Figure 15. USB-PD Source - 27W 5V, 9V/3A Fixed PDO Mode"
    type: "application_circuit"
    page: 25
  - file: "lt8350/figures/lt8350-f054.png"
    caption: "for common switching frequencies. Table 1. Switching Frequency vs RT Value (1% Resistor)"
    type: "other"
    page: 16
  - file: "lt8350/figures/lt8350-eq01.png"
    caption: "Equation as printed (p. 8)"
    type: equation
    page: 8
  - file: "lt8350/figures/lt8350-eq02.png"
    caption: "Equation as printed (p. 17)"
    type: equation
    page: 17
  - file: "lt8350/figures/lt8350-eq03.png"
    caption: "Equation as printed (p. 18)"
    type: equation
    page: 18
  - file: "lt8350/figures/lt8350-eq04.png"
    caption: "Equation as printed (p. 18)"
    type: equation
    page: 18
  - file: "lt8350/figures/lt8350-eq05.png"
    caption: "Equation as printed (p. 18)"
    type: equation
    page: 18
  - file: "lt8350/figures/lt8350-eq06.png"
    caption: "Equation as printed (p. 18)"
    type: equation
    page: 18
  - file: "lt8350/figures/lt8350-eq07.png"
    caption: "Equation as printed (p. 18)"
    type: equation
    page: 18
  - file: "lt8350/figures/lt8350-eq08.png"
    caption: "Equation as printed (p. 18)"
    type: equation
    page: 18
  - file: "lt8350/figures/lt8350-eq10.png"
    caption: "Equation as printed (p. 19)"
    type: equation
    page: 19
  - file: "lt8350/figures/lt8350-eq11.png"
    caption: "Equation as printed (p. 19)"
    type: equation
    page: 19
  - file: "lt8350/figures/lt8350-eq09.png"
    caption: "Equation as printed (p. 18)"
    type: equation
    page: 18
  - file: "lt8350/figures/lt8350-eq13.png"
    caption: "Equation as printed (p. 19)"
    type: equation
    page: 19
  - file: "lt8350/figures/lt8350-eq14.png"
    caption: "Equation as printed (p. 19)"
    type: equation
    page: 19
  - file: "lt8350/figures/lt8350-eq15.png"
    caption: "Equation as printed (p. 20)"
    type: equation
    page: 20
  - file: "lt8350/figures/lt8350-eq16.png"
    caption: "Equation as printed (p. 20)"
    type: equation
    page: 20
  - file: "lt8350/figures/lt8350-eq17.png"
    caption: "Equation as printed (p. 20)"
    type: equation
    page: 20
agentforge:
  part_number: "LT8350"
  collection: "okf-r12-batch1"
---

# LT8350 — 40VIN, 18VOUT, 6A Synchronous Buck-Boost Silent Switcher

*Datasheet: [LT8350 data sheet (PDF)](https://www.analog.com/media/en/technical-documentation/data-sheets/lt8350.pdf)*

![application circuit (p. 1)](lt8350/figures/lt8350-f000.png)

### FEATURES

- 4-Switch Single Inductor Architecture Allows V IN Above, Below or Equal to V OUT
- Silent Switcher ®  Architecture for Low EMI
- Up to 95% Efficiency at 2MHz
- Proprietary Peak Current Mode
- 3V to 40V Input Voltage Range
- 1V to 18V Output Voltage Range
- ±1.5% Output Voltage Regulation
- Output/Input Current Regulation and Monitor
- Constant-Voltage/Constant-Current Regulation
- High Side PMOS Load Switch Driver
- No Top MOSFET Refresh Noise in Buck or Boost
- 200kHz to 2MHz Fixed Switching Frequency with External Frequency Synchronization and SSFM
- VOUT  Disconnected from V IN  During Shutdown
- Small 4mm × 6mm 32-Pin LQFN Package
- AEC-Q100 Qualified for Automotive Applications

### APPLICATIONS

- Automotive, Industrial, Telecom Systems
- Voltage Regulator with Accurate Current Limit
- High Frequency Battery-Powered System
- USB-PD Source

All registered trademarks and trademarks are the property of their respective owners.

### DESCRIPTION

The LT ® 8350 is a monolithic 4-switch synchronous buckboost converter with Silent Switcher architecture to minimize EMI emissions while delivering high efficiency at high switching frequency. The switcher can regulate the output voltage, input or output current from input voltages above, below, or equal to the output voltage. The proprietary peak current mode control scheme allows adjustable and synchronizable 200kHz to 2MHz fixed frequency operation, or spread spectrum frequency modulation (SSFM) operation. With 3V to 40V input voltage range, 1V to 18V output voltage capability, and seamless low noise transitions between operation regions, the LT8350 is ideal for voltage regulator , battery and supercapacitor charger applications in automotive, industrial, telecom, and battery powered systems.

The LT8350 provides input or output current monitor and power good flag. Robust fault protection is provided to detect output short-circuit condition, during which the LT8350 retries, latches off, or keeps running.

![Efficiency vs VIN](lt8350/figures/lt8350-f001.png)

*Efficiency vs VIN*

### TYPICAL APPLICATION

95% Efficient 24W (12V, 2A) 2MHz Buck-Boost Voltage Regulator with Output Current Limit

![pinout (p. 2)](lt8350/figures/lt8350-f002.png)

### ABSOLUTE MAXIMUM RATINGS (Note 1)

**Absolute Maximum Ratings** ([table-00-p2-abs_max.csv](lt8350/tables/table-00-p2-abs_max.csv), p. 2)

| PARAMETER | RATING |
|---|---|
| V_IN, EN/UVLO, ISP, ISN | −0.3V to 42V |
| V_OUT, EXTV_CC | −0.3V to 20V |
| SW1 | −0.3V to 42V |
| SW2 | −0.3V to 20V |
| BST1 | 47V |
| BST2 | 25V |
| BST1–SW1, BST2–SW2, INTV_CC | −0.3V to 5V |
| CTRL, FB, LOADEN, SYNC/MODE, P̅G̅O̅O̅D̅ | −0.3V to 5V |
| ISMON, V_C, RT | −0.3V to 5V |
| SS, V_REF | −0.3V to 4V |
| ISP–ISN | −1V to 1V |
| CLKOUT, LOADTG | (Note 2) |
| Operating Junction Temperature Range (Notes 3, 4) |  |
| LT8350R | −40°C to 150°C |
| Storage Temperature Range | −65°C to 150°C |

### ORDER INFORMATION

**Order Information** ([table-01-p2-data.csv](lt8350/tables/table-01-p2-data.csv), p. 2)

| PART NUMBER | PAD OR BALL FINISH | DEVICE | FINISH CODE | PACKAGE TYPE** | MSL RATING | TEMPERATURE RANGE |
|---|---|---|---|---|---|---|
| LT8350RV#PBF | Au (RoHS) | 8350 | e4 | LQFN (Laminate Package with QFN Footprint) | 3 | –40°C to 150°C |
| **AUTOMOTIVE PRODUCTS***** |  |  |  |  |  |  |
| LT8350RV#WPBF | Au (RoHS) | 8350 | e4 | LQFN (Laminate Package with QFN Footprint) | 3 | –40°C to 150°C |

- **\*:** Pad or ball finish code is per IPC/JEDEC J-STD-609.
- **\*\*:** The LT8350 package has the same footprint as a standard 4mm × 6mm QFN package.
- ***: Versions of this part are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. These models are designated with a #W suffix. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models.

-  Contact the factory for parts specified with wider operating temperature ranges. *Pad or ball finish code is per IPC/JEDEC J-STD-609.
- [ Recommended LGA and BGA PCB Assembly and Manufacturing Procedures](https://www.analog.com/en/products/landing-pages/001/umodule-design-manufacturing-resources.html#manufacturing?doc=LT8350.pdf)

- [ LGA and BGA Package and Tray Drawings](https://www.analog.com/en/design-center/packaging-quality-symbols-footprints.html?doc=LT8350-8350S.pdf)

### PIN CONFIGURATION

![Efficiency vs Load Current (Buck Region)](lt8350/figures/lt8350-f003.png)

*Efficiency vs Load Current (Buck Region)*

### ELECTRICAL CHARACTERISTICS

● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T A  = 25°C. V IN  = 12V, V EN/UVLO  = 1.5V, unless otherwise noted.

**Electrical Characteristics** ([table-02-p3-spec.csv](lt8350/tables/table-02-p3-spec.csv), p. 3)

| PARAMETER | CONDITIONS | MIN | TYP | MAX | UNITS | OVERTEMP |
|---|---|---|---|---|---|---|
| **Input and Output** |  |  |  |  |  |  |
| **Input and Output** |  |  |  |  |  |  |
| V_IN Operating Voltage Range |  | 3 |  | 40 | V | ● |
| V_IN Shutdown Current | V_EN/UVLO = 0.3V |  | 2 | 5 | µA |  |
| V_IN Active Current (Not Switching) | V_EN/UVLO = 1.5V, EXTV_CC = 0V |  | 3.5 | 5 | mA |  |
| V_IN Active Current (Not Switching) | V_EN/UVLO = 1.5V, EXTV_CC = 5V |  | 400 | 650 | µA |  |
| EXTV_CC Voltage Range |  | 1 |  | 18 | V | ● |
| V_OUT Voltage Range |  | 0 |  | 18 | V | ● |
| EN/UVLO Shutdown Threshold | Falling | 0.3 | 0.6 | 0.9 | V |  |
| EN/UVLO Enable Threshold | Falling | 1.196 | 1.220 | 1.244 | V | ● |
| EN/UVLO Enable Hysteresis |  |  | 15 |  | mV |  |
| EN/UVLO Hysteresis Current | V_EN/UVLO = 1.1V | 2.1 | 2.5 | 2.9 | µA |  |
| EN/UVLO Hysteresis Current | V_EN/UVLO = 1.5V | −0.1 | 0 | 0.1 | µA |  |
| **Linear Regulators** |  |  |  |  |  |  |
| **Linear Regulators** |  |  |  |  |  |  |
| INTV_CC Regulation Voltage | I_INTVCC = 20mA | 3.4 | 3.6 | 3.8 | V |  |
| V_REF Regulation Voltage | I_VREF = 100µA | 1.97 | 2.00 | 2.03 | V | ● |
| **Current Regulation Loop** |  |  |  |  |  |  |
| **Current Regulation Loop** |  |  |  |  |  |  |
| Full-Scale Current Regulation V_(ISP-ISN) | V_CTRL = 2V, V_ISP = 12V | 94 | 100 | 103 | mV | ● |
| Full-Scale Current Regulation V_(ISP-ISN) | V_CTRL = 2V, V_ISP = 0V | 94 | 100 | 103 | mV | ● |
| ISP/ISN Input Common Mode Range |  | 0 |  | 40 | V | ● |
| ISP/ISN Current Regulation Amplifier g_m |  |  | 2300 |  | µS |  |
| **Voltage Regulation Loop** |  |  |  |  |  |  |
| **Voltage Regulation Loop** |  |  |  |  |  |  |
| FB Pin Current | FB in Regulation, Current Out of Pin |  | 35 | 80 | nA |  |
| FB Regulation Voltage | V_C = 0.8V | 0.985 | 1.00 | 1.015 | V | ● |
| FB Line Regulation | V_IN = 3V to 40V |  | 0.02 | 0.2 | % |  |
| FB Load Regulation |  |  | 0.02 | 0.1 | % |  |
| FB Voltage Regulation Amplifier g_m |  |  | 580 |  | µS |  |
| V_C Output Impedance |  |  | 10 |  | MΩ |  |
| **Power Switches** |  |  |  |  |  |  |
| **Power Switches** |  |  |  |  |  |  |
| Maximum Switch Current Limit | Peak-Boost Current Mode | 6.3 | 7.0 | 7.7 | A |  |
| Maximum Switch Current Limit | Peak-Buck Current Mode | 5.8 | 7.0 | 8.0 | A |  |
| Switch A On-Resistance (From V_IN to SW1) | I_SW = 1A |  | 50 |  | mΩ |  |
| Switch B On-Resistance (From SW1 to GND) | I_SW = 1A |  | 50 |  | mΩ |  |
| Switch C On-Resistance (From SW2 to GND) | I_SW = 1A |  | 30 |  | mΩ |  |
| Switch D On-Resistance (From V_OUT to SW2) | I_SW = 1A |  | 30 |  | mΩ |  |
| **Oscillator** |  |  |  |  |  |  |
| **Oscillator** |  |  |  |  |  |  |
| Switching Frequency | V_SYNC/MODE = 0V, R_T = 14.3kΩ | 1900 | 2000 | 2100 | kHz | ● |
| Switching Frequency | V_SYNC/MODE = 0V, R_T = 178kΩ | 260 | 290 | 320 | kHz |  |
| SYNC Frequency |  | 200 |  | 2000 | kHz |  |
| SYNC/MODE Threshold Voltage |  | 0.4 |  | 1.5 | V |  |
| Spread Spectrum Above Oscillator Frequency | V_SYNC/MODE = 3.6V | 20 | 23 | 26 | % |  |
| **Fault** |  |  |  |  |  |  |
| **Fault** |  |  |  |  |  |  |
| FB Short Threshold (V_FB) | Falling | 0.23 | 0.25 | 0.27 | V |  |
| FB Short Hysteresis |  | 38 | 50 | 62 | mV |  |
| ISP/ISN Over Current Threshold V_(ISP-ISN) | V_ISP = 12V |  | 750 |  | mV |  |
| P̅G̅O̅O̅D̅ Upper Threshold Offset from V_FB | Rising | 8 | 10 | 12 | % |  |
| P̅G̅O̅O̅D̅ Lower Threshold Offset from V_FB | Falling | −12 | −10 | −8 | % |  |
| P̅G̅O̅O̅D̅ Pull-Down Resistance |  |  | 130 | 200 | Ω |  |
| SS Hard Pull-Down Resistance |  |  | 130 | 200 | Ω |  |
| SS Pull-Up Current | V_FB = 0.8V, V_SS = 0V | 10.5 | 12.5 | 14.5 | µA |  |
| SS Pull-Down Current | V_FB = 1V, V_SS = 2V | 1.0 | 1.25 | 1.5 | µA |  |
| SS Fault Latch-Off Threshold |  |  | 1.75 |  | V |  |
| SS Fault Reset Threshold |  |  | 0.2 |  | V |  |
| **Output Current Monitor** |  |  |  |  |  |  |
| **Output Current Monitor** |  |  |  |  |  |  |
| ISMON Voltage | V_(ISP-ISN) = 100mV, V_ISP = 12V/0V | 1.21 | 1.25 | 1.29 | V |  |
| ISMON Voltage | V_(ISP-ISN) = 0mV, V_ISP = 12V/0V | 0.22 | 0.25 | 0.28 | V |  |
| **Load Switch Driver** |  |  |  |  |  |  |
| **Load Switch Driver** |  |  |  |  |  |  |
| LOADEN Threshold | Rising |  | 1.5 |  | V |  |
| LOADEN Hysteresis |  |  | 540 |  | mV |  |
| Minimum V_OUT for LOADTG to be On | V_LOADEN = 5V |  | 3 | 4.0 | V |  |
| LOADTG On Voltage V_(VOUT-LOADTG) | V_OUT = 12V | 4.5 | 5 | 5.5 | V |  |
| LOADTG Off Voltage V_(VOUT-LOADTG) | V_OUT = 12V | −0.1 | 0 | 0.1 | V |  |

*OVERTEMP: ● marks a limit specified over the full operating temperature range; a blank cell means the limit is specified at T<sub>A</sub> = 25°C only.*

- **Note 1:** Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime.

- **Note 2:** Do not apply a positive or negative voltage source to these pins, otherwise permanent damage may occur .

- **Note 3:** The LT8350R is specified over the -40°C to 150°C operating junction temperature range. High Junction temperatures degrade operating lifetimes. Note the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors.

- **Note 4:** The LT8350 includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 150°C when overtemperature protection is active. Continuous operation above the specified absolute maximum operating junction temperature may impair device reliability or permanently damage the device.

### TYPICAL PERFORMANCE CHARACTERISTICS

![Switching Waveforms (Buck Region)](lt8350/figures/lt8350-f004.png)

*Switching Waveforms (Buck Region)*

![VIN  Shutdown Current](lt8350/figures/lt8350-f005.png)

*VIN  Shutdown Current*

![Efficiency vs Load Current (Buck-Boost Region)](lt8350/figures/lt8350-f006.png)

*Efficiency vs Load Current (Buck-Boost Region)*

T A  = 25°C, unless otherwise noted.

![Switching Waveforms (Buck-Boost Region)](lt8350/figures/lt8350-f007.png)

*Switching Waveforms (Buck-Boost Region)*

![VIN Active Current](lt8350/figures/lt8350-f008.png)

*VIN Active Current*

![Efficiency vs Load Current (Boost Region)](lt8350/figures/lt8350-f009.png)

*Efficiency vs Load Current (Boost Region)*

![Switching Waveforms (Boost Region)](lt8350/figures/lt8350-f010.png)

*Switching Waveforms (Boost Region)*

![VREF  Voltage vs Temperature](lt8350/figures/lt8350-f011.png)

*VREF  Voltage vs Temperature*

![EN/UVLO Enable Threshold](lt8350/figures/lt8350-f012.png)

*EN/UVLO Enable Threshold*

![V(ISP-ISN) Regulation vs VCTRL](lt8350/figures/lt8350-f013.png)

*V(ISP-ISN) Regulation vs VCTRL*

![V(ISP-ISN) Regulation vs V(FB)](lt8350/figures/lt8350-f014.png)

*V(ISP-ISN) Regulation vs V(FB)*

![EN/UVLO Hysteresis Current](lt8350/figures/lt8350-f016.png)

*EN/UVLO Hysteresis Current*

T A  = 25°C, unless otherwise noted.

![CTRL Off Threshold](lt8350/figures/lt8350-f017.png)

*CTRL Off Threshold*

![V(ISP-ISN) Regulation vs VISP](lt8350/figures/lt8350-f018.png)

*V(ISP-ISN) Regulation vs VISP*

![FB Regulation vs Temperature](lt8350/figures/lt8350-f019.png)

*FB Regulation vs Temperature*

![V(ISP-ISN) Regulation vs Temperature](lt8350/figures/lt8350-f020.png)

*V(ISP-ISN) Regulation vs Temperature*

![Power Switch RDS(ON)](lt8350/figures/lt8350-f021.png)

*Power Switch RDS(ON)*

![Peak Current vs Temperature](lt8350/figures/lt8350-f022.png)

*Peak Current vs Temperature*

![FB Short-Circuit Threshold](lt8350/figures/lt8350-f023.png)

*FB Short-Circuit Threshold*

![ISMON vs V(ISP-ISN)](lt8350/figures/lt8350-f024.png)

*ISMON vs V(ISP-ISN)*

![Min On-Time vs Temperature](lt8350/figures/lt8350-f025.png)

*Min On-Time vs Temperature*

T A  = 25°C, unless otherwise noted.

![Max On-Time vs Temperature](lt8350/figures/lt8350-f026.png)

*Max On-Time vs Temperature*

![PGOOD Thresholds](lt8350/figures/lt8350-f027.png)

*PGOOD Thresholds*

![SS Current vs Temperature](lt8350/figures/lt8350-f028.png)

*SS Current vs Temperature*

![ISMON vs Temperature](lt8350/figures/lt8350-f029.png)

*ISMON vs Temperature*

![Frequency vs Temperature](lt8350/figures/lt8350-f030.png)

*Frequency vs Temperature*


### PIN FUNCTIONS

VIN  (Pin 2, 3): Input Voltage Pin. The V IN  pin supplies the internal circuitry and connects to the power input of the converter . Bypass this pin to ground with a ceramic capacitor .  The  bypass  capacitor  should  be  placed  as close to the chip as possible with vias directly down to the ground plane.

EN/UVLO  (Pin  5): Enable  and  Undervoltage  Lockout Pin. Force the pin below 0.3V to shut down the chip and reduce V IN  quiescent current below 2µA. Force the pin above 1.235V (typical) for normal operation. The accurate 1.220V falling threshold can be used to program an undervoltage lockout (UVLO) threshold with a resistor divider from V IN  to ground. An accurate 2.5µA pull-down current allows the programming of V IN  UVLO hysteresis. If neither function is used, tie this pin directly to V IN .

INTV CC  (Pin 6): Internal 3.6V Linear Regulator Output Pin. Powered from the V IN  pin, the INTV CC  supplies the internal control circuitry and gate drivers. Do not force any voltage on this pin. Place a 1µF bypass capacitor to GND close to the package.

RP (Pin 7): Factory Test Pin. Always tie this pin to INTV CC .

LOADEN (Pin 8): Load Switch Enable Input. The LOADEN pin is used to control the ON/OFF of the high side PMOS load switch. If the load switch control is not used, tie this pin to V REF  or INTV CC .  Forcing the pin low turns off all power switches, disconnects the V C  pin from all internal loads, and turns off LOADTG.

VREF  (Pin 9): Voltage Reference Output Pin. The V REF  pin provides an accurate 2V reference capable of supplying up to 2mA current. It can be used to supply resistor networks for setting the voltages at the CTRL pin. Place a 220nF bypass capacitor to GND close to the package.

ISMON (Pin 10): ISP/ISN Current Monitor Output Pin. The ISMON pin generates a buffered voltage that is equal to ten times V (ISP-ISN)  plus 0.25V offset voltage. The voltage on the ISMON pin will be 1.25V when V (ISP-ISN)  is equal to 100mV full-scale.

ISP (Pin 11): Positive Terminal of ISP/ISN Current Sense Resistor (R IS ). Ensure accurate current sense with Kelvin connection.

ISN  (Pin  12): Negative  Terminal  of  ISP/ISN  Current Sense Resistor (R IS ). Ensure accurate current sense with Kelvin connection.

CTRL (Pin 13): Control Input for ISP/ISN Current Sense Threshold. The CTRL pin is used to program the ISP/ISN regulation current:

![Equation as printed (p. 8)](lt8350/figures/lt8350-eq01.png)

$$I_{IS ( MAX )} = \frac{\min ( V_{CTRL} - 0.25 V , 1 V )}{10 \cdot R_{IS}}$$

*LaTeX transcription of the equation above, checked against the symbols printed on the page.*

The V CTRL  can be set by an external voltage reference or a resistor divider from V REF  to ground. For 0.25V ≤ VCTRL  ≤ 1.15V, the current sense threshold linearly goes up from 0mV to 90mV. For V CTRL  ≥ 1.35V, the current sense threshold is constant at 100mV full-scale value. For 1.15V ≤ V CTRL  ≤ 1.35V, the current sense threshold smoothly transitions from the linear function of V CTRL  to the 100mV constant value. Tie CTRL pin to V REF  for the 100mV full-scale threshold. Force the pin below 0.1V to stop switching.

FB (Pin 14): Voltage Loop Feedback Input. The FB pin is used for constant-voltage regulation and output fault protection. The internal error amplifier with its output V C regulates V FB  to 1V through the DC/DC converter . During the output short-circuit (V FB < 0.25V) fault condition, the part gets into one fault mode per customer setting. During an overvoltage (V FB  > 1.1V) condition, the part turns off all power switches and LOADTG.

VC  (Pin 15): Error Amplifier Output to Set Inductor Current Comparator Threshold. The V C  pin is used to compensate the control loop with an external RC network. During LOADEN low state, the V C  pin is disconnected from all internal loads to store its voltage information.

PGOOD (Pin 16): Power Good Open Drain Output. The PGOOD pin is pulled low when the FB pin is within ±10% of the final regulation voltage. To function, this pin requires an external pull-up resistor .

SS (Pin 17): Soft-Start Timer Setting. The SS pin is used to set soft-start timer by connecting a capacitor to ground. An internal 12.5µA pull-up current charging the external SS capacitor gradually ramps up FB regulation voltage. A

22nF capacitor is recommended on this pin. Any UVLO or thermal shutdown immediately pulls SS pin to ground and stops switching. Using a single resistor from SS to V REF , the LT8350 can be set in three different fault modes during output short-circuit fault condition: hiccup (no resistor), latch-off (499k), and keep-running (100k). See more details in the Applications Information section.

RT (Pin 18): Switching Frequency Setting. Connect a resistor from this pin to ground to set the internal oscillator frequency from 200kHz to 2MHz.

SYNC/MODE (Pin 19): External  Switching  Frequency Synchronization  and  Operation  Mode  Selection.  This pin  allows  five  selectable  modes  for  optimization  of performance:

1. External Clock: For external frequency synchronization and force continuous mode at light load.
2. INTV CC : For spread spectrum frequency modulation and force continuous mode at light load.
3. V REF : For spread spectrum frequency modulation and pulse-skipping mode at light load.
4. Float: For internal oscillator frequency and force continuous mode at light load.
5. GND: For internal oscillator frequency and pulse-skipping mode at light load.

CLKOUT (Pin 20): Clock output. The CLKOUT pin provides a 50% duty cycle square wave with 180 degrees out of phase with the system clock. This allows synchronization with other regulators. Float this pin if the CLKOUT function is not used.

EXTVCC   (Pin  21): Second  Input  Supply  for  Powering INTV CC . The part intelligently chooses either V IN or EXTV CC for INTV CC  LDO to improve efficiency. See EXTV CC  connection in the Applications Information section. Tie this pin to GND if not used.

LOADTG (Pin 22): High Side PMOS Load Switch Top Gate Drive. The LOADTG pin produces a buffered and inverted version of the LOADEN input signal and drives an external high side PMOS load switch with a voltage swing from the higher voltage between (V OUT -5V) and 1.2V to V OUT . Leave this pin open if not used.

VOUT  (Pin 24, 25): Power Output. The V OUT  pins connect to the power output of the converter , and also serve as the positive rail for the LOADTG drive. Bypass this pin to ground with a ceramic capacitor . The bypass capacitor should be placed as close to the chip as possible with vias directly down to the ground plane.

SW2 (Pin 27, 28): Boost Side Switch Node. The SW2 pins connect to the internal power switches, and swing from ground to a diode voltage above V OUT . Do not force any voltage on these pins.

BST2 (Pin  29): Boost  Side  Bootstrap  Floating  Driver Supply. The BST2 pin connects to an integrated bootstrap diode from the INTV CC  pin and supplies the boost side top power switch gate driver . Place a 100nF bypass capacitor to SW2 close to the package.

BST1  (Pin  30): Buck  Side  Bootstrap  Floating  Driver Supply. The BST1 pin connects to an integrated bootstrap diode from the INTV CC  pin and supplies the buck side top power switch gate driver . Place a 100nF bypass capacitor to SW1 close to the package.

SW1 (Pin 31, 32): Buck Side Switch Node. The SW1 pins connect to the internal power switches, and swing from a diode voltage drop below ground up to V IN . Do not force any voltage on these pins.

GND (Exposed Pad Pins 33, 34, 35, 36): Ground. Solder the exposed pads directly to the ground plane.

Corner Pins: These pins are for mechanical support only and can be tied anywhere on the PCB.

![block diagram (p. 10)](lt8350/figures/lt8350-f032.png)

### BLOCK DIAGRAM

![Figure 1. Power Stage Schematic](lt8350/figures/lt8350-f034.png)

*Figure 1. Power Stage Schematic*

### OPERATION

The LT8350 is a current mode DC/DC converter that can regulate output voltage from input voltage above, below, or equal to the output voltage. Four internal low resistance N-channel  DMOS  switches  minimize  the  size  of  the application circuit and reduce power losses to maximize efficiency. Internal high side gate drivers, further simplify the design process. The ADI proprietary peak current mode control scheme directly senses the inductor current across the internal power switches and provides smooth transition between buck region, buck-boost region, and boost region. The LT8350 can be configured to operate over a wide range of switching frequencies, from 200kHz to 2MHz, allowing applications to be optimized for broad area and efficiency. The operation can be best understood by referring to the Block Diagram.

### Power Switch Control

Figure 1 shows the topology of the LT8350 power stage which is comprised of four N-channel DMOS switches and their associated gate drivers. Figure 2 shows the current mode control as a function of V IN /V OUT ratio and Figure 3 shows the operation region as a function of V IN /V OUT  ratio. The power switches are properly controlled to smoothly transition  between  modes  and  regions.  Hysteresis  is added to prevent chattering between modes and regions.

![Figure 2. Current Mode vs V IN /V OUT  Ratio](lt8350/figures/lt8350-f035.png)

*Figure 2. Current Mode vs V IN /V OUT  Ratio*

There are total four states: (1) peak-buck current mode control in buck region, (2) peak-buck current mode control in buck-boost region, (3) peak-boost current mode control in buck-boost region, and (4) peak-boost current mode control in boost region. The following sections give detailed description for each state with waveforms, in which the shoot-through protection dead time between switches A and B, between switches C and D are ignored for simplification.

![Figure 3. Operation Region vs V IN /V OUT  Ratio](lt8350/figures/lt8350-f036.png)

*Figure 3. Operation Region vs V IN /V OUT  Ratio*

![Figure 4. Peak-Buck in Buck Region (V IN  >> V OUT )](lt8350/figures/lt8350-f037.png)

*Figure 4. Peak-Buck in Buck Region (V IN  >> V OUT )*

### (1) Peak-Buck in Buck Region (V IN  >> V OUT )

When VIN  is much higher than V OUT , the LT8350 uses peak-buck current mode control in buck region (Figure 4). Switch C is always off and switch D is always on. At the beginning of every cycle, switch A is turned on and the inductor current ramps up. When the inductor current hits the peak buck current threshold commanded by V C  voltage at buck current comparator A1 during (A+D) phase, switch A is turned off and switch B is turned on for the rest of the cycle. Switches A and B will alternate, behaving like a typical synchronous buck regulator .

![Figure 5. Peak-Buck in Buck-Boost Region (V IN  ~> V OUT )](lt8350/figures/lt8350-f038.png)

*Figure 5. Peak-Buck in Buck-Boost Region (V IN  ~> V OUT )*

### (2) Peak-Buck in Buck-Boost Region (V IN  ~> V OUT )

When VIN  is slightly higher than V OUT , the LT8350 uses peak-buck current mode control in buck-boost region (Figure 5). In each switching cycle, switch C is turned on for the beginning 20% cycle and switch D is turned on for the remaining 80% cycle. At the beginning of every cycle, switches A and C are turned on and the inductor current ramps up. After 20% cycle, switch C is turned off and switch D is turned on, and the inductor keeps ramping up. When the inductor current hits the peak buck current threshold commanded by V C  voltage at buck current comparator A1 during (A+D) phase, switch A is turned off and switch B is turned on for the rest of the cycle.

![Figure 6. Peak-Boost in Buck-Boost Region (V IN  <~ V OUT )](lt8350/figures/lt8350-f039.png)

*Figure 6. Peak-Boost in Buck-Boost Region (V IN  <~ V OUT )*

### (3) Peak-Boost in Buck-Boost Region (V IN  &lt;~ V OUT )

When VIN  is slightly lower than V OUT , the LT8350 uses peak-boost current mode control in buck-boost region (Figure 6). In each switching cycle, switch A is turned on for the beginning 80% cycle and switch B is turned on for the remaining 20% cycle. At the beginning of every cycle,

![Figure 7. Peak-Boost in Boost Region (V IN  << V OUT )](lt8350/figures/lt8350-f040.png)

*Figure 7. Peak-Boost in Boost Region (V IN  << V OUT )*

switches A and C are turned on and the inductor current ramps up. When the inductor current hits the peak boost current threshold commanded by V C  voltage at boost current comparator A2 during (A+C) phase, switch C is turned off and switch D is turned on for the rest of the cycle. After 80% cycle, switch A is turned off and switch B is turned on for the rest of the cycle.

### (4) Peak-Boost in Boost Region (V IN  << V OUT )

When V IN  is much lower than V OUT , the LT8350 uses peakboost current mode control in boost region (Figure 7). Switch A is always on and switch B is always off. At the beginning of every cycle, switch C is turned on and the inductor current ramps up. When the inductor current hits the peak boost current threshold commanded by V C  voltage at boost current comparator A2 during (A+C) phase, switch C is turned off and switch D is turned on for the rest of the cycle. Switches C and D will alternate, behaving like a typical synchronous boost regulator .

![Figure 8. Start-Up and Fault Sequence](lt8350/figures/lt8350-f041.png)

*Figure 8. Start-Up and Fault Sequence*

### Main Control Loop

The LT8350 is a fixed frequency current mode DC/DC converter . The inductor current is directly sensed across the internal switch A. The current sense voltage is added to a slope compensation ramp signal from the internal oscillator . The summing signal is then fed into the positive terminals of the buck current comparator A1 and boost current comparator A2. The negative terminals of A1 and A2 are controlled by the voltage on the V C  pin, which is the diode-OR of error amplifiers EA1 and EA2.

Depending on the state of the peak-buck peak-boost current mode control, either the buck logic or the boost logic is controlling the four power switches so that either the FB voltage is regulated to 1V or the current sense voltage between the ISP and ISN pins is regulated by the CTRL pin during normal operation. The gains of EA1 and EA2 have been balanced to ensure smooth transition between constant-voltage and constant-current operation with the same compensation network.

### Light Load Current Operation

At light load, the LT8350 can be configurated to operate in forced continuous conduction mode or discontinuous conduction mode.

In force continuous conduction mode, the LT8350 runs at their full switching frequency.

In discontinuous conduction mode, both buck and boost reverse current sense thresholds are set to be positive, thus preventing any reverse current flowing from the output to the input. In the buck region, switch B is turned off whenever the buck reverse current threshold is triggered during (B+D) phase. In the boost region, switch D is turned off whenever the boost reverse current threshold is triggered during (A+D) phase. In the buck-boost

region, switch D is turned off whenever the boost reverse current threshold is triggered during (A+D) phase, and both switches B and D are turned off whenever the buck reverse current threshold is triggered during (B+D) phase. As the load becomes lower and lower , or when a smaller value inductor is used and the inductor current ripple is bigger , the LT8350 may run in pulse-skipping mode, where the switches are held off for multiple cycles (i.e., skipping pulses) to maintain the regulation.

### Internal Charge Path

Each of the two high side gate drivers is biased from its floating bootstrap capacitor C BST1  and C BST2 , which is normally recharged by INTV CC  through the integrated bootstrap  diode  D1  and  D2  when  the  bottom  power switches are turned on. When the LT8350 operates exclusively in the buck or boost regions, one of the top power switches is constantly on. Internal charge paths, from VOUT  and BST2 to BST1, or from V IN  and BST1 to BST2, charge the bootstrap capacitors to above 3.3V so that the top power switch can be kept on.

### Shutdown and Power-On-Reset

The LT8350 enters shutdown mode and drains less than 2µA (typical) quiescent current when the EN/UVLO pin is below its shutdown threshold (0.3V minimum). Once the EN/UVLO pin is above its shutdown threshold (0.9V maximum), the LT8350 wakes up startup circuitry, generates bandgap reference, and powers up the internal INTV CC LDO. The INTV CC  LDO supplies the internal control circuitry and gate drivers. Now the LT8350 enters undervoltage lockout (UVLO) mode with a hysteresis current (2.5µA typical) pulled into the EN/UVLO pin. When the INTV CC  pin is charged above its rising UVLO threshold (2.52V typical), and the EN/UVLO pin passes its rising enable threshold (1.235V typical), and the junction temperature is less than its thermal shutdown (165°C typical), the LT8350 enters enable mode, in which the EN/UVLO hysteresis current is turned off and V REF  is being charged up from ground. From the time of entering enable mode to the time of V REF  passing its rising UVLO threshold (1.89V typical), the LT8350 is going through a power-on-reset (POR), waking up the entire internal control circuitry and settling to the right initial conditions. After the POR, the LT8350 is ready and waiting for the signals on the CTRL and LOADEN pins to start switching.

### Start-Up and Fault Protection

Figure 8 shows the start-up and fault sequence for the LT8350. During the POR state, the SS pin is hard pulled down with a 130Ω to ground. In a pre-biased condition, the SS pin has to be pulled below 0.2V to enter the INIT state, where the LT8350 waits 10µs so that the SS pin can be fully discharged to ground. After the 10µs, the LT8350 enters the UP/PRE state when the LOADON signal goes high. The LOADON high signal happens when CTRL pin is above its CTRL OFF thresholds (0.225V typical) and the LOADEN is high.

During the UP/PRE state, the SS pin is charged up by a 12.5µA pull-up current while the switching is disabled and the LOADTG is turned off. Once the SS pin is charged above 0.25V, the LT8350 enters the UP/TRY state, where the LOADTG is turned on first while the switching is still disabled.  If  an  excessive  current  flowing  through  the current sense resistor triggers the ISP/ISN over current (ISOC) signal, it will reset the LT8350 back into the POR state. After 10µs in the UP/TRY state without triggering the ISOC signal, the LT8350 enters the UP/RUN state.

During the UP/RUN state, the switching is enabled and the start-up of the output voltage V OUT  is controlled by the voltage on the SS pin. When the SS pin voltage is less than 1V, the LT8350 regulates the FB pin voltage to the SS pin voltage instead of the 1V reference. This allows the SS pin to be used to program soft-start by connecting an external capacitor from the SS pin to GND. The internal 12.5µA pull-up current charges up the capacitor , creating a voltage ramp on the SS pin. As the SS pin voltage rises

linearly from 0.25V to 1V (and beyond), the output voltage VOUT  rises smoothly to its final regulation voltage.

Once the SS pin is charged above 1.75V, the LT8350 enters the OK/RUN state, where the output short detection is activated. The output short means that V FB < 0.25V. When the output short happens, the LT8350 enters the FAULT/RUN state,  where  a  1.25µA  pull-down  current slowly discharges the SS pin with the other conditions the same as the OK/RUN state. Once the SS pin is discharged below 1.7V, the LT8350 enters the DOWN/STOP state and the short detection is deactivated with the previous fault latched. Once the SS pin is discharged below 0.2V and the LOADON signal is still high, the LT8350 goes back to the UP/RUN state.

In output short condition, the LT8350 can be set to hiccup, latch-off, or keep-running fault protection mode with a resistor between the SS and V REF  pins. Without any resistor , the LT8350 will hiccup between 0.2V and 1.75V and go around the UP/RUN, OK/RUN, FAULT/RUN, and DOWN/STOP states until the fault condition is cleared. With a 499kΩ resistor , the LT8350 will latch off until the EN/UVLO is toggled. With a 100kΩ resistor , the LT8350 will keep running regardless of the fault.

![Figure 9. Conducted Average EMI (CISPR25)](lt8350/figures/lt8350-f042.png)

*Figure 9. Conducted Average EMI (CISPR25)*

### APPLICATIONS INFORMATION

The front page shows a typical LT8350 application circuit. This Applications Information section serves as a guideline of selecting external components for typical applications. The examples and equations in this section assume continuous conduction mode unless otherwise specified.

### Switching Frequency Selection

The LT8350 uses a constant frequency control scheme between 200kHz and 2MHz. Selection of the switching frequency is a trade-off between efficiency and component size. Low frequency operation improves efficiency by reducing MOSFET switching losses, but requires larger inductor and capacitor values. For high power applications, consider operating at lower frequencies to minimize MOSFET heating from switching losses. For low power applications, consider operating at higher frequencies to minimize the total solution size. In addition, the specific application also plays an important role in switching frequency selection. In a noise-sensitive system, the switching frequency is usually selected to keep the switching noise out of a sensitive frequency band.

### Switching Frequency Setting

The switching frequency of the LT8350 can be set by the internal oscillator . With the SYNC/MODE pin pulled to ground, the switching frequency is set by a resistor from the RT pin to ground. Table 1 shows R T  resistor values for common switching frequencies.

**Table 1. Switching Frequency vs RT Value (1% Resistor)** ([table-03-p16-data.csv](lt8350/tables/table-03-p16-data.csv), p. 16)

| f_OSC (kHz) | R_T (kΩ) |
|---|---|
| 200 | 249 |
| 400 | 124 |
| 600 | 78.7 |
| 800 | 56.2 |
| 1000 | 43.2 |
| 1200 | 33.2 |
| 1400 | 26.1 |
| 1600 | 21.5 |
| 1800 | 17.4 |
| 2000 | 14.3 |

### Spread Spectrum Frequency Modulation

Switching regulators can be particularly troublesome for applications where electromagnetic interference (EMI) is a concern. To improve the EMI performance, the LT8350 implements a triangle spread spectrum frequency modulation scheme. With the SYNC/MODE pin tied to INTV CC , the  LT8350  starts  to  spread  its  switching  frequency 23% (typical) above the internal oscillator frequency. Figure 9 and Figure 10 show the noise spectrum of the typical application (Figure 14) when the part operates at 12VOUT , 2.5A and 350kHz with ferrite bead EMI filter and spread spectrum enabled.

![Figure 10. Conducted Peak EMI (CISPR25)](lt8350/figures/lt8350-f043.png)

*Figure 10. Conducted Peak EMI (CISPR25)*

![Figure 11. LT8350 Output Currents Resulting 60°C Case Temperature Increase](lt8350/figures/lt8350-f044.png)

*Figure 11. LT8350 Output Currents Resulting 60°C Case Temperature Increase*

### Frequency Synchronization

The LT8350 switching frequency can be synchronized to an external clock using the SYNC/MODE pin. Driving the SYNC/MODE with 10% to 90% duty cycle waveform is recommended. Due to the use of a phase-locked loop (PLL) inside, there is no restriction between the synchronization frequency and the internal oscillator frequency. The rising edge of the synchronization clock represents the beginning of a switching cycle, turning on switches A and C, or switches A and D.

### Maximum Output Current

The LT8350 is a constant-voltage constant-current buckboost converter . The output voltage is regulated up to the current limit threshold, which is set by the CTRL pin voltage and the current sense resistor across the ISP/ ISN pins. If the accurate current limit is not required in the application, connect the CTRL pin to V REF  and short the ISP and ISN pins to disable this accurate current limit function. Refer to the Programming Input or Output Current Limit section for more details.

In practice, the maximum output current can be limited by the thermal constraints of the application. Figure 11 shows the measured output currents over V IN  that increase the case temperature by 60°C. The output is regulated at 12V, and the ambient temperature is 25°C. The measurements were done using the LT8350 demo board. Figure 11 can be a reference to estimate how much output current and power the LT8350 can provide under the temperature constraint for a given application.

![Figure 12. V IN  Undervoltage Lockout (UVLO)](lt8350/figures/lt8350-f045.png)

*Figure 12. V IN  Undervoltage Lockout (UVLO)*

Another factor that can limit the output current and power from the LT8350 is the maximum switch current limit. The typical maximum switch current limit is 6.8A. When the output current and power increase for a given input voltage, the input current will increase until the peak of the inductor current reaches the maximum switch current limit. If the load demands more current, the output voltage may decrease as the converter will regulate the peak of the inductor current to be less than the maximum switch current limit.

### Inductor Selection

The switching frequency and inductor selection are interrelated in that higher switching frequencies allow the use of smaller inductor and capacitor values. The inductor value has a direct effect on ripple current. The highest current ripple ∆I L % happens in the buck region at PV IN(MAX) , and the lowest current ripple ∆I L % happens in the boost region at V IN(MIN) . For any given ripple allowance, the minimum inductance can be calculated as:

![Equation as printed (p. 17)](lt8350/figures/lt8350-eq02.png)

$$L_{BUCK} > \frac{V_{OUT} \bullet (V_{IN(MAX)} - V_{OUT})}{f_{SW} \bullet I_{OUT(MAX)} \bullet \Delta I_L\% \bullet V_{IN(MAX)}} \\
L_{BOOST} > \frac{V_{IN(MIN)}^2 \bullet (V_{OUT} - V_{IN(MIN)})}{f_{SW} \bullet I_{OUT(MAX)} \bullet \Delta I_L\% \bullet V_{OUT}^2}$$

*LaTeX transcription of the equation above, checked against the symbols printed on the page.*

where:

f SW is switching frequency

∆I L % is allowable inductor current ripple

VIN(MIN)  is minimum input voltage

VIN(MAX)  is maximum input voltage

VOUT  is output voltage

I OUT(MAX)  is maximum output current

Slope compensation provides stability in constant frequency current mode control by preventing subharmonic

oscillations at certain duty cycles. The minimum inductance required for stability can be calculated as:

![Equation as printed (p. 18)](lt8350/figures/lt8350-eq03.png)

$$L > \frac{V_{OUT}}{2 \cdot f_{SW} \cdot I_{SW(MAX)}}$$

*LaTeX transcription of the equation above, checked against the symbols printed on the page.*

where:

f SW is switching frequency

I SW(MAX)  is maximum switch current limit = 6.8A (typical)

For high efficiency, choose an inductor with low core loss, such as ferrite. Also, the inductor should have low DC resistance to reduce the I 2 R losses, and must be able to handle the peak inductor current without saturating. To minimize radiated noise, use a shielded inductor .

### CIN  and C OUT  Selection

Input and output capacitance is necessary to suppress voltage ripple caused by discontinuous current moving in and out the regulator . A parallel combination of capacitors is typically used to achieve high capacitance and low equivalent series resistance (ESR). Dry tantalum, special polymer , aluminum electrolytic and ceramic capacitors are all available in surface mount packages. Capacitors with low ESR and high ripple current ratings, such as OS-CON and POSCAP are also available.

Ceramic capacitors should be placed near the regulator input and output to suppress high frequency switching spikes. Ceramic capacitors, of at least 1µF, should also be placed from V IN  to GND and V OUT  to GND as close to the LT8350 pins as possible. Due to their excellent low ESR characteristics, ceramic capacitors can significantly reduce input ripple voltage and help reduce power loss  in  the  higher  ESR  bulk  capacitors.  X5R  or  X7R dielectrics are preferred, as these materials retain their capacitance over wide voltage and temperature ranges. Many ceramic capacitors, particularly 0805 or 0603 case sizes, have greatly reduced capacitance at the desired operating voltage.

### Input Capacitance C IN

Discontinuous input current is highest in the buck region due to the switch A toggling on and off. Make sure that the CIN  capacitor network has low enough ESR and is sized to handle the maximum RMS current. In buck region, the input RMS current is given by:

![Equation as printed (p. 18)](lt8350/figures/lt8350-eq04.png)

$$I_{RMS} \approx I_{OUT(MAX)} \cdot \frac{V_{OUT}}{V_{IN}} \cdot \sqrt{\frac{V_{IN}}{V_{OUT}} - 1}$$

*LaTeX transcription of the equation above, checked against the symbols printed on the page.*

The formula has a maximum at V IN  = 2V OUT , where I RMS = I OUT(MAX) /2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief.

### Output Capacitance C OUT

Discontinuous current shifts from the input to the output in the boost region. Make sure that the C OUT  capacitor network is capable of reducing the output voltage ripple. The effects of ESR and the bulk capacitance must be considered when choosing the right capacitor for a given output ripple voltage. The maximum steady state ripple due to charging and discharging the bulk capacitance is given by:

![Equation as printed (p. 18)](lt8350/figures/lt8350-eq05.png)

$$\ givon \, by . \\ \Delta V_{\text{CAP} ( \text{BOOST} )} = \frac{I_{\text{OUT}} \bullet ( V_{\text{OUT}} - V_{\text{IN} ( \min )} )}{C_{\text{OUT}} \bullet V_{\text{OUT}} \bullet f_{\text{SW}}}$$

*LaTeX transcription of the equation above, checked against the symbols printed on the page.*

![Equation as printed (p. 18)](lt8350/figures/lt8350-eq06.png)

$$\Delta V_{CAP ( BUCK )} = \frac{V_{OUT} \bullet ( 1 - \frac{V_{OUT}}{V_{IN ( \min )}} )}{8 \cdot L \cdot f_{SW}^{2} \cdot C_{OUT}}$$

*LaTeX transcription of the equation above, checked against the symbols printed on the page.*

$$\frac { \cdot 0 0 1 } { C _ { O U T } \cdot V _ { O U T } \cdot f _ { S W } } 
 C _ { O U } \cdot V _ { O U } 
 \frac { V _ { O U } } { V _ { I N ( MΩ N ) } } 
 8 \cdot L \cdot f _ { S W } ^ { 2 } \cdot C _ { O U T }$$

The  maximum  steady  ripple  due  to  the  voltage  drop across the ESR is given by:

![Equation as printed (p. 18)](lt8350/figures/lt8350-eq07.png)

$$\frac{\cdot 001}{C_{OUT} \cdot V_{OUT} \cdot f_{SW}} 
 C_{OU} \cdot V_{OU} 
 \frac{V_{OU}}{V_{IN ( MIN )}} 
 8 \cdot L \cdot f_{SW}^{2} \cdot C_{OUT}$$

*LaTeX transcription of the equation above, checked against the symbols printed on the page.*

![Equation as printed (p. 18)](lt8350/figures/lt8350-eq08.png)

$$\Delta V_{ERS(BOOST)} = \frac{V_{OUT} \cdot I_{OUT(MAX)}}{V_{IN(MIN)}} \cdot ESR$$

*LaTeX transcription of the equation above, checked against the symbols printed on the page.*

### Programming V IN  UVLO

A resistor divider from V IN  to the EN/UVLO pin implements V IN  undervoltage lockout (UVLO). The EN/UVLO enable falling threshold is set at 1.220V with 15mV hysteresis. In addition, the EN/UVLO pin sinks 2.5µA when the voltage on the pin is below 1.220V. This current provides user programmable hysteresis based on the value of R1. The programmable UVLO thresholds are:

![Equation as printed (p. 19)](lt8350/figures/lt8350-eq10.png)

$$V_{\text{IN} ( UVL 0^{+} )} = 1.235 V \bullet \frac{R 1 + R 2}{R 2} + 2.5 \mu A \bullet R 1 \\ V_{\text{IN} ( UVL 0^{-} )} = 1.220 V \bullet \frac{R 1 + R 2}{R 2}$$

*LaTeX transcription of the equation above, checked against the symbols printed on the page.*

![Equation as printed (p. 19)](lt8350/figures/lt8350-eq11.png)

Figure 12 shows the implementation of external shutdown control while still using the UVLO function. The NMOS grounds the EN/UVLO pin when turned on, and puts the LT8350 in shutdown with quiescent current less than 2µA (typical).

![Figure 13. Feedback Resistor Connection](lt8350/figures/lt8350-f046.png)

*Figure 13. Feedback Resistor Connection*

### Programming Input or Output Current Limit

The input or output current limit is programmed by placing an appropriate value current sense resistor , R IS , in the input or output power path. The voltage drop across RIS  is (Kelvin) sensed by the ISP and ISN pins. The CTRL pin should be tied to a voltage higher than 1.35V to get the full-scale 100mV (typical) threshold across the sense resistor . The CTRL pin can be used to reduce the input or  output  current  to  zero,  although  relative  accuracy decreases with the decreasing sense threshold. When the CTRL pin voltage, V CTRL , is less than 1.15V, the current limit is:

![Equation as printed (p. 18)](lt8350/figures/lt8350-eq09.png)

$$\Delta V_{ERS(BUCK)} = \frac{V_{OUT} \cdot (1 - \frac{V_{OUT}}{V_{IN(MIN)}})}{L \cdot f_{SW}} \cdot ESR$$

*LaTeX transcription of the equation above, checked against the symbols printed on the page.*

When VCTRL  is higher than 1.35V, the current threshold is regulated to:

![Equation as printed (p. 19)](lt8350/figures/lt8350-eq13.png)

$$I_{IS ( MAX )} = \frac{100 mV}{R_{IS}}$$

*LaTeX transcription of the equation above, checked against the symbols printed on the page.*

The CTRL pin should not be left open (tie to V REF  if not used). The CTRL pin can also be used in conjunction with a thermistor to provide overtemperature protection for the output load, or with a resistor divider to V IN  to reduce output power and switching current when V IN  is low.

The presence of a time varying differential voltage ripple signal across ISP and ISN at the switching frequency is expected. The amplitude of this signal is increased by higher load current, lower switching frequency, or smaller value output filter capacitor . Some level of ripple signal is acceptable, and the compensation capacitor on the V C pin filters the signal so the average difference between ISP and ISN is regulated to the user-programmed value. The ripple voltage amplitude (peak-to-peak) in excess of 20mV should not cause mis-operation, but may lead to noticeable offset between the average value and the userprogrammed value.

### ISMON Current Monitor

The ISMON pin provides a buffered monitor output of the current flowing through the ISP/ISN current sense resistor , R IS . The ISMON voltage is calculated as:

![Equation as printed (p. 19)](lt8350/figures/lt8350-eq14.png)

$$V_{ISMON} = 10 \bullet V_{( ISP - ISN )} + 250 mV$$

*LaTeX transcription of the equation above, checked against the symbols printed on the page.*

Since the ISMON pin has the same 0.25V offset as the CTRL pin, the primary LT8350 ISMON pin can be directly tied to the secondary LT8350 pin for equal current sharing in parallel applications.

### LOAD Switch Control

The LOADEN and LOADTG pins provide high side PMOS load switch control. The LOADEN pin accepts a logic level ON/OFF signal and then drives the LOADTG pin to turn on or off the high side PMOS load switch, thereby connecting or disconnecting the LT8350 power output from the system output. When the LOADEN pin is force low, the LT8350 turns off power switches, disconnects the V C  pin

from all internal loads, and turn off LOADTG. The LOADEN pin should not be open (tie to INTV CC  or V REF  if not used).

### High Side PMOS Load Switch Selection

A high side PMOS load switch is recommended in some LT8350 applications requiring load switch control. The high side PMOS load switch is typically selected for drainsource voltage V DS , gate-source threshold voltage V GS(TH) , and continuous drain current ID. For proper operations, VDS  rating should exceed the maximum output voltage set by the FB pin, the absolute value of V GS(TH)  should be less than 3V, and I D rating should be above I OUT(MAX) .

### Programming Output Voltage and Thresholds

The LT8350 has a voltage feedback pin FB that can be used to program a constant-voltage output. The output voltage can be set by selecting the values of R3 and R4 (Figure 13) according to the following equation:

![Equation as printed (p. 20)](lt8350/figures/lt8350-eqx03.png)

$$V_{OUT} = 1V \cdot \frac{R3 + R4}{R4}$$

*LaTeX transcription of the equation above, checked against the symbols printed on the page.*

![application circuit (p. 22)](lt8350/figures/lt8350-f047.png)

In addition, the FB pin also sets output overvoltage threshold,  output  power  good thresholds, and output short threshold. For an application with small output capacitors, the output voltage may exhibit considerable overshoots during load transient event. Once the FB pin hits its overvoltage threshold 1.1V, the LT8350 stops switching by turning off all four power switches, and also turns off LOADTG to disconnect the output load for protection. The output overvoltage threshold can be set as:

![Equation as printed (p. 20)](lt8350/figures/lt8350-eq15.png)

$$V_{OUT ( OVP )} = 1.1 V \bullet \frac{R 3 + R 4}{R 4}$$

*LaTeX transcription of the equation above, checked against the symbols printed on the page.*

To provide the output short-circuit detection and protection, the output short threshold can be set as:

![Equation as printed (p. 20)](lt8350/figures/lt8350-eq16.png)

$$V_{OUT ( SHORT )} = 0.25 V \bullet \frac{R 3 + R 4}{R 4}$$

*LaTeX transcription of the equation above, checked against the symbols printed on the page.*

### Power Good ( PGOOD ) Pin

The LT8350 provides an open-drain status pin, PGOOD , which is pulled low when V FB  is within ±10% of the 1V regulation voltage. The PGOOD pin is allowed to be pulled up by an external resistor to INTV CC  or an external voltage source of up to 5V.

### Soft-Start and Fault Protection

As shown in Figure 8 and explained in the Operation section, the SS pin can be used to program soft-start by connecting an external capacitor from the SS pin to ground. The internal 12.5µA pull-up current charges up the capacitor , creating a voltage ramp on the SS pin. As the SS pin voltage rises linearly from 0.25V to 1V (and beyond), the output voltage rises smoothly and transitions into its final voltage regulation. The soft-start time can be calculated as:

![Equation as printed (p. 20)](lt8350/figures/lt8350-eq17.png)

$$t_{ss} = 1 V \bullet \frac{C_{ss}}{12.5 \mu A}$$

*LaTeX transcription of the equation above, checked against the symbols printed on the page.*

Make sure the C SS  is at least five to ten times larger than the compensation capacitor on the V C  pin for a well-controlled output voltage soft-start. A 22nF ceramic capacitor is a good starting point.

The SS pin is also used as a fault timer . Once a short-circuit fault is detected, a 1.25µA pull-down current source is activated. Using a single resistor from the SS pin to the VREF  pin, the LT8350 can be set to three different fault protection modes: hiccup (no resistor), latch-off (499kΩ), and keep-running (100kΩ).

With a 100kΩ resistor in keep-running mode, the LT8350 continues switching normally and regulates the current into ground. With a 499kΩ resistor in latch-off mode, the LT8350 stops switching until the EN/UVLO pin is pulled low and high to restart. With no resistor in hiccup mode,

the LT8350 enters low duty cycle auto-retry operation. The 1.25µA pull-down current discharges the SS pin to 0.2V and then 12.5µA pull-up current charges the SS pin up. If the short-circuit condition has not been removed when the SS pin reaches 1.75V, the 1.25µA pull-down current turns on again, initiating a new hiccup cycle. This will continue until the fault is removed. Once the output short-circuit condition is removed, the output will have a smooth short-circuit recovery due to soft-start.

### Loop Compensation

The  LT8350  uses  an  internal  transconductance  error amplifier , the output of which, V C , compensates the control loop. The external inductor , output capacitor , and the compensation resistor and capacitor determine the loop stability.

The inductor and output capacitor are chosen based on performance, size and cost. The compensation resistor and capacitor on the V C  pin are set to optimize control loop response and stability. For a typical application, a 2.2nF compensation capacitor on the V C  pin is adequate, and a series resistor should always be used to increase the slew rate on the V C pin to maintain tighter output voltage regulation during fast transients on the input supply of the converter .

### Efficiency Considerations

The power efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Although all dissipative elements in circuits produce losses, four main sources account for most of the losses in LT8350 circuit:

1. DC I 2 R losses. These arise from the resistances of the MOSFETs, sensing resistor , inductor and PC board traces and cause the efficiency to drop at high output currents.
2. T ransition loss. This loss arises from the brief amount of time switch A or switch C spends in the saturated region during switch node transitions. It depends upon the input voltage, load current, driver strength and MOSFET capacitance, among other factors.
3. INTV CC  current. This is the sum of the MOSFET driver and control currents.
4. C IN   and C OUT  loss. The input capacitor has the difficult job of filtering the large RMS input current to the regulator in buck region. The output capacitor has the difficult job of filtering the large RMS output current in boost region. Both C IN  and C OUT  are required to have low ESR to minimize the AC I 2 R loss and sufficient capacitance to prevent the RMS current from causing additional upstream losses in fuses or batteries.

### TYPICAL APPLICATIONS

![Figure 14. 96% Efficient 30W (12V 2.5A), 350kHz Buck-Boost Voltage Regulator](lt8350/figures/lt8350-f048.png)

*Figure 14. 96% Efficient 30W (12V 2.5A), 350kHz Buck-Boost Voltage Regulator*

![other (p. 23)](lt8350/figures/lt8350-f049.png)

### PACKAGE DESCRIPTION

### REVISION HISTORY

**Revision History** ([table-04-p24-data.csv](lt8350/tables/table-04-p24-data.csv), p. 24)

| REV | DATE | DESCRIPTION | PAGE NUMBER |
|---|---|---|---|
| A | 09/24 | Updated Waveform Label for the Buck-Boost Region | 5 |
|  |  | Updated Package Description Diagram | 23 |
| B | 10/24 | Updated Features | 1 |
|  |  | Updated Order Information | 2 |

![Figure 15. USB-PD Source - 27W 5V, 9V/3A Fixed PDO Mode](lt8350/figures/lt8350-f052.png)

*Figure 15. USB-PD Source - 27W 5V, 9V/3A Fixed PDO Mode*

### RELATED PARTS

**Related Parts** ([table-05-p25-data.csv](lt8350/tables/table-05-p25-data.csv), p. 25)

| PART NUMBER | DESCRIPTION | COMMENTS |
|---|---|---|
| LT8390/LT8390A | 60V 4-Switch Synchronous Buck-Boost Controller with Spread Spectrum | V_IN: 4V to 60V, V_OUT(MAX): 60V, ±1.5% Voltage Accuracy, ±3% Current Accuracy, 4mm × 5mm QFN and TSSOP-28 Packages. |
| LT3942 | 36V, 2A Synchronous Buck-Boost Converter | V_IN: 3V to 36V, V_OUT(MAX): 36V, ±3% Current Accuracy, 4mm × 5mm QFN Package. |
| LTC3115-1/ LTC3115-2 | 40V, 2A Synchronous Buck-Boost DC/DC Converter | V_IN: 2.7V to 40V, V_OUT: 2.7V to 40V, DFN and TSSOP-20 Packages. |
| LTC3114-1 | 40V, 1A(I_OUT) Synchronous Buck-Boost DC/DC Converter | V_IN: 2.2V to 40V, V_OUT: 2.7V to 40V, I_Q = 30µA, I_SD < 3µA, DFN and TSSOP Packages. |
| LT3120 | 26V, 9A Low-I_Q CC/CV Synchronous Buck-Boost Converter | V_IN: 2.5V to 26V, V_OUT: 0.8V to 24V, I_Q = 35µA, 4mm × 5mm LQFN Package. |

![for common switching frequencies. Table 1. Switching Frequency vs RT Value (1% Resistor)](lt8350/figures/lt8350-f054.png)

*for common switching frequencies. Table 1. Switching Frequency vs RT Value (1% Resistor)*