

    Cadence Design Systems, Inc.
    Bomhdl 17.4-2019 S039 (4154356) 11/15/2023
    Copyright 2021 Cadence Design Systems, Inc, Cadence Design Systems, Inc.

    Run on Tue Aug  6 11:38:24 2024


*****************************
*  Processing project file  *
*****************************

    DESIGN_LIBRARY '02_070959b_lib'
    DESIGN_NAME '02_070959b_top'
    VIEW_SCHEMATIC 'sch_1'
    VIEW_PACKAGER 'packaged'
    VIEW_VARIANT 'variant'
    VIEW_BOM ''
    VIEW_CONFIG_PHYSICAL 'cfg_package'
    PPT 'Z:\allegro\v174_site\logical\share\library\mechanical\mech\part_table\part.ptf'
    USE_LIBRARY_PPT 'on'
    MERGE_PPT 'on'
    INCLUDE_PPT ''
    EXCLUDE_PPT ''
    SPREADSHEET 'ON'
    LAST_OUTPUT_FILE './worklib/02_070959b_top/bom/070959-02.csv'
    TEMPLATE_FILE 'template.bom'
    PACKAGED_VARIANT_SYNC_CHECK '1'
    LAST_TEMPLATE_FILE './worklib/02_070959b_top/bom/bom.bom'
    SS_DELIMITER 'Comma ,'
    USE_FILTERS '1'
    LAST_STANDARD_OPTION '1'
    LAST_WHAT_TO_OUTPUT '1'
    LAST_VARIANT_FILE 'variant.dat'
    LAST_SS_DELIMITER 'Comma ,'
    LAST_CALLOUT_FILE './worklib/02_070959b_top/bom/mechanical.callouts'
    LAST_VARIANT '070959-02'
    GEN_HIER_BOM '0'

*********************************
*  End processing project file  *
*********************************

 
Initializing tool communication modules... 

*********************************
*  Loading the design database  *
*********************************

Start loading the design. 
Loading logical design view of 02_070959b_top 
Setting design view directives...
 
Loading pstX files...
 

Loading... C:\tmp\20_070959b\worklib\02_070959b_top\packaged\pstchip.dat
 

Loading... C:\tmp\20_070959b\worklib\02_070959b_top\packaged\pstxprt.dat
 

Loading... C:\tmp\20_070959b\worklib\02_070959b_top\packaged\pstxnet.dat
 
packaging the design view... 
End loading logical design view of 02_070959b_top 
Reading cell level PPTs... 
INFO(SPCODD-181): Loading Z:/allegro/v174_site/logical/share/library/mechanical/mech/part_table/part.ptf.
       
INFO(SPCODD-181): Loading Z:/allegro/v174_site/logical/share/library/conn_pcb/cntp1p/part_table/part.ptf.
       
INFO(SPCODD-181): Loading Z:/allegro/v174_site/logical/share/library/capacitors/cap/part_table/part.ptf.
       
INFO(SPCODD-181): Loading Z:/allegro/v174_site/logical/share/library/conn_pcb/cn6p/part_table/part.ptf.
       
INFO(SPCODD-181): Loading Z:/allegro/v174_site/logical/share/library/conn_pcb/cn8p_a/part_table/part.ptf.
       
INFO(SPCODD-181): Loading Z:/allegro/v174_site/logical/share/library/conn_pcb/cn6p_odd_even/part_table/part.ptf.
       
INFO(SPCODD-181): Loading Z:/allegro/v174_site/logical/share/library/conn_pcb/cn10p/part_table/part.ptf.
       
INFO(SPCODD-181): Loading Z:/allegro/v174_site/logical/share/library/conn_pcb/cn12p/part_table/part.ptf.
       
INFO(SPCODD-181): Loading Z:/allegro/v174_site/logical/share/library/resistors/res/part_table/part.ptf.
       
INFO(SPCODD-181): Loading Z:/allegro/v174_site/logical/share/library/ic_other/ic24xx32a_v2/part_table/part.ptf.
       
INFO(SPCODD-181): Loading Z:/allegro/v174_site/logical/share/library/conn_pcb/cn3p/part_table/part.ptf.
       
INFO(SPCODD-181): Loading Z:/allegro/v174_site/logical/share/library/diodes/dioschottky/part_table/part.ptf.
       
INFO(SPCODD-181): Loading Z:/allegro/v174_site/logical/share/library/conn_pcb/cn2p/part_table/part.ptf.
       
INFO(SPCODD-181): Loading Z:/allegro/v174_site/logical/share/library/conn_pcb/cnbnc5p/part_table/part.ptf.
       
INFO(SPCODD-181): Loading Z:/allegro/v174_site/logical/share/library/resistors/resjmpr_3p/part_table/part.ptf.
       
INFO(SPCODD-181): Loading Z:/allegro/v174_site/logical/share/library/resistors/resjmprshrt/part_table/part.ptf.
       
INFO(SPCODD-181): Loading Z:/allegro/v174_site/logical/share/library/inductors/ind/part_table/part.ptf.
       
INFO(SPCODD-181): Loading Z:/allegro/v174_site/logical/share/library/ic_adi/adp5071/part_table/part.ptf.
       
INFO(SPCODD-181): Loading Z:/allegro/v174_site/logical/share/library/ic_adi/adr45xx_v2/part_table/part.ptf.
       
INFO(SPCODD-181): Loading Z:/allegro/v174_site/logical/share/library/conn_pcb/cn16p_odd_even/part_table/part.ptf.
       
INFO(SPCODD-181): Loading Z:/allegro/v174_site/logical/share/library/ic_adi/ad5766/part_table/part.ptf.
       
Start loading variant databse... 
Setting design view directives...
 
Loading variant data base C:\tmp\20_070959b\worklib\02_070959b_top\variant\variant.dat 

Loading... C:\tmp\20_070959b\worklib\02_070959b_top\packaged\pstchip.dat
 

Loading... C:\tmp\20_070959b\worklib\02_070959b_top\variant\variant.dat
 
End loading variant database of C:\tmp\20_070959b\worklib\02_070959b_top\variant\variant.dat 
Start Merging the variant database in main design view.
 
Variant Database merged successfully.
 
Design loaded successfully. 


******************************************
*  Finished loading the design database  *
******************************************


**********************************
*  Start generating bom reports. *
**********************************

Report generated successfully.

Output file list :
C:\tmp\20_070959b\worklib\02_070959b_top\bom\070959-01.csv

*********************************
*  End generating bom reports   *
*********************************


*********************************
*  Loading the design database  *
*********************************

Start loading the design. 
Loading logical design view of 02_070959b_top 
Setting design view directives...
 
Loading pstX files...
 

Loading... C:\tmp\20_070959b\worklib\02_070959b_top\packaged\pstchip.dat
 

Loading... C:\tmp\20_070959b\worklib\02_070959b_top\packaged\pstxprt.dat
 

Loading... C:\tmp\20_070959b\worklib\02_070959b_top\packaged\pstxnet.dat
 
packaging the design view... 
End loading logical design view of 02_070959b_top 
Start loading variant databse... 
Setting design view directives...
 
Loading variant data base variant.dat 

Loading... C:\tmp\20_070959b\worklib\02_070959b_top\packaged\pstchip.dat
 

Loading... variant.dat
 
End loading variant database of variant.dat 
Start Merging the variant database in main design view.
 
Variant Database merged successfully.
 
Design loaded successfully. 


******************************************
*  Finished loading the design database  *
******************************************


**********************************
*  Start generating bom reports. *
**********************************

Report generated successfully.

Output file list :
C:\tmp\20_070959b\worklib\02_070959b_top\bom\070959-02.csv

*********************************
*  End generating bom reports   *
*********************************

    Start time   11:38:24
    End time     11:41:01
    Elapsed time  0:02:37

*********************************
*  BOM-HDL execution done.      *
*********************************

