



    Cadence Design Systems, Inc.
    Packager-XL 17.4-2019 S039 (4153571) WIN32 11/4/2023 12:00:00 IST
    (C) Copyright 1994, Cadence Design Systems, Inc.

    Run on Tue Aug  6 10:20:37 2024


 **********************************************
 *  Processing project file and command line  *
 **********************************************



    ANNOTATE  'BODY' 'PIN' 'NET'
    COMP_DEF_PROP  'ALT_SYMBOLS' 'JEDEC_TYPE' 'NC_PINS' 'MERGE_NC_PINS'
                   'POWER_GROUP' 'POWER_PINS' 'MERGE_POWER_PINS' 'PINCOUNT'
    COMP_INST_PROP  'GROUP' 'ROOM' 'REUSE_INSTANCE' 'REUSE_ID' 'REUSE_NAME'
                    'SIGNAL_MODEL' 'DEFAULT_SIGNAL_MODEL'
                    'VOLT_TEMP_SIGNAL_MODEL' 'SYMBOL_EDITED'
                    'INCLUDE_IN_RF_TOPOLOGY' 'CDS_FSP_LIB_PART_MODEL'
                    'CDS_FSP_IS_FPGA' 'CDS_FSP_INSTANCE_NAME'
                    'CDS_FSP_INSTANCE_ID' 'NO_XNET_CONNECTION'
                    'EMBEDDED_PLACEMENT' 'DIE_ATTACH_ORIENTATION'
                    'DIE_ATTACH_TYPE' 'DIE_COMPONENT' 'ISRFELEMENT'
                    'RFELEMENTTYPE' 'RFLAYER' 'RFLAYER1' 'RFLAYER2' 'RFLAYER3'
                    'RFLAYER4' 'RFLAYER5' 'RFLAYER6' 'RFLAYER7' 'RFLAYER8'
                    'RFLAYER9' 'RFLAYER10' 'RFLAYER11' 'RFLAYER12' 'RFLAYER13'
                    'RFLAYER14' 'RFLAYER15' 'RFLAYER16' 'RFCOUPLINGMODE'
                    'RFFLIPMODE' 'RFANGLE' 'RFANGLE1' 'RFWIDTH' 'RFWIDTH1'
                    'RFWIDTH2' 'RFWIDTH3' 'RFWIDTH4' 'RFWIDTH5' 'RFWIDTH6'
                    'RFWIDTH7' 'RFWIDTH8' 'RFWIDTH9' 'RFWIDTH10' 'RFWIDTH11'
                    'RFWIDTH12' 'RFWIDTH13' 'RFWIDTH14' 'RFWIDTH15' 'RFWIDTH16'
                    'RFLENGTH' 'RFLENGTH1' 'RFLENGTH2' 'RFLENGTH3' 'RFLENGTH4'
                    'RFLENGTH5' 'RFLENGTH6' 'RFLENGTH7' 'RFLENGTH8' 'RFSPACING'
                    'RFSPACING1' 'RFSPACING2' 'RFSPACING3' 'RFSPACING4'
                    'RFSPACING5' 'RFSPACING6' 'RFSPACING7' 'RFSPACING8'
                    'RFSPACING9' 'RFSPACING10' 'RFSPACING11' 'RFSPACING12'
                    'RFSPACING13' 'RFSPACING14' 'RFSPACING15' 'RFOFFSETX'
                    'RFOFFSETY' 'RFRADIUS' 'RFDEPTH' 'RFFREQUENCY'
                    'RFMITERFRACTION' 'RFBENDMODE' 'RFNUMBERLEGS'
                    'RFNUMBERPAIRS' 'RFNUMBERTURNS' 'RFCAPACITANCE'
                    'RFRESISTANCE' 'RFINDUCTANCE' 'RFPADSTACKNAME'
                    'RFPADSSMNAME1' 'RFPADSSMNAME2' 'RFPADBEGINLAYER'
                    'RFPADENDLAYER' 'RFPADLINEWIDTH1' 'RFPADLINEWIDTH2'
                    'RFPADDIAMETER' 'RFPADDIAMETER1' 'RFPADDIAMETER2'
                    'RFPADLENGTH1' 'RFPADLENGTH2' 'RFHOLEDIAMETER' 'RFPADANGLE'
                    'RFDRANAME' 'RFPADTYPE' 'RFUID' 'RFBLOCK' 'RFDCNET'
                    'RFGROUP' 'MWO_NAME'
    SUPPRESS_GLOBAL_SHORT_CHECK OFF
    DEBUG    0
    DEFAULT_PHYS_DES_PREFIX U
    FEEDBACK  'OFF'
    MAX_ERRORS 999
    NET_NAME_CHARS   @  -  !  #  %  &  (  )  *  .  /  :  ?  [  ]  ^  _  `  +
                     =  >  0  1  2  3  4  5  6  7  8  9
    NET_NAME_LENGTH 255
    NUM_OLD_VERSIONS 3
    OPTIMIZE OFF
    REUSE_REFDES ON
    OPF_OPTIMIZATION OFF
    HARD_LOC_SEC OFF
    FORCE_PTF_ENTRY OFF
    REGENERATE_PHYSICAL_NET_NAME OFF
    SCH_POWER_GROUP_WINS_OVER_PPT OFF
    NULL_OPT_VALID OFF
    USE_VECTOR_NOTATION ON
    FILTER_ECS_FROM_XNET ON
    OUTPUT  'ON'
    PACKAGE_PROP  'GROUP' 'ROOM'
    PART_TYPE_LENGTH 255
    PPT 
         Z:\allegro\v174_site\logical\share\library\mechanical\mech\part_table\part.ptf 
    REF_DES_LENGTH 10
    REPACKAGE OFF
    ELECTRICAL_CONSTRAINTS ON
    OVERWRITE_CONSTRAINTS OFF
    RUN_DIR ./worklib/02_070959b_top/packaged/
    STRICT_PACKAGE_PROP  'REUSE_INSTANCE'
    USE_LIBRARY_PPT ON
    USE_STATE ON
    WARNINGS ON
    LIBRARY  '02_070959b_lib' 'adi_standard' 'capacitors' 'conn_pcb'
             'contactors' 'crystals' 'diodes' 'filters' 'fuses' 'graphics'
             'ic_adi' 'ic_cmos' 'ic_ecl' 'ic_lin' 'ic_other' 'ic_ttl'
             'inductors' 'modules' 'nocomponent' 'nqa' 'power_ground' 'relays'
             'resistors' 'sockets' 'standard' 'switches' 'transformers'
             'transistors'
    VIEW_PTF part_table
    VIEW_PACKAGER packaged
    VIEW_CONSTRAINTS constraints
    DESIGN_LIBRARY 02_070959b_lib
    DESIGN_NAME 02_070959b_top
    VIEW_CONFIG_PHYSICAL cfg_package
    SD_SUFFIX_SEPARATOR _
    STOP_PST_GEN_ON_PTF_MISMATCH ON
    IGNORE_PRIM_BINDING OFF
    LOG_INST_PHYS_PATH ON
    ANNOTATE_VISIBLE_SEC OFF
    PTF_MISMATCH_EXCLUDE_INJ_PROP  'ALL'
    IMPORT_HFS_HARDSEC_ON_SWAP_PINS OFF
    ALLOW_PTFVALUE_INITIAL_BLANKS ON
    PRESERVE_UNSUBSTITUTED_MACROS OFF
    DETECT_SYS_NETSHORTS_PKG ON
    PROCESS_PIN_SHORT_PROP ON
    STOP_PACKAGE_ON_SCHEMATIC_ERROR OFF
    LOCK_FILE_PERM 444
    LOCK_FOR_SAME_USER OFF
    ERROR_ON_MISMATCHED_INTERFACE ON
    RETAIN_ZERO_NODE_NETS OFF
    IGNORE_ERR_EMPTY_LONGPARTNAME OFF
    ERROR_ILLEGAL_QUOTE_PPT OFF
    B2F_OVERWRITE_CONSTRAINTS OFF
    ERROR_ON_PARTIAL_INSTANTIATION_OF_HSS OFF
    RUN_HIERWR_BEFORE_PXL OFF
    IMPORT_CONSTRAINTS_ONLY_FEEDBACK OFF
    REPORT_NET_PROP_CONFLICT_AS_ERROR OFF
    CHECK_PACK_SYNC_ON_PKG OFF
    ERR_OK_NET_ONE_PIN_MULTI_NODES OFF
    ALLOW_PINTEXT_SWAP ON
    SHOW_EXTENDED_HELP ON
    HONOR_SOFT_PROPS_PACKAGE  'NONE'
    ALLOW_SAME_PACKAGE OFF
    INCLUDE_KEY_PROP_COMP_DEF OFF

 **************************************************************
 *  End processing project file and command line  (00:00:01)  *
 **************************************************************


Creating Configuration "cfg_package" for Design "02_070959b_top"

INFO(SPCODD-181): Loading C:\pcblib\apps\allegro\SPB_17.4\share\cdssetup\cdspr~
	op.tmf.
      INFO(SPCODD-181): Loading C:\pcblib\apps\allegro\SPB_17.4\share\cdssetup\cdspr~
	op.paf.
      INFO(SPCODD-181): Loading Z:/allegro/v174_site/logical/share/library/mechanica~
	l/mech/part_table/part.ptf.
      
 *********************************
 *  Loading the design database  *
 *********************************

INFO(SPCODD-181): Loading Z:/allegro/v174_site/logical/share/library/conn_pcb/~
	cn10p/part_table/part.ptf.
      INFO(SPCODD-181): Loading Z:/allegro/v174_site/logical/share/library/conn_pcb/~
	cn8p_a/part_table/part.ptf.
      INFO(SPCODD-181): Loading Z:/allegro/v174_site/logical/share/library/conn_pcb/~
	cn6p/part_table/part.ptf.
      INFO(SPCODD-181): Loading Z:/allegro/v174_site/logical/share/library/resistors~
	/res/part_table/part.ptf.
      INFO(SPCODD-181): Loading Z:/allegro/v174_site/logical/share/library/ic_other/~
	ic24xx32a_v2/part_table/part.ptf.
      INFO(SPCODD-181): Loading Z:/allegro/v174_site/logical/share/library/conn_pcb/~
	cn6p_odd_even/part_table/part.ptf.
      INFO(SPCODD-181): Loading Z:/allegro/v174_site/logical/share/library/capacitor~
	s/cap/part_table/part.ptf.
      INFO(SPCODD-181): Loading Z:/allegro/v174_site/logical/share/library/ic_adi/ad~
	p5071/part_table/part.ptf.
      INFO(SPCODD-181): Loading Z:/allegro/v174_site/logical/share/library/resistors~
	/resjmpr_3p/part_table/part.ptf.
      INFO(SPCODD-181): Loading Z:/allegro/v174_site/logical/share/library/inductors~
	/ind/part_table/part.ptf.
      INFO(SPCODD-181): Loading Z:/allegro/v174_site/logical/share/library/diodes/di~
	oschottky/part_table/part.ptf.
      INFO(SPCODD-181): Loading Z:/allegro/v174_site/logical/share/library/conn_pcb/~
	cn12p/part_table/part.ptf.
      INFO(SPCODD-181): Loading Z:/allegro/v174_site/logical/share/library/conn_pcb/~
	cnbnc5p/part_table/part.ptf.
      INFO(SPCODD-181): Loading Z:/allegro/v174_site/logical/share/library/conn_pcb/~
	cntp1p/part_table/part.ptf.
      INFO(SPCODD-181): Loading Z:/allegro/v174_site/logical/share/library/conn_pcb/~
	cn2p/part_table/part.ptf.
      INFO(SPCODD-181): Loading Z:/allegro/v174_site/logical/share/library/ic_adi/ad~
	r45xx_v2/part_table/part.ptf.
      INFO(SPCODD-181): Loading Z:/allegro/v174_site/logical/share/library/resistors~
	/resjmprshrt/part_table/part.ptf.
      INFO(SPCODD-181): Loading Z:/allegro/v174_site/logical/share/library/conn_pcb/~
	cn3p/part_table/part.ptf.
      INFO(SPCODD-181): Loading Z:/allegro/v174_site/logical/share/library/ic_adi/ad~
	5766/part_table/part.ptf.
      INFO(SPCODD-181): Loading Z:/allegro/v174_site/logical/share/library/conn_pcb/~
	cn16p_odd_even/part_table/part.ptf.
      
 *************************
 *  Loading State Files  *
 *************************

Loading ./worklib/02_070959b_top/packaged/pxl.state. 
 
#1   WARNING(SPCODD-276): The state file generated for the root drawing differ~
	s from the current root name of '02_070959B_TOP'. The names found in the state~
	 file will be modified accordingly.
       
#2   WARNING(SPCODD-276): The state file generated for the root drawing differ~
	s from the current root name of '02_070959B_TOP'. The names found in the state~
	 file will be modified accordingly.
       
#3   WARNING(SPCODD-276): The state file generated for the root drawing differ~
	s from the current root name of '02_070959B_TOP'. The names found in the state~
	 file will be modified accordingly.
       
#4   WARNING(SPCODD-276): The state file generated for the root drawing differ~
	s from the current root name of '02_070959B_TOP'. The names found in the state~
	 file will be modified accordingly.
      
 *****************************************
 *  End loading State Files  (00:00:00)  *
 *****************************************


 ****************************************
 *  Starting to assign physical parts.  *
 ****************************************


 ***********************************************
 *  End assigning physical parts.  (00:00:00)  *
 ***********************************************


 ***************
 *  Packaging  *
 ***************


 *******************************
 *  End packaging  (00:00:00)  *
 *******************************

INFO(SPCOPK-1442): No errors detected
INFO(SPCOPK-1443): 4 warnings detected
INFO(SPCOPK-1448): Use Tools - Markers - Packager in Design Entry HDL to highl~
	ight the instances for which errors or warnings are reported
    Start time   10:20:36
    End time     10:21:48
    Elapsed time  0:01:12

 ***************************************************************************
 *  Packager-XL execution done.
 ***************************************************************************
Starting to audit ECsets in the design...
Audit completed successfully.