    IF :LNOT::DEF:INCLUDED_CYFITTERRV_INC
INCLUDED_CYFITTERRV_INC EQU 1
    GET cydevicerv_trm.inc

; HPD
HPD__0__DR EQU CYREG_GPIO_PRT3_DR
HPD__0__DR_CLR EQU CYREG_GPIO_PRT3_DR_CLR
HPD__0__DR_INV EQU CYREG_GPIO_PRT3_DR_INV
HPD__0__DR_SET EQU CYREG_GPIO_PRT3_DR_SET
HPD__0__HSIOM EQU CYREG_HSIOM_PORT_SEL3
HPD__0__HSIOM_MASK EQU 0x0000F000
HPD__0__HSIOM_SHIFT EQU 12
HPD__0__INTCFG EQU CYREG_GPIO_PRT3_INTR_CFG
HPD__0__INTR EQU CYREG_GPIO_PRT3_INTR
HPD__0__INTR_CFG EQU CYREG_GPIO_PRT3_INTR_CFG
HPD__0__INTSTAT EQU CYREG_GPIO_PRT3_INTR
HPD__0__MASK EQU 0x08
HPD__0__PC EQU CYREG_GPIO_PRT3_PC
HPD__0__PC2 EQU CYREG_GPIO_PRT3_PC2
HPD__0__PORT EQU 3
HPD__0__PS EQU CYREG_GPIO_PRT3_PS
HPD__0__SHIFT EQU 3
HPD__DR EQU CYREG_GPIO_PRT3_DR
HPD__DR_CLR EQU CYREG_GPIO_PRT3_DR_CLR
HPD__DR_INV EQU CYREG_GPIO_PRT3_DR_INV
HPD__DR_SET EQU CYREG_GPIO_PRT3_DR_SET
HPD__INTCFG EQU CYREG_GPIO_PRT3_INTR_CFG
HPD__INTR EQU CYREG_GPIO_PRT3_INTR
HPD__INTR_CFG EQU CYREG_GPIO_PRT3_INTR_CFG
HPD__INTSTAT EQU CYREG_GPIO_PRT3_INTR
HPD__MASK EQU 0x08
HPD__PC EQU CYREG_GPIO_PRT3_PC
HPD__PC2 EQU CYREG_GPIO_PRT3_PC2
HPD__PORT EQU 3
HPD__PS EQU CYREG_GPIO_PRT3_PS
HPD__SHIFT EQU 3

; EC_INT
EC_INT__0__DR EQU CYREG_GPIO_PRT3_DR
EC_INT__0__DR_CLR EQU CYREG_GPIO_PRT3_DR_CLR
EC_INT__0__DR_INV EQU CYREG_GPIO_PRT3_DR_INV
EC_INT__0__DR_SET EQU CYREG_GPIO_PRT3_DR_SET
EC_INT__0__HSIOM EQU CYREG_HSIOM_PORT_SEL3
EC_INT__0__HSIOM_MASK EQU 0x00000F00
EC_INT__0__HSIOM_SHIFT EQU 8
EC_INT__0__INTCFG EQU CYREG_GPIO_PRT3_INTR_CFG
EC_INT__0__INTR EQU CYREG_GPIO_PRT3_INTR
EC_INT__0__INTR_CFG EQU CYREG_GPIO_PRT3_INTR_CFG
EC_INT__0__INTSTAT EQU CYREG_GPIO_PRT3_INTR
EC_INT__0__MASK EQU 0x04
EC_INT__0__PC EQU CYREG_GPIO_PRT3_PC
EC_INT__0__PC2 EQU CYREG_GPIO_PRT3_PC2
EC_INT__0__PORT EQU 3
EC_INT__0__PS EQU CYREG_GPIO_PRT3_PS
EC_INT__0__SHIFT EQU 2
EC_INT__DR EQU CYREG_GPIO_PRT3_DR
EC_INT__DR_CLR EQU CYREG_GPIO_PRT3_DR_CLR
EC_INT__DR_INV EQU CYREG_GPIO_PRT3_DR_INV
EC_INT__DR_SET EQU CYREG_GPIO_PRT3_DR_SET
EC_INT__INTCFG EQU CYREG_GPIO_PRT3_INTR_CFG
EC_INT__INTR EQU CYREG_GPIO_PRT3_INTR
EC_INT__INTR_CFG EQU CYREG_GPIO_PRT3_INTR_CFG
EC_INT__INTSTAT EQU CYREG_GPIO_PRT3_INTR
EC_INT__MASK EQU 0x04
EC_INT__PC EQU CYREG_GPIO_PRT3_PC
EC_INT__PC2 EQU CYREG_GPIO_PRT3_PC2
EC_INT__PORT EQU 3
EC_INT__PS EQU CYREG_GPIO_PRT3_PS
EC_INT__SHIFT EQU 2

; FW_LED
FW_LED__0__DR EQU CYREG_GPIO_PRT2_DR
FW_LED__0__DR_CLR EQU CYREG_GPIO_PRT2_DR_CLR
FW_LED__0__DR_INV EQU CYREG_GPIO_PRT2_DR_INV
FW_LED__0__DR_SET EQU CYREG_GPIO_PRT2_DR_SET
FW_LED__0__HSIOM EQU CYREG_HSIOM_PORT_SEL2
FW_LED__0__HSIOM_MASK EQU 0x0000000F
FW_LED__0__HSIOM_SHIFT EQU 0
FW_LED__0__INTCFG EQU CYREG_GPIO_PRT2_INTR_CFG
FW_LED__0__INTR EQU CYREG_GPIO_PRT2_INTR
FW_LED__0__INTR_CFG EQU CYREG_GPIO_PRT2_INTR_CFG
FW_LED__0__INTSTAT EQU CYREG_GPIO_PRT2_INTR
FW_LED__0__MASK EQU 0x01
FW_LED__0__PC EQU CYREG_GPIO_PRT2_PC
FW_LED__0__PC2 EQU CYREG_GPIO_PRT2_PC2
FW_LED__0__PORT EQU 2
FW_LED__0__PS EQU CYREG_GPIO_PRT2_PS
FW_LED__0__SHIFT EQU 0
FW_LED__DR EQU CYREG_GPIO_PRT2_DR
FW_LED__DR_CLR EQU CYREG_GPIO_PRT2_DR_CLR
FW_LED__DR_INV EQU CYREG_GPIO_PRT2_DR_INV
FW_LED__DR_SET EQU CYREG_GPIO_PRT2_DR_SET
FW_LED__INTCFG EQU CYREG_GPIO_PRT2_INTR_CFG
FW_LED__INTR EQU CYREG_GPIO_PRT2_INTR
FW_LED__INTR_CFG EQU CYREG_GPIO_PRT2_INTR_CFG
FW_LED__INTSTAT EQU CYREG_GPIO_PRT2_INTR
FW_LED__MASK EQU 0x01
FW_LED__PC EQU CYREG_GPIO_PRT2_PC
FW_LED__PC2 EQU CYREG_GPIO_PRT2_PC2
FW_LED__PORT EQU 2
FW_LED__PS EQU CYREG_GPIO_PRT2_PS
FW_LED__SHIFT EQU 0

; I2C_CFG
I2C_CFG__0__DR EQU CYREG_GPIO_PRT2_DR
I2C_CFG__0__DR_CLR EQU CYREG_GPIO_PRT2_DR_CLR
I2C_CFG__0__DR_INV EQU CYREG_GPIO_PRT2_DR_INV
I2C_CFG__0__DR_SET EQU CYREG_GPIO_PRT2_DR_SET
I2C_CFG__0__HSIOM EQU CYREG_HSIOM_PORT_SEL2
I2C_CFG__0__HSIOM_MASK EQU 0x000000F0
I2C_CFG__0__HSIOM_SHIFT EQU 4
I2C_CFG__0__INTCFG EQU CYREG_GPIO_PRT2_INTR_CFG
I2C_CFG__0__INTR EQU CYREG_GPIO_PRT2_INTR
I2C_CFG__0__INTR_CFG EQU CYREG_GPIO_PRT2_INTR_CFG
I2C_CFG__0__INTSTAT EQU CYREG_GPIO_PRT2_INTR
I2C_CFG__0__MASK EQU 0x02
I2C_CFG__0__PC EQU CYREG_GPIO_PRT2_PC
I2C_CFG__0__PC2 EQU CYREG_GPIO_PRT2_PC2
I2C_CFG__0__PORT EQU 2
I2C_CFG__0__PS EQU CYREG_GPIO_PRT2_PS
I2C_CFG__0__SHIFT EQU 1
I2C_CFG__DR EQU CYREG_GPIO_PRT2_DR
I2C_CFG__DR_CLR EQU CYREG_GPIO_PRT2_DR_CLR
I2C_CFG__DR_INV EQU CYREG_GPIO_PRT2_DR_INV
I2C_CFG__DR_SET EQU CYREG_GPIO_PRT2_DR_SET
I2C_CFG__INTCFG EQU CYREG_GPIO_PRT2_INTR_CFG
I2C_CFG__INTR EQU CYREG_GPIO_PRT2_INTR
I2C_CFG__INTR_CFG EQU CYREG_GPIO_PRT2_INTR_CFG
I2C_CFG__INTSTAT EQU CYREG_GPIO_PRT2_INTR
I2C_CFG__MASK EQU 0x02
I2C_CFG__PC EQU CYREG_GPIO_PRT2_PC
I2C_CFG__PC2 EQU CYREG_GPIO_PRT2_PC2
I2C_CFG__PORT EQU 2
I2C_CFG__PS EQU CYREG_GPIO_PRT2_PS
I2C_CFG__SHIFT EQU 1

; MUX_CTRL_SCB
MUX_CTRL_SCB__CMD_RESP_CTRL EQU CYREG_SCB3_CMD_RESP_CTRL
MUX_CTRL_SCB__CMD_RESP_STATUS EQU CYREG_SCB3_CMD_RESP_STATUS
MUX_CTRL_SCB__CTRL EQU CYREG_SCB3_CTRL
MUX_CTRL_SCB__EZ_DATA0 EQU CYREG_SCB3_EZ_DATA0
MUX_CTRL_SCB__EZ_DATA1 EQU CYREG_SCB3_EZ_DATA1
MUX_CTRL_SCB__EZ_DATA10 EQU CYREG_SCB3_EZ_DATA10
MUX_CTRL_SCB__EZ_DATA100 EQU CYREG_SCB3_EZ_DATA100
MUX_CTRL_SCB__EZ_DATA101 EQU CYREG_SCB3_EZ_DATA101
MUX_CTRL_SCB__EZ_DATA102 EQU CYREG_SCB3_EZ_DATA102
MUX_CTRL_SCB__EZ_DATA103 EQU CYREG_SCB3_EZ_DATA103
MUX_CTRL_SCB__EZ_DATA104 EQU CYREG_SCB3_EZ_DATA104
MUX_CTRL_SCB__EZ_DATA105 EQU CYREG_SCB3_EZ_DATA105
MUX_CTRL_SCB__EZ_DATA106 EQU CYREG_SCB3_EZ_DATA106
MUX_CTRL_SCB__EZ_DATA107 EQU CYREG_SCB3_EZ_DATA107
MUX_CTRL_SCB__EZ_DATA108 EQU CYREG_SCB3_EZ_DATA108
MUX_CTRL_SCB__EZ_DATA109 EQU CYREG_SCB3_EZ_DATA109
MUX_CTRL_SCB__EZ_DATA11 EQU CYREG_SCB3_EZ_DATA11
MUX_CTRL_SCB__EZ_DATA110 EQU CYREG_SCB3_EZ_DATA110
MUX_CTRL_SCB__EZ_DATA111 EQU CYREG_SCB3_EZ_DATA111
MUX_CTRL_SCB__EZ_DATA112 EQU CYREG_SCB3_EZ_DATA112
MUX_CTRL_SCB__EZ_DATA113 EQU CYREG_SCB3_EZ_DATA113
MUX_CTRL_SCB__EZ_DATA114 EQU CYREG_SCB3_EZ_DATA114
MUX_CTRL_SCB__EZ_DATA115 EQU CYREG_SCB3_EZ_DATA115
MUX_CTRL_SCB__EZ_DATA116 EQU CYREG_SCB3_EZ_DATA116
MUX_CTRL_SCB__EZ_DATA117 EQU CYREG_SCB3_EZ_DATA117
MUX_CTRL_SCB__EZ_DATA118 EQU CYREG_SCB3_EZ_DATA118
MUX_CTRL_SCB__EZ_DATA119 EQU CYREG_SCB3_EZ_DATA119
MUX_CTRL_SCB__EZ_DATA12 EQU CYREG_SCB3_EZ_DATA12
MUX_CTRL_SCB__EZ_DATA120 EQU CYREG_SCB3_EZ_DATA120
MUX_CTRL_SCB__EZ_DATA121 EQU CYREG_SCB3_EZ_DATA121
MUX_CTRL_SCB__EZ_DATA122 EQU CYREG_SCB3_EZ_DATA122
MUX_CTRL_SCB__EZ_DATA123 EQU CYREG_SCB3_EZ_DATA123
MUX_CTRL_SCB__EZ_DATA124 EQU CYREG_SCB3_EZ_DATA124
MUX_CTRL_SCB__EZ_DATA125 EQU CYREG_SCB3_EZ_DATA125
MUX_CTRL_SCB__EZ_DATA126 EQU CYREG_SCB3_EZ_DATA126
MUX_CTRL_SCB__EZ_DATA127 EQU CYREG_SCB3_EZ_DATA127
MUX_CTRL_SCB__EZ_DATA128 EQU CYREG_SCB3_EZ_DATA128
MUX_CTRL_SCB__EZ_DATA129 EQU CYREG_SCB3_EZ_DATA129
MUX_CTRL_SCB__EZ_DATA13 EQU CYREG_SCB3_EZ_DATA13
MUX_CTRL_SCB__EZ_DATA130 EQU CYREG_SCB3_EZ_DATA130
MUX_CTRL_SCB__EZ_DATA131 EQU CYREG_SCB3_EZ_DATA131
MUX_CTRL_SCB__EZ_DATA132 EQU CYREG_SCB3_EZ_DATA132
MUX_CTRL_SCB__EZ_DATA133 EQU CYREG_SCB3_EZ_DATA133
MUX_CTRL_SCB__EZ_DATA134 EQU CYREG_SCB3_EZ_DATA134
MUX_CTRL_SCB__EZ_DATA135 EQU CYREG_SCB3_EZ_DATA135
MUX_CTRL_SCB__EZ_DATA136 EQU CYREG_SCB3_EZ_DATA136
MUX_CTRL_SCB__EZ_DATA137 EQU CYREG_SCB3_EZ_DATA137
MUX_CTRL_SCB__EZ_DATA138 EQU CYREG_SCB3_EZ_DATA138
MUX_CTRL_SCB__EZ_DATA139 EQU CYREG_SCB3_EZ_DATA139
MUX_CTRL_SCB__EZ_DATA14 EQU CYREG_SCB3_EZ_DATA14
MUX_CTRL_SCB__EZ_DATA140 EQU CYREG_SCB3_EZ_DATA140
MUX_CTRL_SCB__EZ_DATA141 EQU CYREG_SCB3_EZ_DATA141
MUX_CTRL_SCB__EZ_DATA142 EQU CYREG_SCB3_EZ_DATA142
MUX_CTRL_SCB__EZ_DATA143 EQU CYREG_SCB3_EZ_DATA143
MUX_CTRL_SCB__EZ_DATA144 EQU CYREG_SCB3_EZ_DATA144
MUX_CTRL_SCB__EZ_DATA145 EQU CYREG_SCB3_EZ_DATA145
MUX_CTRL_SCB__EZ_DATA146 EQU CYREG_SCB3_EZ_DATA146
MUX_CTRL_SCB__EZ_DATA147 EQU CYREG_SCB3_EZ_DATA147
MUX_CTRL_SCB__EZ_DATA148 EQU CYREG_SCB3_EZ_DATA148
MUX_CTRL_SCB__EZ_DATA149 EQU CYREG_SCB3_EZ_DATA149
MUX_CTRL_SCB__EZ_DATA15 EQU CYREG_SCB3_EZ_DATA15
MUX_CTRL_SCB__EZ_DATA150 EQU CYREG_SCB3_EZ_DATA150
MUX_CTRL_SCB__EZ_DATA151 EQU CYREG_SCB3_EZ_DATA151
MUX_CTRL_SCB__EZ_DATA152 EQU CYREG_SCB3_EZ_DATA152
MUX_CTRL_SCB__EZ_DATA153 EQU CYREG_SCB3_EZ_DATA153
MUX_CTRL_SCB__EZ_DATA154 EQU CYREG_SCB3_EZ_DATA154
MUX_CTRL_SCB__EZ_DATA155 EQU CYREG_SCB3_EZ_DATA155
MUX_CTRL_SCB__EZ_DATA156 EQU CYREG_SCB3_EZ_DATA156
MUX_CTRL_SCB__EZ_DATA157 EQU CYREG_SCB3_EZ_DATA157
MUX_CTRL_SCB__EZ_DATA158 EQU CYREG_SCB3_EZ_DATA158
MUX_CTRL_SCB__EZ_DATA159 EQU CYREG_SCB3_EZ_DATA159
MUX_CTRL_SCB__EZ_DATA16 EQU CYREG_SCB3_EZ_DATA16
MUX_CTRL_SCB__EZ_DATA160 EQU CYREG_SCB3_EZ_DATA160
MUX_CTRL_SCB__EZ_DATA161 EQU CYREG_SCB3_EZ_DATA161
MUX_CTRL_SCB__EZ_DATA162 EQU CYREG_SCB3_EZ_DATA162
MUX_CTRL_SCB__EZ_DATA163 EQU CYREG_SCB3_EZ_DATA163
MUX_CTRL_SCB__EZ_DATA164 EQU CYREG_SCB3_EZ_DATA164
MUX_CTRL_SCB__EZ_DATA165 EQU CYREG_SCB3_EZ_DATA165
MUX_CTRL_SCB__EZ_DATA166 EQU CYREG_SCB3_EZ_DATA166
MUX_CTRL_SCB__EZ_DATA167 EQU CYREG_SCB3_EZ_DATA167
MUX_CTRL_SCB__EZ_DATA168 EQU CYREG_SCB3_EZ_DATA168
MUX_CTRL_SCB__EZ_DATA169 EQU CYREG_SCB3_EZ_DATA169
MUX_CTRL_SCB__EZ_DATA17 EQU CYREG_SCB3_EZ_DATA17
MUX_CTRL_SCB__EZ_DATA170 EQU CYREG_SCB3_EZ_DATA170
MUX_CTRL_SCB__EZ_DATA171 EQU CYREG_SCB3_EZ_DATA171
MUX_CTRL_SCB__EZ_DATA172 EQU CYREG_SCB3_EZ_DATA172
MUX_CTRL_SCB__EZ_DATA173 EQU CYREG_SCB3_EZ_DATA173
MUX_CTRL_SCB__EZ_DATA174 EQU CYREG_SCB3_EZ_DATA174
MUX_CTRL_SCB__EZ_DATA175 EQU CYREG_SCB3_EZ_DATA175
MUX_CTRL_SCB__EZ_DATA176 EQU CYREG_SCB3_EZ_DATA176
MUX_CTRL_SCB__EZ_DATA177 EQU CYREG_SCB3_EZ_DATA177
MUX_CTRL_SCB__EZ_DATA178 EQU CYREG_SCB3_EZ_DATA178
MUX_CTRL_SCB__EZ_DATA179 EQU CYREG_SCB3_EZ_DATA179
MUX_CTRL_SCB__EZ_DATA18 EQU CYREG_SCB3_EZ_DATA18
MUX_CTRL_SCB__EZ_DATA180 EQU CYREG_SCB3_EZ_DATA180
MUX_CTRL_SCB__EZ_DATA181 EQU CYREG_SCB3_EZ_DATA181
MUX_CTRL_SCB__EZ_DATA182 EQU CYREG_SCB3_EZ_DATA182
MUX_CTRL_SCB__EZ_DATA183 EQU CYREG_SCB3_EZ_DATA183
MUX_CTRL_SCB__EZ_DATA184 EQU CYREG_SCB3_EZ_DATA184
MUX_CTRL_SCB__EZ_DATA185 EQU CYREG_SCB3_EZ_DATA185
MUX_CTRL_SCB__EZ_DATA186 EQU CYREG_SCB3_EZ_DATA186
MUX_CTRL_SCB__EZ_DATA187 EQU CYREG_SCB3_EZ_DATA187
MUX_CTRL_SCB__EZ_DATA188 EQU CYREG_SCB3_EZ_DATA188
MUX_CTRL_SCB__EZ_DATA189 EQU CYREG_SCB3_EZ_DATA189
MUX_CTRL_SCB__EZ_DATA19 EQU CYREG_SCB3_EZ_DATA19
MUX_CTRL_SCB__EZ_DATA190 EQU CYREG_SCB3_EZ_DATA190
MUX_CTRL_SCB__EZ_DATA191 EQU CYREG_SCB3_EZ_DATA191
MUX_CTRL_SCB__EZ_DATA192 EQU CYREG_SCB3_EZ_DATA192
MUX_CTRL_SCB__EZ_DATA193 EQU CYREG_SCB3_EZ_DATA193
MUX_CTRL_SCB__EZ_DATA194 EQU CYREG_SCB3_EZ_DATA194
MUX_CTRL_SCB__EZ_DATA195 EQU CYREG_SCB3_EZ_DATA195
MUX_CTRL_SCB__EZ_DATA196 EQU CYREG_SCB3_EZ_DATA196
MUX_CTRL_SCB__EZ_DATA197 EQU CYREG_SCB3_EZ_DATA197
MUX_CTRL_SCB__EZ_DATA198 EQU CYREG_SCB3_EZ_DATA198
MUX_CTRL_SCB__EZ_DATA199 EQU CYREG_SCB3_EZ_DATA199
MUX_CTRL_SCB__EZ_DATA2 EQU CYREG_SCB3_EZ_DATA2
MUX_CTRL_SCB__EZ_DATA20 EQU CYREG_SCB3_EZ_DATA20
MUX_CTRL_SCB__EZ_DATA200 EQU CYREG_SCB3_EZ_DATA200
MUX_CTRL_SCB__EZ_DATA201 EQU CYREG_SCB3_EZ_DATA201
MUX_CTRL_SCB__EZ_DATA202 EQU CYREG_SCB3_EZ_DATA202
MUX_CTRL_SCB__EZ_DATA203 EQU CYREG_SCB3_EZ_DATA203
MUX_CTRL_SCB__EZ_DATA204 EQU CYREG_SCB3_EZ_DATA204
MUX_CTRL_SCB__EZ_DATA205 EQU CYREG_SCB3_EZ_DATA205
MUX_CTRL_SCB__EZ_DATA206 EQU CYREG_SCB3_EZ_DATA206
MUX_CTRL_SCB__EZ_DATA207 EQU CYREG_SCB3_EZ_DATA207
MUX_CTRL_SCB__EZ_DATA208 EQU CYREG_SCB3_EZ_DATA208
MUX_CTRL_SCB__EZ_DATA209 EQU CYREG_SCB3_EZ_DATA209
MUX_CTRL_SCB__EZ_DATA21 EQU CYREG_SCB3_EZ_DATA21
MUX_CTRL_SCB__EZ_DATA210 EQU CYREG_SCB3_EZ_DATA210
MUX_CTRL_SCB__EZ_DATA211 EQU CYREG_SCB3_EZ_DATA211
MUX_CTRL_SCB__EZ_DATA212 EQU CYREG_SCB3_EZ_DATA212
MUX_CTRL_SCB__EZ_DATA213 EQU CYREG_SCB3_EZ_DATA213
MUX_CTRL_SCB__EZ_DATA214 EQU CYREG_SCB3_EZ_DATA214
MUX_CTRL_SCB__EZ_DATA215 EQU CYREG_SCB3_EZ_DATA215
MUX_CTRL_SCB__EZ_DATA216 EQU CYREG_SCB3_EZ_DATA216
MUX_CTRL_SCB__EZ_DATA217 EQU CYREG_SCB3_EZ_DATA217
MUX_CTRL_SCB__EZ_DATA218 EQU CYREG_SCB3_EZ_DATA218
MUX_CTRL_SCB__EZ_DATA219 EQU CYREG_SCB3_EZ_DATA219
MUX_CTRL_SCB__EZ_DATA22 EQU CYREG_SCB3_EZ_DATA22
MUX_CTRL_SCB__EZ_DATA220 EQU CYREG_SCB3_EZ_DATA220
MUX_CTRL_SCB__EZ_DATA221 EQU CYREG_SCB3_EZ_DATA221
MUX_CTRL_SCB__EZ_DATA222 EQU CYREG_SCB3_EZ_DATA222
MUX_CTRL_SCB__EZ_DATA223 EQU CYREG_SCB3_EZ_DATA223
MUX_CTRL_SCB__EZ_DATA224 EQU CYREG_SCB3_EZ_DATA224
MUX_CTRL_SCB__EZ_DATA225 EQU CYREG_SCB3_EZ_DATA225
MUX_CTRL_SCB__EZ_DATA226 EQU CYREG_SCB3_EZ_DATA226
MUX_CTRL_SCB__EZ_DATA227 EQU CYREG_SCB3_EZ_DATA227
MUX_CTRL_SCB__EZ_DATA228 EQU CYREG_SCB3_EZ_DATA228
MUX_CTRL_SCB__EZ_DATA229 EQU CYREG_SCB3_EZ_DATA229
MUX_CTRL_SCB__EZ_DATA23 EQU CYREG_SCB3_EZ_DATA23
MUX_CTRL_SCB__EZ_DATA230 EQU CYREG_SCB3_EZ_DATA230
MUX_CTRL_SCB__EZ_DATA231 EQU CYREG_SCB3_EZ_DATA231
MUX_CTRL_SCB__EZ_DATA232 EQU CYREG_SCB3_EZ_DATA232
MUX_CTRL_SCB__EZ_DATA233 EQU CYREG_SCB3_EZ_DATA233
MUX_CTRL_SCB__EZ_DATA234 EQU CYREG_SCB3_EZ_DATA234
MUX_CTRL_SCB__EZ_DATA235 EQU CYREG_SCB3_EZ_DATA235
MUX_CTRL_SCB__EZ_DATA236 EQU CYREG_SCB3_EZ_DATA236
MUX_CTRL_SCB__EZ_DATA237 EQU CYREG_SCB3_EZ_DATA237
MUX_CTRL_SCB__EZ_DATA238 EQU CYREG_SCB3_EZ_DATA238
MUX_CTRL_SCB__EZ_DATA239 EQU CYREG_SCB3_EZ_DATA239
MUX_CTRL_SCB__EZ_DATA24 EQU CYREG_SCB3_EZ_DATA24
MUX_CTRL_SCB__EZ_DATA240 EQU CYREG_SCB3_EZ_DATA240
MUX_CTRL_SCB__EZ_DATA241 EQU CYREG_SCB3_EZ_DATA241
MUX_CTRL_SCB__EZ_DATA242 EQU CYREG_SCB3_EZ_DATA242
MUX_CTRL_SCB__EZ_DATA243 EQU CYREG_SCB3_EZ_DATA243
MUX_CTRL_SCB__EZ_DATA244 EQU CYREG_SCB3_EZ_DATA244
MUX_CTRL_SCB__EZ_DATA245 EQU CYREG_SCB3_EZ_DATA245
MUX_CTRL_SCB__EZ_DATA246 EQU CYREG_SCB3_EZ_DATA246
MUX_CTRL_SCB__EZ_DATA247 EQU CYREG_SCB3_EZ_DATA247
MUX_CTRL_SCB__EZ_DATA248 EQU CYREG_SCB3_EZ_DATA248
MUX_CTRL_SCB__EZ_DATA249 EQU CYREG_SCB3_EZ_DATA249
MUX_CTRL_SCB__EZ_DATA25 EQU CYREG_SCB3_EZ_DATA25
MUX_CTRL_SCB__EZ_DATA250 EQU CYREG_SCB3_EZ_DATA250
MUX_CTRL_SCB__EZ_DATA251 EQU CYREG_SCB3_EZ_DATA251
MUX_CTRL_SCB__EZ_DATA252 EQU CYREG_SCB3_EZ_DATA252
MUX_CTRL_SCB__EZ_DATA253 EQU CYREG_SCB3_EZ_DATA253
MUX_CTRL_SCB__EZ_DATA254 EQU CYREG_SCB3_EZ_DATA254
MUX_CTRL_SCB__EZ_DATA255 EQU CYREG_SCB3_EZ_DATA255
MUX_CTRL_SCB__EZ_DATA26 EQU CYREG_SCB3_EZ_DATA26
MUX_CTRL_SCB__EZ_DATA27 EQU CYREG_SCB3_EZ_DATA27
MUX_CTRL_SCB__EZ_DATA28 EQU CYREG_SCB3_EZ_DATA28
MUX_CTRL_SCB__EZ_DATA29 EQU CYREG_SCB3_EZ_DATA29
MUX_CTRL_SCB__EZ_DATA3 EQU CYREG_SCB3_EZ_DATA3
MUX_CTRL_SCB__EZ_DATA30 EQU CYREG_SCB3_EZ_DATA30
MUX_CTRL_SCB__EZ_DATA31 EQU CYREG_SCB3_EZ_DATA31
MUX_CTRL_SCB__EZ_DATA32 EQU CYREG_SCB3_EZ_DATA32
MUX_CTRL_SCB__EZ_DATA33 EQU CYREG_SCB3_EZ_DATA33
MUX_CTRL_SCB__EZ_DATA34 EQU CYREG_SCB3_EZ_DATA34
MUX_CTRL_SCB__EZ_DATA35 EQU CYREG_SCB3_EZ_DATA35
MUX_CTRL_SCB__EZ_DATA36 EQU CYREG_SCB3_EZ_DATA36
MUX_CTRL_SCB__EZ_DATA37 EQU CYREG_SCB3_EZ_DATA37
MUX_CTRL_SCB__EZ_DATA38 EQU CYREG_SCB3_EZ_DATA38
MUX_CTRL_SCB__EZ_DATA39 EQU CYREG_SCB3_EZ_DATA39
MUX_CTRL_SCB__EZ_DATA4 EQU CYREG_SCB3_EZ_DATA4
MUX_CTRL_SCB__EZ_DATA40 EQU CYREG_SCB3_EZ_DATA40
MUX_CTRL_SCB__EZ_DATA41 EQU CYREG_SCB3_EZ_DATA41
MUX_CTRL_SCB__EZ_DATA42 EQU CYREG_SCB3_EZ_DATA42
MUX_CTRL_SCB__EZ_DATA43 EQU CYREG_SCB3_EZ_DATA43
MUX_CTRL_SCB__EZ_DATA44 EQU CYREG_SCB3_EZ_DATA44
MUX_CTRL_SCB__EZ_DATA45 EQU CYREG_SCB3_EZ_DATA45
MUX_CTRL_SCB__EZ_DATA46 EQU CYREG_SCB3_EZ_DATA46
MUX_CTRL_SCB__EZ_DATA47 EQU CYREG_SCB3_EZ_DATA47
MUX_CTRL_SCB__EZ_DATA48 EQU CYREG_SCB3_EZ_DATA48
MUX_CTRL_SCB__EZ_DATA49 EQU CYREG_SCB3_EZ_DATA49
MUX_CTRL_SCB__EZ_DATA5 EQU CYREG_SCB3_EZ_DATA5
MUX_CTRL_SCB__EZ_DATA50 EQU CYREG_SCB3_EZ_DATA50
MUX_CTRL_SCB__EZ_DATA51 EQU CYREG_SCB3_EZ_DATA51
MUX_CTRL_SCB__EZ_DATA52 EQU CYREG_SCB3_EZ_DATA52
MUX_CTRL_SCB__EZ_DATA53 EQU CYREG_SCB3_EZ_DATA53
MUX_CTRL_SCB__EZ_DATA54 EQU CYREG_SCB3_EZ_DATA54
MUX_CTRL_SCB__EZ_DATA55 EQU CYREG_SCB3_EZ_DATA55
MUX_CTRL_SCB__EZ_DATA56 EQU CYREG_SCB3_EZ_DATA56
MUX_CTRL_SCB__EZ_DATA57 EQU CYREG_SCB3_EZ_DATA57
MUX_CTRL_SCB__EZ_DATA58 EQU CYREG_SCB3_EZ_DATA58
MUX_CTRL_SCB__EZ_DATA59 EQU CYREG_SCB3_EZ_DATA59
MUX_CTRL_SCB__EZ_DATA6 EQU CYREG_SCB3_EZ_DATA6
MUX_CTRL_SCB__EZ_DATA60 EQU CYREG_SCB3_EZ_DATA60
MUX_CTRL_SCB__EZ_DATA61 EQU CYREG_SCB3_EZ_DATA61
MUX_CTRL_SCB__EZ_DATA62 EQU CYREG_SCB3_EZ_DATA62
MUX_CTRL_SCB__EZ_DATA63 EQU CYREG_SCB3_EZ_DATA63
MUX_CTRL_SCB__EZ_DATA64 EQU CYREG_SCB3_EZ_DATA64
MUX_CTRL_SCB__EZ_DATA65 EQU CYREG_SCB3_EZ_DATA65
MUX_CTRL_SCB__EZ_DATA66 EQU CYREG_SCB3_EZ_DATA66
MUX_CTRL_SCB__EZ_DATA67 EQU CYREG_SCB3_EZ_DATA67
MUX_CTRL_SCB__EZ_DATA68 EQU CYREG_SCB3_EZ_DATA68
MUX_CTRL_SCB__EZ_DATA69 EQU CYREG_SCB3_EZ_DATA69
MUX_CTRL_SCB__EZ_DATA7 EQU CYREG_SCB3_EZ_DATA7
MUX_CTRL_SCB__EZ_DATA70 EQU CYREG_SCB3_EZ_DATA70
MUX_CTRL_SCB__EZ_DATA71 EQU CYREG_SCB3_EZ_DATA71
MUX_CTRL_SCB__EZ_DATA72 EQU CYREG_SCB3_EZ_DATA72
MUX_CTRL_SCB__EZ_DATA73 EQU CYREG_SCB3_EZ_DATA73
MUX_CTRL_SCB__EZ_DATA74 EQU CYREG_SCB3_EZ_DATA74
MUX_CTRL_SCB__EZ_DATA75 EQU CYREG_SCB3_EZ_DATA75
MUX_CTRL_SCB__EZ_DATA76 EQU CYREG_SCB3_EZ_DATA76
MUX_CTRL_SCB__EZ_DATA77 EQU CYREG_SCB3_EZ_DATA77
MUX_CTRL_SCB__EZ_DATA78 EQU CYREG_SCB3_EZ_DATA78
MUX_CTRL_SCB__EZ_DATA79 EQU CYREG_SCB3_EZ_DATA79
MUX_CTRL_SCB__EZ_DATA8 EQU CYREG_SCB3_EZ_DATA8
MUX_CTRL_SCB__EZ_DATA80 EQU CYREG_SCB3_EZ_DATA80
MUX_CTRL_SCB__EZ_DATA81 EQU CYREG_SCB3_EZ_DATA81
MUX_CTRL_SCB__EZ_DATA82 EQU CYREG_SCB3_EZ_DATA82
MUX_CTRL_SCB__EZ_DATA83 EQU CYREG_SCB3_EZ_DATA83
MUX_CTRL_SCB__EZ_DATA84 EQU CYREG_SCB3_EZ_DATA84
MUX_CTRL_SCB__EZ_DATA85 EQU CYREG_SCB3_EZ_DATA85
MUX_CTRL_SCB__EZ_DATA86 EQU CYREG_SCB3_EZ_DATA86
MUX_CTRL_SCB__EZ_DATA87 EQU CYREG_SCB3_EZ_DATA87
MUX_CTRL_SCB__EZ_DATA88 EQU CYREG_SCB3_EZ_DATA88
MUX_CTRL_SCB__EZ_DATA89 EQU CYREG_SCB3_EZ_DATA89
MUX_CTRL_SCB__EZ_DATA9 EQU CYREG_SCB3_EZ_DATA9
MUX_CTRL_SCB__EZ_DATA90 EQU CYREG_SCB3_EZ_DATA90
MUX_CTRL_SCB__EZ_DATA91 EQU CYREG_SCB3_EZ_DATA91
MUX_CTRL_SCB__EZ_DATA92 EQU CYREG_SCB3_EZ_DATA92
MUX_CTRL_SCB__EZ_DATA93 EQU CYREG_SCB3_EZ_DATA93
MUX_CTRL_SCB__EZ_DATA94 EQU CYREG_SCB3_EZ_DATA94
MUX_CTRL_SCB__EZ_DATA95 EQU CYREG_SCB3_EZ_DATA95
MUX_CTRL_SCB__EZ_DATA96 EQU CYREG_SCB3_EZ_DATA96
MUX_CTRL_SCB__EZ_DATA97 EQU CYREG_SCB3_EZ_DATA97
MUX_CTRL_SCB__EZ_DATA98 EQU CYREG_SCB3_EZ_DATA98
MUX_CTRL_SCB__EZ_DATA99 EQU CYREG_SCB3_EZ_DATA99
MUX_CTRL_SCB__I2C_CFG EQU CYREG_SCB3_I2C_CFG
MUX_CTRL_SCB__I2C_CTRL EQU CYREG_SCB3_I2C_CTRL
MUX_CTRL_SCB__I2C_M_CMD EQU CYREG_SCB3_I2C_M_CMD
MUX_CTRL_SCB__I2C_S_CMD EQU CYREG_SCB3_I2C_S_CMD
MUX_CTRL_SCB__I2C_STATUS EQU CYREG_SCB3_I2C_STATUS
MUX_CTRL_SCB__INTR_CAUSE EQU CYREG_SCB3_INTR_CAUSE
MUX_CTRL_SCB__INTR_I2C_EC EQU CYREG_SCB3_INTR_I2C_EC
MUX_CTRL_SCB__INTR_I2C_EC_MASK EQU CYREG_SCB3_INTR_I2C_EC_MASK
MUX_CTRL_SCB__INTR_I2C_EC_MASKED EQU CYREG_SCB3_INTR_I2C_EC_MASKED
MUX_CTRL_SCB__INTR_M EQU CYREG_SCB3_INTR_M
MUX_CTRL_SCB__INTR_M_MASK EQU CYREG_SCB3_INTR_M_MASK
MUX_CTRL_SCB__INTR_M_MASKED EQU CYREG_SCB3_INTR_M_MASKED
MUX_CTRL_SCB__INTR_M_SET EQU CYREG_SCB3_INTR_M_SET
MUX_CTRL_SCB__INTR_RX EQU CYREG_SCB3_INTR_RX
MUX_CTRL_SCB__INTR_RX_MASK EQU CYREG_SCB3_INTR_RX_MASK
MUX_CTRL_SCB__INTR_RX_MASKED EQU CYREG_SCB3_INTR_RX_MASKED
MUX_CTRL_SCB__INTR_RX_SET EQU CYREG_SCB3_INTR_RX_SET
MUX_CTRL_SCB__INTR_S EQU CYREG_SCB3_INTR_S
MUX_CTRL_SCB__INTR_S_MASK EQU CYREG_SCB3_INTR_S_MASK
MUX_CTRL_SCB__INTR_S_MASKED EQU CYREG_SCB3_INTR_S_MASKED
MUX_CTRL_SCB__INTR_S_SET EQU CYREG_SCB3_INTR_S_SET
MUX_CTRL_SCB__INTR_SPI_EC EQU CYREG_SCB3_INTR_SPI_EC
MUX_CTRL_SCB__INTR_SPI_EC_MASK EQU CYREG_SCB3_INTR_SPI_EC_MASK
MUX_CTRL_SCB__INTR_SPI_EC_MASKED EQU CYREG_SCB3_INTR_SPI_EC_MASKED
MUX_CTRL_SCB__INTR_TX EQU CYREG_SCB3_INTR_TX
MUX_CTRL_SCB__INTR_TX_MASK EQU CYREG_SCB3_INTR_TX_MASK
MUX_CTRL_SCB__INTR_TX_MASKED EQU CYREG_SCB3_INTR_TX_MASKED
MUX_CTRL_SCB__INTR_TX_SET EQU CYREG_SCB3_INTR_TX_SET
MUX_CTRL_SCB__RX_CTRL EQU CYREG_SCB3_RX_CTRL
MUX_CTRL_SCB__RX_FIFO_CTRL EQU CYREG_SCB3_RX_FIFO_CTRL
MUX_CTRL_SCB__RX_FIFO_RD EQU CYREG_SCB3_RX_FIFO_RD
MUX_CTRL_SCB__RX_FIFO_RD_SILENT EQU CYREG_SCB3_RX_FIFO_RD_SILENT
MUX_CTRL_SCB__RX_FIFO_STATUS EQU CYREG_SCB3_RX_FIFO_STATUS
MUX_CTRL_SCB__RX_MATCH EQU CYREG_SCB3_RX_MATCH
MUX_CTRL_SCB__SPI_CTRL EQU CYREG_SCB3_SPI_CTRL
MUX_CTRL_SCB__SPI_STATUS EQU CYREG_SCB3_SPI_STATUS
MUX_CTRL_SCB__SS0_POSISTION EQU 0
MUX_CTRL_SCB__SS1_POSISTION EQU 1
MUX_CTRL_SCB__SS2_POSISTION EQU 2
MUX_CTRL_SCB__SS3_POSISTION EQU 3
MUX_CTRL_SCB__STATUS EQU CYREG_SCB3_STATUS
MUX_CTRL_SCB__TX_CTRL EQU CYREG_SCB3_TX_CTRL
MUX_CTRL_SCB__TX_FIFO_CTRL EQU CYREG_SCB3_TX_FIFO_CTRL
MUX_CTRL_SCB__TX_FIFO_STATUS EQU CYREG_SCB3_TX_FIFO_STATUS
MUX_CTRL_SCB__TX_FIFO_WR EQU CYREG_SCB3_TX_FIFO_WR
MUX_CTRL_SCB__UART_CTRL EQU CYREG_SCB3_UART_CTRL
MUX_CTRL_SCB__UART_FLOW_CTRL EQU CYREG_SCB3_UART_FLOW_CTRL
MUX_CTRL_SCB__UART_RX_CTRL EQU CYREG_SCB3_UART_RX_CTRL
MUX_CTRL_SCB__UART_RX_STATUS EQU CYREG_SCB3_UART_RX_STATUS
MUX_CTRL_SCB__UART_TX_CTRL EQU CYREG_SCB3_UART_TX_CTRL

; MUX_CTRL_SCB_IRQ
MUX_CTRL_SCB_IRQ__INTC_CLR_EN_REG EQU CYREG_CM0_ICER
MUX_CTRL_SCB_IRQ__INTC_CLR_PD_REG EQU CYREG_CM0_ICPR
MUX_CTRL_SCB_IRQ__INTC_MASK EQU 0x800
MUX_CTRL_SCB_IRQ__INTC_NUMBER EQU 11
MUX_CTRL_SCB_IRQ__INTC_PRIOR_MASK EQU 0xC0000000
MUX_CTRL_SCB_IRQ__INTC_PRIOR_NUM EQU 3
MUX_CTRL_SCB_IRQ__INTC_PRIOR_REG EQU CYREG_CM0_IPR2
MUX_CTRL_SCB_IRQ__INTC_SET_EN_REG EQU CYREG_CM0_ISER
MUX_CTRL_SCB_IRQ__INTC_SET_PD_REG EQU CYREG_CM0_ISPR

; MUX_CTRL_SCBCLK
MUX_CTRL_SCBCLK__CTRL_REGISTER EQU CYREG_PERI_PCLK_CTL3
MUX_CTRL_SCBCLK__DIV_ID EQU 0x00000003
MUX_CTRL_SCBCLK__DIV_REGISTER EQU CYREG_PERI_DIV_8_CTL3
MUX_CTRL_SCBCLK__PA_DIV_ID EQU 0x000000FF

; MUX_CTRL_scl
MUX_CTRL_scl__0__DR EQU CYREG_GPIO_PRT1_DR
MUX_CTRL_scl__0__DR_CLR EQU CYREG_GPIO_PRT1_DR_CLR
MUX_CTRL_scl__0__DR_INV EQU CYREG_GPIO_PRT1_DR_INV
MUX_CTRL_scl__0__DR_SET EQU CYREG_GPIO_PRT1_DR_SET
MUX_CTRL_scl__0__HSIOM EQU CYREG_HSIOM_PORT_SEL1
MUX_CTRL_scl__0__HSIOM_GPIO EQU 0
MUX_CTRL_scl__0__HSIOM_I2C EQU 15
MUX_CTRL_scl__0__HSIOM_I2C_SCL EQU 15
MUX_CTRL_scl__0__HSIOM_MASK EQU 0x00000F00
MUX_CTRL_scl__0__HSIOM_SHIFT EQU 8
MUX_CTRL_scl__0__HSIOM_SPI EQU 14
MUX_CTRL_scl__0__HSIOM_SPI_MOSI EQU 14
MUX_CTRL_scl__0__HSIOM_UART EQU 10
MUX_CTRL_scl__0__HSIOM_UART_CTS EQU 10
MUX_CTRL_scl__0__INTCFG EQU CYREG_GPIO_PRT1_INTR_CFG
MUX_CTRL_scl__0__INTR EQU CYREG_GPIO_PRT1_INTR
MUX_CTRL_scl__0__INTR_CFG EQU CYREG_GPIO_PRT1_INTR_CFG
MUX_CTRL_scl__0__INTSTAT EQU CYREG_GPIO_PRT1_INTR
MUX_CTRL_scl__0__MASK EQU 0x04
MUX_CTRL_scl__0__PC EQU CYREG_GPIO_PRT1_PC
MUX_CTRL_scl__0__PC2 EQU CYREG_GPIO_PRT1_PC2
MUX_CTRL_scl__0__PORT EQU 1
MUX_CTRL_scl__0__PS EQU CYREG_GPIO_PRT1_PS
MUX_CTRL_scl__0__SHIFT EQU 2
MUX_CTRL_scl__DR EQU CYREG_GPIO_PRT1_DR
MUX_CTRL_scl__DR_CLR EQU CYREG_GPIO_PRT1_DR_CLR
MUX_CTRL_scl__DR_INV EQU CYREG_GPIO_PRT1_DR_INV
MUX_CTRL_scl__DR_SET EQU CYREG_GPIO_PRT1_DR_SET
MUX_CTRL_scl__INTCFG EQU CYREG_GPIO_PRT1_INTR_CFG
MUX_CTRL_scl__INTR EQU CYREG_GPIO_PRT1_INTR
MUX_CTRL_scl__INTR_CFG EQU CYREG_GPIO_PRT1_INTR_CFG
MUX_CTRL_scl__INTSTAT EQU CYREG_GPIO_PRT1_INTR
MUX_CTRL_scl__MASK EQU 0x04
MUX_CTRL_scl__PC EQU CYREG_GPIO_PRT1_PC
MUX_CTRL_scl__PC2 EQU CYREG_GPIO_PRT1_PC2
MUX_CTRL_scl__PORT EQU 1
MUX_CTRL_scl__PS EQU CYREG_GPIO_PRT1_PS
MUX_CTRL_scl__SHIFT EQU 2

; MUX_CTRL_sda
MUX_CTRL_sda__0__DR EQU CYREG_GPIO_PRT1_DR
MUX_CTRL_sda__0__DR_CLR EQU CYREG_GPIO_PRT1_DR_CLR
MUX_CTRL_sda__0__DR_INV EQU CYREG_GPIO_PRT1_DR_INV
MUX_CTRL_sda__0__DR_SET EQU CYREG_GPIO_PRT1_DR_SET
MUX_CTRL_sda__0__HSIOM EQU CYREG_HSIOM_PORT_SEL1
MUX_CTRL_sda__0__HSIOM_GPIO EQU 0
MUX_CTRL_sda__0__HSIOM_I2C EQU 15
MUX_CTRL_sda__0__HSIOM_I2C_SDA EQU 15
MUX_CTRL_sda__0__HSIOM_MASK EQU 0x0000F000
MUX_CTRL_sda__0__HSIOM_SHIFT EQU 12
MUX_CTRL_sda__0__HSIOM_SPI EQU 14
MUX_CTRL_sda__0__HSIOM_SPI_CLK EQU 14
MUX_CTRL_sda__0__HSIOM_UART EQU 10
MUX_CTRL_sda__0__HSIOM_UART_RTS EQU 10
MUX_CTRL_sda__0__INTCFG EQU CYREG_GPIO_PRT1_INTR_CFG
MUX_CTRL_sda__0__INTR EQU CYREG_GPIO_PRT1_INTR
MUX_CTRL_sda__0__INTR_CFG EQU CYREG_GPIO_PRT1_INTR_CFG
MUX_CTRL_sda__0__INTSTAT EQU CYREG_GPIO_PRT1_INTR
MUX_CTRL_sda__0__MASK EQU 0x08
MUX_CTRL_sda__0__PC EQU CYREG_GPIO_PRT1_PC
MUX_CTRL_sda__0__PC2 EQU CYREG_GPIO_PRT1_PC2
MUX_CTRL_sda__0__PORT EQU 1
MUX_CTRL_sda__0__PS EQU CYREG_GPIO_PRT1_PS
MUX_CTRL_sda__0__SHIFT EQU 3
MUX_CTRL_sda__DR EQU CYREG_GPIO_PRT1_DR
MUX_CTRL_sda__DR_CLR EQU CYREG_GPIO_PRT1_DR_CLR
MUX_CTRL_sda__DR_INV EQU CYREG_GPIO_PRT1_DR_INV
MUX_CTRL_sda__DR_SET EQU CYREG_GPIO_PRT1_DR_SET
MUX_CTRL_sda__INTCFG EQU CYREG_GPIO_PRT1_INTR_CFG
MUX_CTRL_sda__INTR EQU CYREG_GPIO_PRT1_INTR
MUX_CTRL_sda__INTR_CFG EQU CYREG_GPIO_PRT1_INTR_CFG
MUX_CTRL_sda__INTSTAT EQU CYREG_GPIO_PRT1_INTR
MUX_CTRL_sda__MASK EQU 0x08
MUX_CTRL_sda__PC EQU CYREG_GPIO_PRT1_PC
MUX_CTRL_sda__PC2 EQU CYREG_GPIO_PRT1_PC2
MUX_CTRL_sda__PORT EQU 1
MUX_CTRL_sda__PS EQU CYREG_GPIO_PRT1_PS
MUX_CTRL_sda__SHIFT EQU 3

; VSEL1_P1
VSEL1_P1__0__DR EQU CYREG_GPIO_PRT0_DR
VSEL1_P1__0__DR_CLR EQU CYREG_GPIO_PRT0_DR_CLR
VSEL1_P1__0__DR_INV EQU CYREG_GPIO_PRT0_DR_INV
VSEL1_P1__0__DR_SET EQU CYREG_GPIO_PRT0_DR_SET
VSEL1_P1__0__HSIOM EQU CYREG_HSIOM_PORT_SEL0
VSEL1_P1__0__HSIOM_MASK EQU 0x000000F0
VSEL1_P1__0__HSIOM_SHIFT EQU 4
VSEL1_P1__0__INTCFG EQU CYREG_GPIO_PRT0_INTR_CFG
VSEL1_P1__0__INTR EQU CYREG_GPIO_PRT0_INTR
VSEL1_P1__0__INTR_CFG EQU CYREG_GPIO_PRT0_INTR_CFG
VSEL1_P1__0__INTSTAT EQU CYREG_GPIO_PRT0_INTR
VSEL1_P1__0__MASK EQU 0x02
VSEL1_P1__0__PC EQU CYREG_GPIO_PRT0_PC
VSEL1_P1__0__PC2 EQU CYREG_GPIO_PRT0_PC2
VSEL1_P1__0__PORT EQU 0
VSEL1_P1__0__PS EQU CYREG_GPIO_PRT0_PS
VSEL1_P1__0__SHIFT EQU 1
VSEL1_P1__DR EQU CYREG_GPIO_PRT0_DR
VSEL1_P1__DR_CLR EQU CYREG_GPIO_PRT0_DR_CLR
VSEL1_P1__DR_INV EQU CYREG_GPIO_PRT0_DR_INV
VSEL1_P1__DR_SET EQU CYREG_GPIO_PRT0_DR_SET
VSEL1_P1__INTCFG EQU CYREG_GPIO_PRT0_INTR_CFG
VSEL1_P1__INTR EQU CYREG_GPIO_PRT0_INTR
VSEL1_P1__INTR_CFG EQU CYREG_GPIO_PRT0_INTR_CFG
VSEL1_P1__INTSTAT EQU CYREG_GPIO_PRT0_INTR
VSEL1_P1__MASK EQU 0x02
VSEL1_P1__PC EQU CYREG_GPIO_PRT0_PC
VSEL1_P1__PC2 EQU CYREG_GPIO_PRT0_PC2
VSEL1_P1__PORT EQU 0
VSEL1_P1__PS EQU CYREG_GPIO_PRT0_PS
VSEL1_P1__SHIFT EQU 1

; VSEL2_P1
VSEL2_P1__0__DR EQU CYREG_GPIO_PRT0_DR
VSEL2_P1__0__DR_CLR EQU CYREG_GPIO_PRT0_DR_CLR
VSEL2_P1__0__DR_INV EQU CYREG_GPIO_PRT0_DR_INV
VSEL2_P1__0__DR_SET EQU CYREG_GPIO_PRT0_DR_SET
VSEL2_P1__0__HSIOM EQU CYREG_HSIOM_PORT_SEL0
VSEL2_P1__0__HSIOM_MASK EQU 0x0000000F
VSEL2_P1__0__HSIOM_SHIFT EQU 0
VSEL2_P1__0__INTCFG EQU CYREG_GPIO_PRT0_INTR_CFG
VSEL2_P1__0__INTR EQU CYREG_GPIO_PRT0_INTR
VSEL2_P1__0__INTR_CFG EQU CYREG_GPIO_PRT0_INTR_CFG
VSEL2_P1__0__INTSTAT EQU CYREG_GPIO_PRT0_INTR
VSEL2_P1__0__MASK EQU 0x01
VSEL2_P1__0__PC EQU CYREG_GPIO_PRT0_PC
VSEL2_P1__0__PC2 EQU CYREG_GPIO_PRT0_PC2
VSEL2_P1__0__PORT EQU 0
VSEL2_P1__0__PS EQU CYREG_GPIO_PRT0_PS
VSEL2_P1__0__SHIFT EQU 0
VSEL2_P1__DR EQU CYREG_GPIO_PRT0_DR
VSEL2_P1__DR_CLR EQU CYREG_GPIO_PRT0_DR_CLR
VSEL2_P1__DR_INV EQU CYREG_GPIO_PRT0_DR_INV
VSEL2_P1__DR_SET EQU CYREG_GPIO_PRT0_DR_SET
VSEL2_P1__INTCFG EQU CYREG_GPIO_PRT0_INTR_CFG
VSEL2_P1__INTR EQU CYREG_GPIO_PRT0_INTR
VSEL2_P1__INTR_CFG EQU CYREG_GPIO_PRT0_INTR_CFG
VSEL2_P1__INTSTAT EQU CYREG_GPIO_PRT0_INTR
VSEL2_P1__MASK EQU 0x01
VSEL2_P1__PC EQU CYREG_GPIO_PRT0_PC
VSEL2_P1__PC2 EQU CYREG_GPIO_PRT0_PC2
VSEL2_P1__PORT EQU 0
VSEL2_P1__PS EQU CYREG_GPIO_PRT0_PS
VSEL2_P1__SHIFT EQU 0

; PGOOD_LED
PGOOD_LED__0__DR EQU CYREG_GPIO_PRT2_DR
PGOOD_LED__0__DR_CLR EQU CYREG_GPIO_PRT2_DR_CLR
PGOOD_LED__0__DR_INV EQU CYREG_GPIO_PRT2_DR_INV
PGOOD_LED__0__DR_SET EQU CYREG_GPIO_PRT2_DR_SET
PGOOD_LED__0__HSIOM EQU CYREG_HSIOM_PORT_SEL2
PGOOD_LED__0__HSIOM_MASK EQU 0x000F0000
PGOOD_LED__0__HSIOM_SHIFT EQU 16
PGOOD_LED__0__INTCFG EQU CYREG_GPIO_PRT2_INTR_CFG
PGOOD_LED__0__INTR EQU CYREG_GPIO_PRT2_INTR
PGOOD_LED__0__INTR_CFG EQU CYREG_GPIO_PRT2_INTR_CFG
PGOOD_LED__0__INTSTAT EQU CYREG_GPIO_PRT2_INTR
PGOOD_LED__0__MASK EQU 0x10
PGOOD_LED__0__PC EQU CYREG_GPIO_PRT2_PC
PGOOD_LED__0__PC2 EQU CYREG_GPIO_PRT2_PC2
PGOOD_LED__0__PORT EQU 2
PGOOD_LED__0__PS EQU CYREG_GPIO_PRT2_PS
PGOOD_LED__0__SHIFT EQU 4
PGOOD_LED__DR EQU CYREG_GPIO_PRT2_DR
PGOOD_LED__DR_CLR EQU CYREG_GPIO_PRT2_DR_CLR
PGOOD_LED__DR_INV EQU CYREG_GPIO_PRT2_DR_INV
PGOOD_LED__DR_SET EQU CYREG_GPIO_PRT2_DR_SET
PGOOD_LED__INTCFG EQU CYREG_GPIO_PRT2_INTR_CFG
PGOOD_LED__INTR EQU CYREG_GPIO_PRT2_INTR
PGOOD_LED__INTR_CFG EQU CYREG_GPIO_PRT2_INTR_CFG
PGOOD_LED__INTSTAT EQU CYREG_GPIO_PRT2_INTR
PGOOD_LED__MASK EQU 0x10
PGOOD_LED__PC EQU CYREG_GPIO_PRT2_PC
PGOOD_LED__PC2 EQU CYREG_GPIO_PRT2_PC2
PGOOD_LED__PORT EQU 2
PGOOD_LED__PS EQU CYREG_GPIO_PRT2_PS
PGOOD_LED__SHIFT EQU 4

; SMBALERTB
SMBALERTB__0__DR EQU CYREG_GPIO_PRT3_DR
SMBALERTB__0__DR_CLR EQU CYREG_GPIO_PRT3_DR_CLR
SMBALERTB__0__DR_INV EQU CYREG_GPIO_PRT3_DR_INV
SMBALERTB__0__DR_SET EQU CYREG_GPIO_PRT3_DR_SET
SMBALERTB__0__HSIOM EQU CYREG_HSIOM_PORT_SEL3
SMBALERTB__0__HSIOM_MASK EQU 0x0F000000
SMBALERTB__0__HSIOM_SHIFT EQU 24
SMBALERTB__0__INTCFG EQU CYREG_GPIO_PRT3_INTR_CFG
SMBALERTB__0__INTR EQU CYREG_GPIO_PRT3_INTR
SMBALERTB__0__INTR_CFG EQU CYREG_GPIO_PRT3_INTR_CFG
SMBALERTB__0__INTSTAT EQU CYREG_GPIO_PRT3_INTR
SMBALERTB__0__MASK EQU 0x40
SMBALERTB__0__PC EQU CYREG_GPIO_PRT3_PC
SMBALERTB__0__PC2 EQU CYREG_GPIO_PRT3_PC2
SMBALERTB__0__PORT EQU 3
SMBALERTB__0__PS EQU CYREG_GPIO_PRT3_PS
SMBALERTB__0__SHIFT EQU 6
SMBALERTB__DR EQU CYREG_GPIO_PRT3_DR
SMBALERTB__DR_CLR EQU CYREG_GPIO_PRT3_DR_CLR
SMBALERTB__DR_INV EQU CYREG_GPIO_PRT3_DR_INV
SMBALERTB__DR_SET EQU CYREG_GPIO_PRT3_DR_SET
SMBALERTB__INTCFG EQU CYREG_GPIO_PRT3_INTR_CFG
SMBALERTB__INTR EQU CYREG_GPIO_PRT3_INTR
SMBALERTB__INTR_CFG EQU CYREG_GPIO_PRT3_INTR_CFG
SMBALERTB__INTSTAT EQU CYREG_GPIO_PRT3_INTR
SMBALERTB__MASK EQU 0x40
SMBALERTB__PC EQU CYREG_GPIO_PRT3_PC
SMBALERTB__PC2 EQU CYREG_GPIO_PRT3_PC2
SMBALERTB__PORT EQU 3
SMBALERTB__PS EQU CYREG_GPIO_PRT3_PS
SMBALERTB__SHIFT EQU 6

; I2C_master_SCB
I2C_master_SCB__CMD_RESP_CTRL EQU CYREG_SCB2_CMD_RESP_CTRL
I2C_master_SCB__CMD_RESP_STATUS EQU CYREG_SCB2_CMD_RESP_STATUS
I2C_master_SCB__CTRL EQU CYREG_SCB2_CTRL
I2C_master_SCB__EZ_DATA0 EQU CYREG_SCB2_EZ_DATA0
I2C_master_SCB__EZ_DATA1 EQU CYREG_SCB2_EZ_DATA1
I2C_master_SCB__EZ_DATA10 EQU CYREG_SCB2_EZ_DATA10
I2C_master_SCB__EZ_DATA100 EQU CYREG_SCB2_EZ_DATA100
I2C_master_SCB__EZ_DATA101 EQU CYREG_SCB2_EZ_DATA101
I2C_master_SCB__EZ_DATA102 EQU CYREG_SCB2_EZ_DATA102
I2C_master_SCB__EZ_DATA103 EQU CYREG_SCB2_EZ_DATA103
I2C_master_SCB__EZ_DATA104 EQU CYREG_SCB2_EZ_DATA104
I2C_master_SCB__EZ_DATA105 EQU CYREG_SCB2_EZ_DATA105
I2C_master_SCB__EZ_DATA106 EQU CYREG_SCB2_EZ_DATA106
I2C_master_SCB__EZ_DATA107 EQU CYREG_SCB2_EZ_DATA107
I2C_master_SCB__EZ_DATA108 EQU CYREG_SCB2_EZ_DATA108
I2C_master_SCB__EZ_DATA109 EQU CYREG_SCB2_EZ_DATA109
I2C_master_SCB__EZ_DATA11 EQU CYREG_SCB2_EZ_DATA11
I2C_master_SCB__EZ_DATA110 EQU CYREG_SCB2_EZ_DATA110
I2C_master_SCB__EZ_DATA111 EQU CYREG_SCB2_EZ_DATA111
I2C_master_SCB__EZ_DATA112 EQU CYREG_SCB2_EZ_DATA112
I2C_master_SCB__EZ_DATA113 EQU CYREG_SCB2_EZ_DATA113
I2C_master_SCB__EZ_DATA114 EQU CYREG_SCB2_EZ_DATA114
I2C_master_SCB__EZ_DATA115 EQU CYREG_SCB2_EZ_DATA115
I2C_master_SCB__EZ_DATA116 EQU CYREG_SCB2_EZ_DATA116
I2C_master_SCB__EZ_DATA117 EQU CYREG_SCB2_EZ_DATA117
I2C_master_SCB__EZ_DATA118 EQU CYREG_SCB2_EZ_DATA118
I2C_master_SCB__EZ_DATA119 EQU CYREG_SCB2_EZ_DATA119
I2C_master_SCB__EZ_DATA12 EQU CYREG_SCB2_EZ_DATA12
I2C_master_SCB__EZ_DATA120 EQU CYREG_SCB2_EZ_DATA120
I2C_master_SCB__EZ_DATA121 EQU CYREG_SCB2_EZ_DATA121
I2C_master_SCB__EZ_DATA122 EQU CYREG_SCB2_EZ_DATA122
I2C_master_SCB__EZ_DATA123 EQU CYREG_SCB2_EZ_DATA123
I2C_master_SCB__EZ_DATA124 EQU CYREG_SCB2_EZ_DATA124
I2C_master_SCB__EZ_DATA125 EQU CYREG_SCB2_EZ_DATA125
I2C_master_SCB__EZ_DATA126 EQU CYREG_SCB2_EZ_DATA126
I2C_master_SCB__EZ_DATA127 EQU CYREG_SCB2_EZ_DATA127
I2C_master_SCB__EZ_DATA128 EQU CYREG_SCB2_EZ_DATA128
I2C_master_SCB__EZ_DATA129 EQU CYREG_SCB2_EZ_DATA129
I2C_master_SCB__EZ_DATA13 EQU CYREG_SCB2_EZ_DATA13
I2C_master_SCB__EZ_DATA130 EQU CYREG_SCB2_EZ_DATA130
I2C_master_SCB__EZ_DATA131 EQU CYREG_SCB2_EZ_DATA131
I2C_master_SCB__EZ_DATA132 EQU CYREG_SCB2_EZ_DATA132
I2C_master_SCB__EZ_DATA133 EQU CYREG_SCB2_EZ_DATA133
I2C_master_SCB__EZ_DATA134 EQU CYREG_SCB2_EZ_DATA134
I2C_master_SCB__EZ_DATA135 EQU CYREG_SCB2_EZ_DATA135
I2C_master_SCB__EZ_DATA136 EQU CYREG_SCB2_EZ_DATA136
I2C_master_SCB__EZ_DATA137 EQU CYREG_SCB2_EZ_DATA137
I2C_master_SCB__EZ_DATA138 EQU CYREG_SCB2_EZ_DATA138
I2C_master_SCB__EZ_DATA139 EQU CYREG_SCB2_EZ_DATA139
I2C_master_SCB__EZ_DATA14 EQU CYREG_SCB2_EZ_DATA14
I2C_master_SCB__EZ_DATA140 EQU CYREG_SCB2_EZ_DATA140
I2C_master_SCB__EZ_DATA141 EQU CYREG_SCB2_EZ_DATA141
I2C_master_SCB__EZ_DATA142 EQU CYREG_SCB2_EZ_DATA142
I2C_master_SCB__EZ_DATA143 EQU CYREG_SCB2_EZ_DATA143
I2C_master_SCB__EZ_DATA144 EQU CYREG_SCB2_EZ_DATA144
I2C_master_SCB__EZ_DATA145 EQU CYREG_SCB2_EZ_DATA145
I2C_master_SCB__EZ_DATA146 EQU CYREG_SCB2_EZ_DATA146
I2C_master_SCB__EZ_DATA147 EQU CYREG_SCB2_EZ_DATA147
I2C_master_SCB__EZ_DATA148 EQU CYREG_SCB2_EZ_DATA148
I2C_master_SCB__EZ_DATA149 EQU CYREG_SCB2_EZ_DATA149
I2C_master_SCB__EZ_DATA15 EQU CYREG_SCB2_EZ_DATA15
I2C_master_SCB__EZ_DATA150 EQU CYREG_SCB2_EZ_DATA150
I2C_master_SCB__EZ_DATA151 EQU CYREG_SCB2_EZ_DATA151
I2C_master_SCB__EZ_DATA152 EQU CYREG_SCB2_EZ_DATA152
I2C_master_SCB__EZ_DATA153 EQU CYREG_SCB2_EZ_DATA153
I2C_master_SCB__EZ_DATA154 EQU CYREG_SCB2_EZ_DATA154
I2C_master_SCB__EZ_DATA155 EQU CYREG_SCB2_EZ_DATA155
I2C_master_SCB__EZ_DATA156 EQU CYREG_SCB2_EZ_DATA156
I2C_master_SCB__EZ_DATA157 EQU CYREG_SCB2_EZ_DATA157
I2C_master_SCB__EZ_DATA158 EQU CYREG_SCB2_EZ_DATA158
I2C_master_SCB__EZ_DATA159 EQU CYREG_SCB2_EZ_DATA159
I2C_master_SCB__EZ_DATA16 EQU CYREG_SCB2_EZ_DATA16
I2C_master_SCB__EZ_DATA160 EQU CYREG_SCB2_EZ_DATA160
I2C_master_SCB__EZ_DATA161 EQU CYREG_SCB2_EZ_DATA161
I2C_master_SCB__EZ_DATA162 EQU CYREG_SCB2_EZ_DATA162
I2C_master_SCB__EZ_DATA163 EQU CYREG_SCB2_EZ_DATA163
I2C_master_SCB__EZ_DATA164 EQU CYREG_SCB2_EZ_DATA164
I2C_master_SCB__EZ_DATA165 EQU CYREG_SCB2_EZ_DATA165
I2C_master_SCB__EZ_DATA166 EQU CYREG_SCB2_EZ_DATA166
I2C_master_SCB__EZ_DATA167 EQU CYREG_SCB2_EZ_DATA167
I2C_master_SCB__EZ_DATA168 EQU CYREG_SCB2_EZ_DATA168
I2C_master_SCB__EZ_DATA169 EQU CYREG_SCB2_EZ_DATA169
I2C_master_SCB__EZ_DATA17 EQU CYREG_SCB2_EZ_DATA17
I2C_master_SCB__EZ_DATA170 EQU CYREG_SCB2_EZ_DATA170
I2C_master_SCB__EZ_DATA171 EQU CYREG_SCB2_EZ_DATA171
I2C_master_SCB__EZ_DATA172 EQU CYREG_SCB2_EZ_DATA172
I2C_master_SCB__EZ_DATA173 EQU CYREG_SCB2_EZ_DATA173
I2C_master_SCB__EZ_DATA174 EQU CYREG_SCB2_EZ_DATA174
I2C_master_SCB__EZ_DATA175 EQU CYREG_SCB2_EZ_DATA175
I2C_master_SCB__EZ_DATA176 EQU CYREG_SCB2_EZ_DATA176
I2C_master_SCB__EZ_DATA177 EQU CYREG_SCB2_EZ_DATA177
I2C_master_SCB__EZ_DATA178 EQU CYREG_SCB2_EZ_DATA178
I2C_master_SCB__EZ_DATA179 EQU CYREG_SCB2_EZ_DATA179
I2C_master_SCB__EZ_DATA18 EQU CYREG_SCB2_EZ_DATA18
I2C_master_SCB__EZ_DATA180 EQU CYREG_SCB2_EZ_DATA180
I2C_master_SCB__EZ_DATA181 EQU CYREG_SCB2_EZ_DATA181
I2C_master_SCB__EZ_DATA182 EQU CYREG_SCB2_EZ_DATA182
I2C_master_SCB__EZ_DATA183 EQU CYREG_SCB2_EZ_DATA183
I2C_master_SCB__EZ_DATA184 EQU CYREG_SCB2_EZ_DATA184
I2C_master_SCB__EZ_DATA185 EQU CYREG_SCB2_EZ_DATA185
I2C_master_SCB__EZ_DATA186 EQU CYREG_SCB2_EZ_DATA186
I2C_master_SCB__EZ_DATA187 EQU CYREG_SCB2_EZ_DATA187
I2C_master_SCB__EZ_DATA188 EQU CYREG_SCB2_EZ_DATA188
I2C_master_SCB__EZ_DATA189 EQU CYREG_SCB2_EZ_DATA189
I2C_master_SCB__EZ_DATA19 EQU CYREG_SCB2_EZ_DATA19
I2C_master_SCB__EZ_DATA190 EQU CYREG_SCB2_EZ_DATA190
I2C_master_SCB__EZ_DATA191 EQU CYREG_SCB2_EZ_DATA191
I2C_master_SCB__EZ_DATA192 EQU CYREG_SCB2_EZ_DATA192
I2C_master_SCB__EZ_DATA193 EQU CYREG_SCB2_EZ_DATA193
I2C_master_SCB__EZ_DATA194 EQU CYREG_SCB2_EZ_DATA194
I2C_master_SCB__EZ_DATA195 EQU CYREG_SCB2_EZ_DATA195
I2C_master_SCB__EZ_DATA196 EQU CYREG_SCB2_EZ_DATA196
I2C_master_SCB__EZ_DATA197 EQU CYREG_SCB2_EZ_DATA197
I2C_master_SCB__EZ_DATA198 EQU CYREG_SCB2_EZ_DATA198
I2C_master_SCB__EZ_DATA199 EQU CYREG_SCB2_EZ_DATA199
I2C_master_SCB__EZ_DATA2 EQU CYREG_SCB2_EZ_DATA2
I2C_master_SCB__EZ_DATA20 EQU CYREG_SCB2_EZ_DATA20
I2C_master_SCB__EZ_DATA200 EQU CYREG_SCB2_EZ_DATA200
I2C_master_SCB__EZ_DATA201 EQU CYREG_SCB2_EZ_DATA201
I2C_master_SCB__EZ_DATA202 EQU CYREG_SCB2_EZ_DATA202
I2C_master_SCB__EZ_DATA203 EQU CYREG_SCB2_EZ_DATA203
I2C_master_SCB__EZ_DATA204 EQU CYREG_SCB2_EZ_DATA204
I2C_master_SCB__EZ_DATA205 EQU CYREG_SCB2_EZ_DATA205
I2C_master_SCB__EZ_DATA206 EQU CYREG_SCB2_EZ_DATA206
I2C_master_SCB__EZ_DATA207 EQU CYREG_SCB2_EZ_DATA207
I2C_master_SCB__EZ_DATA208 EQU CYREG_SCB2_EZ_DATA208
I2C_master_SCB__EZ_DATA209 EQU CYREG_SCB2_EZ_DATA209
I2C_master_SCB__EZ_DATA21 EQU CYREG_SCB2_EZ_DATA21
I2C_master_SCB__EZ_DATA210 EQU CYREG_SCB2_EZ_DATA210
I2C_master_SCB__EZ_DATA211 EQU CYREG_SCB2_EZ_DATA211
I2C_master_SCB__EZ_DATA212 EQU CYREG_SCB2_EZ_DATA212
I2C_master_SCB__EZ_DATA213 EQU CYREG_SCB2_EZ_DATA213
I2C_master_SCB__EZ_DATA214 EQU CYREG_SCB2_EZ_DATA214
I2C_master_SCB__EZ_DATA215 EQU CYREG_SCB2_EZ_DATA215
I2C_master_SCB__EZ_DATA216 EQU CYREG_SCB2_EZ_DATA216
I2C_master_SCB__EZ_DATA217 EQU CYREG_SCB2_EZ_DATA217
I2C_master_SCB__EZ_DATA218 EQU CYREG_SCB2_EZ_DATA218
I2C_master_SCB__EZ_DATA219 EQU CYREG_SCB2_EZ_DATA219
I2C_master_SCB__EZ_DATA22 EQU CYREG_SCB2_EZ_DATA22
I2C_master_SCB__EZ_DATA220 EQU CYREG_SCB2_EZ_DATA220
I2C_master_SCB__EZ_DATA221 EQU CYREG_SCB2_EZ_DATA221
I2C_master_SCB__EZ_DATA222 EQU CYREG_SCB2_EZ_DATA222
I2C_master_SCB__EZ_DATA223 EQU CYREG_SCB2_EZ_DATA223
I2C_master_SCB__EZ_DATA224 EQU CYREG_SCB2_EZ_DATA224
I2C_master_SCB__EZ_DATA225 EQU CYREG_SCB2_EZ_DATA225
I2C_master_SCB__EZ_DATA226 EQU CYREG_SCB2_EZ_DATA226
I2C_master_SCB__EZ_DATA227 EQU CYREG_SCB2_EZ_DATA227
I2C_master_SCB__EZ_DATA228 EQU CYREG_SCB2_EZ_DATA228
I2C_master_SCB__EZ_DATA229 EQU CYREG_SCB2_EZ_DATA229
I2C_master_SCB__EZ_DATA23 EQU CYREG_SCB2_EZ_DATA23
I2C_master_SCB__EZ_DATA230 EQU CYREG_SCB2_EZ_DATA230
I2C_master_SCB__EZ_DATA231 EQU CYREG_SCB2_EZ_DATA231
I2C_master_SCB__EZ_DATA232 EQU CYREG_SCB2_EZ_DATA232
I2C_master_SCB__EZ_DATA233 EQU CYREG_SCB2_EZ_DATA233
I2C_master_SCB__EZ_DATA234 EQU CYREG_SCB2_EZ_DATA234
I2C_master_SCB__EZ_DATA235 EQU CYREG_SCB2_EZ_DATA235
I2C_master_SCB__EZ_DATA236 EQU CYREG_SCB2_EZ_DATA236
I2C_master_SCB__EZ_DATA237 EQU CYREG_SCB2_EZ_DATA237
I2C_master_SCB__EZ_DATA238 EQU CYREG_SCB2_EZ_DATA238
I2C_master_SCB__EZ_DATA239 EQU CYREG_SCB2_EZ_DATA239
I2C_master_SCB__EZ_DATA24 EQU CYREG_SCB2_EZ_DATA24
I2C_master_SCB__EZ_DATA240 EQU CYREG_SCB2_EZ_DATA240
I2C_master_SCB__EZ_DATA241 EQU CYREG_SCB2_EZ_DATA241
I2C_master_SCB__EZ_DATA242 EQU CYREG_SCB2_EZ_DATA242
I2C_master_SCB__EZ_DATA243 EQU CYREG_SCB2_EZ_DATA243
I2C_master_SCB__EZ_DATA244 EQU CYREG_SCB2_EZ_DATA244
I2C_master_SCB__EZ_DATA245 EQU CYREG_SCB2_EZ_DATA245
I2C_master_SCB__EZ_DATA246 EQU CYREG_SCB2_EZ_DATA246
I2C_master_SCB__EZ_DATA247 EQU CYREG_SCB2_EZ_DATA247
I2C_master_SCB__EZ_DATA248 EQU CYREG_SCB2_EZ_DATA248
I2C_master_SCB__EZ_DATA249 EQU CYREG_SCB2_EZ_DATA249
I2C_master_SCB__EZ_DATA25 EQU CYREG_SCB2_EZ_DATA25
I2C_master_SCB__EZ_DATA250 EQU CYREG_SCB2_EZ_DATA250
I2C_master_SCB__EZ_DATA251 EQU CYREG_SCB2_EZ_DATA251
I2C_master_SCB__EZ_DATA252 EQU CYREG_SCB2_EZ_DATA252
I2C_master_SCB__EZ_DATA253 EQU CYREG_SCB2_EZ_DATA253
I2C_master_SCB__EZ_DATA254 EQU CYREG_SCB2_EZ_DATA254
I2C_master_SCB__EZ_DATA255 EQU CYREG_SCB2_EZ_DATA255
I2C_master_SCB__EZ_DATA26 EQU CYREG_SCB2_EZ_DATA26
I2C_master_SCB__EZ_DATA27 EQU CYREG_SCB2_EZ_DATA27
I2C_master_SCB__EZ_DATA28 EQU CYREG_SCB2_EZ_DATA28
I2C_master_SCB__EZ_DATA29 EQU CYREG_SCB2_EZ_DATA29
I2C_master_SCB__EZ_DATA3 EQU CYREG_SCB2_EZ_DATA3
I2C_master_SCB__EZ_DATA30 EQU CYREG_SCB2_EZ_DATA30
I2C_master_SCB__EZ_DATA31 EQU CYREG_SCB2_EZ_DATA31
I2C_master_SCB__EZ_DATA32 EQU CYREG_SCB2_EZ_DATA32
I2C_master_SCB__EZ_DATA33 EQU CYREG_SCB2_EZ_DATA33
I2C_master_SCB__EZ_DATA34 EQU CYREG_SCB2_EZ_DATA34
I2C_master_SCB__EZ_DATA35 EQU CYREG_SCB2_EZ_DATA35
I2C_master_SCB__EZ_DATA36 EQU CYREG_SCB2_EZ_DATA36
I2C_master_SCB__EZ_DATA37 EQU CYREG_SCB2_EZ_DATA37
I2C_master_SCB__EZ_DATA38 EQU CYREG_SCB2_EZ_DATA38
I2C_master_SCB__EZ_DATA39 EQU CYREG_SCB2_EZ_DATA39
I2C_master_SCB__EZ_DATA4 EQU CYREG_SCB2_EZ_DATA4
I2C_master_SCB__EZ_DATA40 EQU CYREG_SCB2_EZ_DATA40
I2C_master_SCB__EZ_DATA41 EQU CYREG_SCB2_EZ_DATA41
I2C_master_SCB__EZ_DATA42 EQU CYREG_SCB2_EZ_DATA42
I2C_master_SCB__EZ_DATA43 EQU CYREG_SCB2_EZ_DATA43
I2C_master_SCB__EZ_DATA44 EQU CYREG_SCB2_EZ_DATA44
I2C_master_SCB__EZ_DATA45 EQU CYREG_SCB2_EZ_DATA45
I2C_master_SCB__EZ_DATA46 EQU CYREG_SCB2_EZ_DATA46
I2C_master_SCB__EZ_DATA47 EQU CYREG_SCB2_EZ_DATA47
I2C_master_SCB__EZ_DATA48 EQU CYREG_SCB2_EZ_DATA48
I2C_master_SCB__EZ_DATA49 EQU CYREG_SCB2_EZ_DATA49
I2C_master_SCB__EZ_DATA5 EQU CYREG_SCB2_EZ_DATA5
I2C_master_SCB__EZ_DATA50 EQU CYREG_SCB2_EZ_DATA50
I2C_master_SCB__EZ_DATA51 EQU CYREG_SCB2_EZ_DATA51
I2C_master_SCB__EZ_DATA52 EQU CYREG_SCB2_EZ_DATA52
I2C_master_SCB__EZ_DATA53 EQU CYREG_SCB2_EZ_DATA53
I2C_master_SCB__EZ_DATA54 EQU CYREG_SCB2_EZ_DATA54
I2C_master_SCB__EZ_DATA55 EQU CYREG_SCB2_EZ_DATA55
I2C_master_SCB__EZ_DATA56 EQU CYREG_SCB2_EZ_DATA56
I2C_master_SCB__EZ_DATA57 EQU CYREG_SCB2_EZ_DATA57
I2C_master_SCB__EZ_DATA58 EQU CYREG_SCB2_EZ_DATA58
I2C_master_SCB__EZ_DATA59 EQU CYREG_SCB2_EZ_DATA59
I2C_master_SCB__EZ_DATA6 EQU CYREG_SCB2_EZ_DATA6
I2C_master_SCB__EZ_DATA60 EQU CYREG_SCB2_EZ_DATA60
I2C_master_SCB__EZ_DATA61 EQU CYREG_SCB2_EZ_DATA61
I2C_master_SCB__EZ_DATA62 EQU CYREG_SCB2_EZ_DATA62
I2C_master_SCB__EZ_DATA63 EQU CYREG_SCB2_EZ_DATA63
I2C_master_SCB__EZ_DATA64 EQU CYREG_SCB2_EZ_DATA64
I2C_master_SCB__EZ_DATA65 EQU CYREG_SCB2_EZ_DATA65
I2C_master_SCB__EZ_DATA66 EQU CYREG_SCB2_EZ_DATA66
I2C_master_SCB__EZ_DATA67 EQU CYREG_SCB2_EZ_DATA67
I2C_master_SCB__EZ_DATA68 EQU CYREG_SCB2_EZ_DATA68
I2C_master_SCB__EZ_DATA69 EQU CYREG_SCB2_EZ_DATA69
I2C_master_SCB__EZ_DATA7 EQU CYREG_SCB2_EZ_DATA7
I2C_master_SCB__EZ_DATA70 EQU CYREG_SCB2_EZ_DATA70
I2C_master_SCB__EZ_DATA71 EQU CYREG_SCB2_EZ_DATA71
I2C_master_SCB__EZ_DATA72 EQU CYREG_SCB2_EZ_DATA72
I2C_master_SCB__EZ_DATA73 EQU CYREG_SCB2_EZ_DATA73
I2C_master_SCB__EZ_DATA74 EQU CYREG_SCB2_EZ_DATA74
I2C_master_SCB__EZ_DATA75 EQU CYREG_SCB2_EZ_DATA75
I2C_master_SCB__EZ_DATA76 EQU CYREG_SCB2_EZ_DATA76
I2C_master_SCB__EZ_DATA77 EQU CYREG_SCB2_EZ_DATA77
I2C_master_SCB__EZ_DATA78 EQU CYREG_SCB2_EZ_DATA78
I2C_master_SCB__EZ_DATA79 EQU CYREG_SCB2_EZ_DATA79
I2C_master_SCB__EZ_DATA8 EQU CYREG_SCB2_EZ_DATA8
I2C_master_SCB__EZ_DATA80 EQU CYREG_SCB2_EZ_DATA80
I2C_master_SCB__EZ_DATA81 EQU CYREG_SCB2_EZ_DATA81
I2C_master_SCB__EZ_DATA82 EQU CYREG_SCB2_EZ_DATA82
I2C_master_SCB__EZ_DATA83 EQU CYREG_SCB2_EZ_DATA83
I2C_master_SCB__EZ_DATA84 EQU CYREG_SCB2_EZ_DATA84
I2C_master_SCB__EZ_DATA85 EQU CYREG_SCB2_EZ_DATA85
I2C_master_SCB__EZ_DATA86 EQU CYREG_SCB2_EZ_DATA86
I2C_master_SCB__EZ_DATA87 EQU CYREG_SCB2_EZ_DATA87
I2C_master_SCB__EZ_DATA88 EQU CYREG_SCB2_EZ_DATA88
I2C_master_SCB__EZ_DATA89 EQU CYREG_SCB2_EZ_DATA89
I2C_master_SCB__EZ_DATA9 EQU CYREG_SCB2_EZ_DATA9
I2C_master_SCB__EZ_DATA90 EQU CYREG_SCB2_EZ_DATA90
I2C_master_SCB__EZ_DATA91 EQU CYREG_SCB2_EZ_DATA91
I2C_master_SCB__EZ_DATA92 EQU CYREG_SCB2_EZ_DATA92
I2C_master_SCB__EZ_DATA93 EQU CYREG_SCB2_EZ_DATA93
I2C_master_SCB__EZ_DATA94 EQU CYREG_SCB2_EZ_DATA94
I2C_master_SCB__EZ_DATA95 EQU CYREG_SCB2_EZ_DATA95
I2C_master_SCB__EZ_DATA96 EQU CYREG_SCB2_EZ_DATA96
I2C_master_SCB__EZ_DATA97 EQU CYREG_SCB2_EZ_DATA97
I2C_master_SCB__EZ_DATA98 EQU CYREG_SCB2_EZ_DATA98
I2C_master_SCB__EZ_DATA99 EQU CYREG_SCB2_EZ_DATA99
I2C_master_SCB__I2C_CFG EQU CYREG_SCB2_I2C_CFG
I2C_master_SCB__I2C_CTRL EQU CYREG_SCB2_I2C_CTRL
I2C_master_SCB__I2C_M_CMD EQU CYREG_SCB2_I2C_M_CMD
I2C_master_SCB__I2C_S_CMD EQU CYREG_SCB2_I2C_S_CMD
I2C_master_SCB__I2C_STATUS EQU CYREG_SCB2_I2C_STATUS
I2C_master_SCB__INTR_CAUSE EQU CYREG_SCB2_INTR_CAUSE
I2C_master_SCB__INTR_I2C_EC EQU CYREG_SCB2_INTR_I2C_EC
I2C_master_SCB__INTR_I2C_EC_MASK EQU CYREG_SCB2_INTR_I2C_EC_MASK
I2C_master_SCB__INTR_I2C_EC_MASKED EQU CYREG_SCB2_INTR_I2C_EC_MASKED
I2C_master_SCB__INTR_M EQU CYREG_SCB2_INTR_M
I2C_master_SCB__INTR_M_MASK EQU CYREG_SCB2_INTR_M_MASK
I2C_master_SCB__INTR_M_MASKED EQU CYREG_SCB2_INTR_M_MASKED
I2C_master_SCB__INTR_M_SET EQU CYREG_SCB2_INTR_M_SET
I2C_master_SCB__INTR_RX EQU CYREG_SCB2_INTR_RX
I2C_master_SCB__INTR_RX_MASK EQU CYREG_SCB2_INTR_RX_MASK
I2C_master_SCB__INTR_RX_MASKED EQU CYREG_SCB2_INTR_RX_MASKED
I2C_master_SCB__INTR_RX_SET EQU CYREG_SCB2_INTR_RX_SET
I2C_master_SCB__INTR_S EQU CYREG_SCB2_INTR_S
I2C_master_SCB__INTR_S_MASK EQU CYREG_SCB2_INTR_S_MASK
I2C_master_SCB__INTR_S_MASKED EQU CYREG_SCB2_INTR_S_MASKED
I2C_master_SCB__INTR_S_SET EQU CYREG_SCB2_INTR_S_SET
I2C_master_SCB__INTR_SPI_EC EQU CYREG_SCB2_INTR_SPI_EC
I2C_master_SCB__INTR_SPI_EC_MASK EQU CYREG_SCB2_INTR_SPI_EC_MASK
I2C_master_SCB__INTR_SPI_EC_MASKED EQU CYREG_SCB2_INTR_SPI_EC_MASKED
I2C_master_SCB__INTR_TX EQU CYREG_SCB2_INTR_TX
I2C_master_SCB__INTR_TX_MASK EQU CYREG_SCB2_INTR_TX_MASK
I2C_master_SCB__INTR_TX_MASKED EQU CYREG_SCB2_INTR_TX_MASKED
I2C_master_SCB__INTR_TX_SET EQU CYREG_SCB2_INTR_TX_SET
I2C_master_SCB__RX_CTRL EQU CYREG_SCB2_RX_CTRL
I2C_master_SCB__RX_FIFO_CTRL EQU CYREG_SCB2_RX_FIFO_CTRL
I2C_master_SCB__RX_FIFO_RD EQU CYREG_SCB2_RX_FIFO_RD
I2C_master_SCB__RX_FIFO_RD_SILENT EQU CYREG_SCB2_RX_FIFO_RD_SILENT
I2C_master_SCB__RX_FIFO_STATUS EQU CYREG_SCB2_RX_FIFO_STATUS
I2C_master_SCB__RX_MATCH EQU CYREG_SCB2_RX_MATCH
I2C_master_SCB__SPI_CTRL EQU CYREG_SCB2_SPI_CTRL
I2C_master_SCB__SPI_STATUS EQU CYREG_SCB2_SPI_STATUS
I2C_master_SCB__SS0_POSISTION EQU 0
I2C_master_SCB__SS1_POSISTION EQU 1
I2C_master_SCB__SS2_POSISTION EQU 2
I2C_master_SCB__SS3_POSISTION EQU 3
I2C_master_SCB__STATUS EQU CYREG_SCB2_STATUS
I2C_master_SCB__TX_CTRL EQU CYREG_SCB2_TX_CTRL
I2C_master_SCB__TX_FIFO_CTRL EQU CYREG_SCB2_TX_FIFO_CTRL
I2C_master_SCB__TX_FIFO_STATUS EQU CYREG_SCB2_TX_FIFO_STATUS
I2C_master_SCB__TX_FIFO_WR EQU CYREG_SCB2_TX_FIFO_WR
I2C_master_SCB__UART_CTRL EQU CYREG_SCB2_UART_CTRL
I2C_master_SCB__UART_FLOW_CTRL EQU CYREG_SCB2_UART_FLOW_CTRL
I2C_master_SCB__UART_RX_CTRL EQU CYREG_SCB2_UART_RX_CTRL
I2C_master_SCB__UART_RX_STATUS EQU CYREG_SCB2_UART_RX_STATUS
I2C_master_SCB__UART_TX_CTRL EQU CYREG_SCB2_UART_TX_CTRL

; I2C_master_SCB_IRQ
I2C_master_SCB_IRQ__INTC_CLR_EN_REG EQU CYREG_CM0_ICER
I2C_master_SCB_IRQ__INTC_CLR_PD_REG EQU CYREG_CM0_ICPR
I2C_master_SCB_IRQ__INTC_MASK EQU 0x400
I2C_master_SCB_IRQ__INTC_NUMBER EQU 10
I2C_master_SCB_IRQ__INTC_PRIOR_MASK EQU 0xC00000
I2C_master_SCB_IRQ__INTC_PRIOR_NUM EQU 3
I2C_master_SCB_IRQ__INTC_PRIOR_REG EQU CYREG_CM0_IPR2
I2C_master_SCB_IRQ__INTC_SET_EN_REG EQU CYREG_CM0_ISER
I2C_master_SCB_IRQ__INTC_SET_PD_REG EQU CYREG_CM0_ISPR

; I2C_master_SCBCLK
I2C_master_SCBCLK__CTRL_REGISTER EQU CYREG_PERI_PCLK_CTL2
I2C_master_SCBCLK__DIV_ID EQU 0x00000001
I2C_master_SCBCLK__DIV_REGISTER EQU CYREG_PERI_DIV_8_CTL1
I2C_master_SCBCLK__PA_DIV_ID EQU 0x000000FF

; I2C_master_scl
I2C_master_scl__0__DR EQU CYREG_GPIO_PRT3_DR
I2C_master_scl__0__DR_CLR EQU CYREG_GPIO_PRT3_DR_CLR
I2C_master_scl__0__DR_INV EQU CYREG_GPIO_PRT3_DR_INV
I2C_master_scl__0__DR_SET EQU CYREG_GPIO_PRT3_DR_SET
I2C_master_scl__0__HSIOM EQU CYREG_HSIOM_PORT_SEL3
I2C_master_scl__0__HSIOM_GPIO EQU 0
I2C_master_scl__0__HSIOM_I2C EQU 15
I2C_master_scl__0__HSIOM_I2C_SCL EQU 15
I2C_master_scl__0__HSIOM_MASK EQU 0x00F00000
I2C_master_scl__0__HSIOM_SHIFT EQU 20
I2C_master_scl__0__HSIOM_SPI EQU 14
I2C_master_scl__0__HSIOM_SPI_CLK EQU 14
I2C_master_scl__0__HSIOM_UART EQU 10
I2C_master_scl__0__HSIOM_UART_RTS EQU 10
I2C_master_scl__0__INTCFG EQU CYREG_GPIO_PRT3_INTR_CFG
I2C_master_scl__0__INTR EQU CYREG_GPIO_PRT3_INTR
I2C_master_scl__0__INTR_CFG EQU CYREG_GPIO_PRT3_INTR_CFG
I2C_master_scl__0__INTSTAT EQU CYREG_GPIO_PRT3_INTR
I2C_master_scl__0__MASK EQU 0x20
I2C_master_scl__0__PC EQU CYREG_GPIO_PRT3_PC
I2C_master_scl__0__PC2 EQU CYREG_GPIO_PRT3_PC2
I2C_master_scl__0__PORT EQU 3
I2C_master_scl__0__PS EQU CYREG_GPIO_PRT3_PS
I2C_master_scl__0__SHIFT EQU 5
I2C_master_scl__DR EQU CYREG_GPIO_PRT3_DR
I2C_master_scl__DR_CLR EQU CYREG_GPIO_PRT3_DR_CLR
I2C_master_scl__DR_INV EQU CYREG_GPIO_PRT3_DR_INV
I2C_master_scl__DR_SET EQU CYREG_GPIO_PRT3_DR_SET
I2C_master_scl__INTCFG EQU CYREG_GPIO_PRT3_INTR_CFG
I2C_master_scl__INTR EQU CYREG_GPIO_PRT3_INTR
I2C_master_scl__INTR_CFG EQU CYREG_GPIO_PRT3_INTR_CFG
I2C_master_scl__INTSTAT EQU CYREG_GPIO_PRT3_INTR
I2C_master_scl__MASK EQU 0x20
I2C_master_scl__PC EQU CYREG_GPIO_PRT3_PC
I2C_master_scl__PC2 EQU CYREG_GPIO_PRT3_PC2
I2C_master_scl__PORT EQU 3
I2C_master_scl__PS EQU CYREG_GPIO_PRT3_PS
I2C_master_scl__SHIFT EQU 5

; I2C_master_sda
I2C_master_sda__0__DR EQU CYREG_GPIO_PRT3_DR
I2C_master_sda__0__DR_CLR EQU CYREG_GPIO_PRT3_DR_CLR
I2C_master_sda__0__DR_INV EQU CYREG_GPIO_PRT3_DR_INV
I2C_master_sda__0__DR_SET EQU CYREG_GPIO_PRT3_DR_SET
I2C_master_sda__0__HSIOM EQU CYREG_HSIOM_PORT_SEL3
I2C_master_sda__0__HSIOM_GPIO EQU 0
I2C_master_sda__0__HSIOM_I2C EQU 15
I2C_master_sda__0__HSIOM_I2C_SDA EQU 15
I2C_master_sda__0__HSIOM_MASK EQU 0x000F0000
I2C_master_sda__0__HSIOM_SHIFT EQU 16
I2C_master_sda__0__HSIOM_SPI EQU 14
I2C_master_sda__0__HSIOM_SPI_MOSI EQU 14
I2C_master_sda__0__HSIOM_UART EQU 10
I2C_master_sda__0__HSIOM_UART_CTS EQU 10
I2C_master_sda__0__INTCFG EQU CYREG_GPIO_PRT3_INTR_CFG
I2C_master_sda__0__INTR EQU CYREG_GPIO_PRT3_INTR
I2C_master_sda__0__INTR_CFG EQU CYREG_GPIO_PRT3_INTR_CFG
I2C_master_sda__0__INTSTAT EQU CYREG_GPIO_PRT3_INTR
I2C_master_sda__0__MASK EQU 0x10
I2C_master_sda__0__PC EQU CYREG_GPIO_PRT3_PC
I2C_master_sda__0__PC2 EQU CYREG_GPIO_PRT3_PC2
I2C_master_sda__0__PORT EQU 3
I2C_master_sda__0__PS EQU CYREG_GPIO_PRT3_PS
I2C_master_sda__0__SHIFT EQU 4
I2C_master_sda__DR EQU CYREG_GPIO_PRT3_DR
I2C_master_sda__DR_CLR EQU CYREG_GPIO_PRT3_DR_CLR
I2C_master_sda__DR_INV EQU CYREG_GPIO_PRT3_DR_INV
I2C_master_sda__DR_SET EQU CYREG_GPIO_PRT3_DR_SET
I2C_master_sda__INTCFG EQU CYREG_GPIO_PRT3_INTR_CFG
I2C_master_sda__INTR EQU CYREG_GPIO_PRT3_INTR
I2C_master_sda__INTR_CFG EQU CYREG_GPIO_PRT3_INTR_CFG
I2C_master_sda__INTSTAT EQU CYREG_GPIO_PRT3_INTR
I2C_master_sda__MASK EQU 0x10
I2C_master_sda__PC EQU CYREG_GPIO_PRT3_PC
I2C_master_sda__PC2 EQU CYREG_GPIO_PRT3_PC2
I2C_master_sda__PORT EQU 3
I2C_master_sda__PS EQU CYREG_GPIO_PRT3_PS
I2C_master_sda__SHIFT EQU 4

; PDSS_PORT0_RX_CLK
PDSS_PORT0_RX_CLK__DIV_ID EQU 0x00000000
PDSS_PORT0_RX_CLK__DIV_REGISTER EQU CYREG_PERI_DIV_8_CTL0
PDSS_PORT0_RX_CLK__PA_DIV_ID EQU 0x000000FF

; PDSS_PORT0_TX_CLK
PDSS_PORT0_TX_CLK__DIV_ID EQU 0x00000041
PDSS_PORT0_TX_CLK__DIV_REGISTER EQU CYREG_PERI_DIV_16_CTL1
PDSS_PORT0_TX_CLK__PA_DIV_ID EQU 0x000000FF

; PDSS_PORT0_SAR_CLK
PDSS_PORT0_SAR_CLK__DIV_ID EQU 0x00000040
PDSS_PORT0_SAR_CLK__DIV_REGISTER EQU CYREG_PERI_DIV_16_CTL0
PDSS_PORT0_SAR_CLK__PA_DIV_ID EQU 0x000000FF

; PDSS_PORT0_SWAP_CLK
PDSS_PORT0_SWAP_CLK__DIV_ID EQU 0x00000002
PDSS_PORT0_SWAP_CLK__DIV_REGISTER EQU CYREG_PERI_DIV_8_CTL2
PDSS_PORT0_SWAP_CLK__PA_DIV_ID EQU 0x000000FF

; Miscellaneous
CYDEV_BCLK__HFCLK__HZ EQU 48000000
CYDEV_BCLK__HFCLK__KHZ EQU 48000
CYDEV_BCLK__HFCLK__MHZ EQU 48
CYDEV_BCLK__SYSCLK__HZ EQU 48000000
CYDEV_BCLK__SYSCLK__KHZ EQU 48000
CYDEV_BCLK__SYSCLK__MHZ EQU 48
CYDEV_CHIP_DIE_LEOPARD EQU 1
CYDEV_CHIP_DIE_PANTHER EQU 19
CYDEV_CHIP_DIE_PSOC4A EQU 11
CYDEV_CHIP_DIE_PSOC5LP EQU 18
CYDEV_CHIP_DIE_TMA4 EQU 2
CYDEV_CHIP_DIE_UNKNOWN EQU 0
CYDEV_CHIP_FAMILY_PSOC3 EQU 1
CYDEV_CHIP_FAMILY_PSOC4 EQU 2
CYDEV_CHIP_FAMILY_PSOC5 EQU 3
CYDEV_CHIP_FAMILY_UNKNOWN EQU 0
CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC4
CYDEV_CHIP_JTAG_ID EQU 0x1D0411AD
CYDEV_CHIP_MEMBER_3A EQU 1
CYDEV_CHIP_MEMBER_4A EQU 11
CYDEV_CHIP_MEMBER_4C EQU 16
CYDEV_CHIP_MEMBER_4D EQU 7
CYDEV_CHIP_MEMBER_4E EQU 4
CYDEV_CHIP_MEMBER_4F EQU 12
CYDEV_CHIP_MEMBER_4G EQU 2
CYDEV_CHIP_MEMBER_4H EQU 10
CYDEV_CHIP_MEMBER_4I EQU 15
CYDEV_CHIP_MEMBER_4J EQU 8
CYDEV_CHIP_MEMBER_4K EQU 9
CYDEV_CHIP_MEMBER_4L EQU 14
CYDEV_CHIP_MEMBER_4M EQU 13
CYDEV_CHIP_MEMBER_4N EQU 6
CYDEV_CHIP_MEMBER_4O EQU 5
CYDEV_CHIP_MEMBER_4U EQU 3
CYDEV_CHIP_MEMBER_5A EQU 18
CYDEV_CHIP_MEMBER_5B EQU 17
CYDEV_CHIP_MEMBER_UNKNOWN EQU 0
CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_4O
CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_MEMBER_USED
CYDEV_CHIP_DIE_ACTUAL EQU CYDEV_CHIP_DIE_EXPECT
CYDEV_CHIP_REV_LEOPARD_ES1 EQU 0
CYDEV_CHIP_REV_LEOPARD_ES2 EQU 1
CYDEV_CHIP_REV_LEOPARD_ES3 EQU 3
CYDEV_CHIP_REV_LEOPARD_PRODUCTION EQU 3
CYDEV_CHIP_REV_PANTHER_ES0 EQU 0
CYDEV_CHIP_REV_PANTHER_ES1 EQU 1
CYDEV_CHIP_REV_PANTHER_PRODUCTION EQU 1
CYDEV_CHIP_REV_PSOC4A_ES0 EQU 17
CYDEV_CHIP_REV_PSOC4A_PRODUCTION EQU 17
CYDEV_CHIP_REV_PSOC5LP_ES0 EQU 0
CYDEV_CHIP_REV_PSOC5LP_PRODUCTION EQU 0
CYDEV_CHIP_REV_TMA4_ES EQU 17
CYDEV_CHIP_REV_TMA4_ES2 EQU 33
CYDEV_CHIP_REV_TMA4_PRODUCTION EQU 17
CYDEV_CHIP_REVISION_3A_ES1 EQU 0
CYDEV_CHIP_REVISION_3A_ES2 EQU 1
CYDEV_CHIP_REVISION_3A_ES3 EQU 3
CYDEV_CHIP_REVISION_3A_PRODUCTION EQU 3
CYDEV_CHIP_REVISION_4A_ES0 EQU 17
CYDEV_CHIP_REVISION_4A_PRODUCTION EQU 17
CYDEV_CHIP_REVISION_4C_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4D_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4E_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4F_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4F_PRODUCTION_256DMA EQU 0
CYDEV_CHIP_REVISION_4F_PRODUCTION_256K EQU 0
CYDEV_CHIP_REVISION_4G_ES EQU 17
CYDEV_CHIP_REVISION_4G_ES2 EQU 33
CYDEV_CHIP_REVISION_4G_PRODUCTION EQU 17
CYDEV_CHIP_REVISION_4H_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4I_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4J_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4K_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4L_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4M_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4N_ES EQU 0
CYDEV_CHIP_REVISION_4N_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4O_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4U_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_5A_ES0 EQU 0
CYDEV_CHIP_REVISION_5A_ES1 EQU 1
CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1
CYDEV_CHIP_REVISION_5B_ES0 EQU 0
CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_USED EQU CYDEV_CHIP_REVISION_4O_PRODUCTION
CYDEV_CHIP_REV_EXPECT EQU CYDEV_CHIP_REVISION_USED
CYDEV_CONFIG_READ_ACCELERATOR EQU 1
CYDEV_CONFIG_UNUSED_IO_AllowButWarn EQU 0
CYDEV_CONFIG_UNUSED_IO_AllowWithInfo EQU 1
CYDEV_CONFIG_UNUSED_IO_Disallowed EQU 2
CYDEV_CONFIGURATION_COMPRESSED EQU 1
CYDEV_CONFIGURATION_MODE_COMPRESSED EQU 0
CYDEV_CONFIGURATION_MODE EQU CYDEV_CONFIGURATION_MODE_COMPRESSED
CYDEV_CONFIGURATION_MODE_DMA EQU 2
CYDEV_CONFIGURATION_MODE_UNCOMPRESSED EQU 1
CYDEV_DEBUG_PROTECT_KILL EQU 4
CYDEV_DEBUG_PROTECT_OPEN EQU 1
CYDEV_DEBUG_PROTECT EQU CYDEV_DEBUG_PROTECT_OPEN
CYDEV_DEBUG_PROTECT_PROTECTED EQU 2
CYDEV_DEBUGGING_DPS_Disable EQU 3
CYDEV_DEBUGGING_DPS EQU CYDEV_DEBUGGING_DPS_Disable
CYDEV_DEBUGGING_DPS_SWD EQU 2
CYDEV_DEBUGGING_ENABLE EQU 0
CYDEV_DFT_SELECT_CLK0 EQU 8
CYDEV_DFT_SELECT_CLK1 EQU 9
CYDEV_HEAP_SIZE EQU 0x80
CYDEV_IMO_TRIMMED_BY_USB EQU 0
CYDEV_IMO_TRIMMED_BY_WCO EQU 0
CYDEV_IS_EXPORTING_CODE EQU 0
CYDEV_IS_IMPORTING_CODE EQU 0
CYDEV_PROJ_TYPE EQU 2
CYDEV_PROJ_TYPE_BOOTLOADER EQU 1
CYDEV_PROJ_TYPE_LAUNCHER EQU 5
CYDEV_PROJ_TYPE_LOADABLE EQU 2
CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER EQU 4
CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER EQU 3
CYDEV_PROJ_TYPE_STANDARD EQU 0
CYDEV_STACK_SIZE EQU 0x0800
CYDEV_USE_BUNDLED_CMSIS EQU 1
CYDEV_VARIABLE_VDDA EQU 1
CYDEV_VDDD_MV EQU 3300
CYDEV_VDDIO_MV EQU 3300
CYDEV_WDT_GENERATE_ISR EQU 0
CYIPBLOCK_m0s8cpussv3_VERSION EQU 1
CYIPBLOCK_m0s8crypto_VERSION EQU 2
CYIPBLOCK_m0s8ioss_VERSION EQU 1
CYIPBLOCK_m0s8peri_VERSION EQU 1
CYIPBLOCK_m0s8scb_VERSION EQU 2
CYIPBLOCK_m0s8tcpwm_VERSION EQU 2
CYIPBLOCK_m0s8usbdss_VERSION EQU 2
CYIPBLOCK_m0s8usbpd_VERSION EQU 2
CYIPBLOCK_s8srsslt_VERSION EQU 1
CYDEV_BOOTLOADER_ENABLE EQU 0
    ENDIF
    END
