#ifndef INCLUDED_CYFITTER_H
#define INCLUDED_CYFITTER_H
#include "cydevice_trm.h"

/* HPD */
#define HPD__0__DR CYREG_GPIO_PRT3_DR
#define HPD__0__DR_CLR CYREG_GPIO_PRT3_DR_CLR
#define HPD__0__DR_INV CYREG_GPIO_PRT3_DR_INV
#define HPD__0__DR_SET CYREG_GPIO_PRT3_DR_SET
#define HPD__0__HSIOM CYREG_HSIOM_PORT_SEL3
#define HPD__0__HSIOM_MASK 0x0000F000u
#define HPD__0__HSIOM_SHIFT 12u
#define HPD__0__INTCFG CYREG_GPIO_PRT3_INTR_CFG
#define HPD__0__INTR CYREG_GPIO_PRT3_INTR
#define HPD__0__INTR_CFG CYREG_GPIO_PRT3_INTR_CFG
#define HPD__0__INTSTAT CYREG_GPIO_PRT3_INTR
#define HPD__0__MASK 0x08u
#define HPD__0__PC CYREG_GPIO_PRT3_PC
#define HPD__0__PC2 CYREG_GPIO_PRT3_PC2
#define HPD__0__PORT 3u
#define HPD__0__PS CYREG_GPIO_PRT3_PS
#define HPD__0__SHIFT 3u
#define HPD__DR CYREG_GPIO_PRT3_DR
#define HPD__DR_CLR CYREG_GPIO_PRT3_DR_CLR
#define HPD__DR_INV CYREG_GPIO_PRT3_DR_INV
#define HPD__DR_SET CYREG_GPIO_PRT3_DR_SET
#define HPD__INTCFG CYREG_GPIO_PRT3_INTR_CFG
#define HPD__INTR CYREG_GPIO_PRT3_INTR
#define HPD__INTR_CFG CYREG_GPIO_PRT3_INTR_CFG
#define HPD__INTSTAT CYREG_GPIO_PRT3_INTR
#define HPD__MASK 0x08u
#define HPD__PC CYREG_GPIO_PRT3_PC
#define HPD__PC2 CYREG_GPIO_PRT3_PC2
#define HPD__PORT 3u
#define HPD__PS CYREG_GPIO_PRT3_PS
#define HPD__SHIFT 3u

/* EC_INT */
#define EC_INT__0__DR CYREG_GPIO_PRT3_DR
#define EC_INT__0__DR_CLR CYREG_GPIO_PRT3_DR_CLR
#define EC_INT__0__DR_INV CYREG_GPIO_PRT3_DR_INV
#define EC_INT__0__DR_SET CYREG_GPIO_PRT3_DR_SET
#define EC_INT__0__HSIOM CYREG_HSIOM_PORT_SEL3
#define EC_INT__0__HSIOM_MASK 0x00000F00u
#define EC_INT__0__HSIOM_SHIFT 8u
#define EC_INT__0__INTCFG CYREG_GPIO_PRT3_INTR_CFG
#define EC_INT__0__INTR CYREG_GPIO_PRT3_INTR
#define EC_INT__0__INTR_CFG CYREG_GPIO_PRT3_INTR_CFG
#define EC_INT__0__INTSTAT CYREG_GPIO_PRT3_INTR
#define EC_INT__0__MASK 0x04u
#define EC_INT__0__PC CYREG_GPIO_PRT3_PC
#define EC_INT__0__PC2 CYREG_GPIO_PRT3_PC2
#define EC_INT__0__PORT 3u
#define EC_INT__0__PS CYREG_GPIO_PRT3_PS
#define EC_INT__0__SHIFT 2u
#define EC_INT__DR CYREG_GPIO_PRT3_DR
#define EC_INT__DR_CLR CYREG_GPIO_PRT3_DR_CLR
#define EC_INT__DR_INV CYREG_GPIO_PRT3_DR_INV
#define EC_INT__DR_SET CYREG_GPIO_PRT3_DR_SET
#define EC_INT__INTCFG CYREG_GPIO_PRT3_INTR_CFG
#define EC_INT__INTR CYREG_GPIO_PRT3_INTR
#define EC_INT__INTR_CFG CYREG_GPIO_PRT3_INTR_CFG
#define EC_INT__INTSTAT CYREG_GPIO_PRT3_INTR
#define EC_INT__MASK 0x04u
#define EC_INT__PC CYREG_GPIO_PRT3_PC
#define EC_INT__PC2 CYREG_GPIO_PRT3_PC2
#define EC_INT__PORT 3u
#define EC_INT__PS CYREG_GPIO_PRT3_PS
#define EC_INT__SHIFT 2u

/* FW_LED */
#define FW_LED__0__DR CYREG_GPIO_PRT2_DR
#define FW_LED__0__DR_CLR CYREG_GPIO_PRT2_DR_CLR
#define FW_LED__0__DR_INV CYREG_GPIO_PRT2_DR_INV
#define FW_LED__0__DR_SET CYREG_GPIO_PRT2_DR_SET
#define FW_LED__0__HSIOM CYREG_HSIOM_PORT_SEL2
#define FW_LED__0__HSIOM_MASK 0x0000000Fu
#define FW_LED__0__HSIOM_SHIFT 0u
#define FW_LED__0__INTCFG CYREG_GPIO_PRT2_INTR_CFG
#define FW_LED__0__INTR CYREG_GPIO_PRT2_INTR
#define FW_LED__0__INTR_CFG CYREG_GPIO_PRT2_INTR_CFG
#define FW_LED__0__INTSTAT CYREG_GPIO_PRT2_INTR
#define FW_LED__0__MASK 0x01u
#define FW_LED__0__PC CYREG_GPIO_PRT2_PC
#define FW_LED__0__PC2 CYREG_GPIO_PRT2_PC2
#define FW_LED__0__PORT 2u
#define FW_LED__0__PS CYREG_GPIO_PRT2_PS
#define FW_LED__0__SHIFT 0u
#define FW_LED__DR CYREG_GPIO_PRT2_DR
#define FW_LED__DR_CLR CYREG_GPIO_PRT2_DR_CLR
#define FW_LED__DR_INV CYREG_GPIO_PRT2_DR_INV
#define FW_LED__DR_SET CYREG_GPIO_PRT2_DR_SET
#define FW_LED__INTCFG CYREG_GPIO_PRT2_INTR_CFG
#define FW_LED__INTR CYREG_GPIO_PRT2_INTR
#define FW_LED__INTR_CFG CYREG_GPIO_PRT2_INTR_CFG
#define FW_LED__INTSTAT CYREG_GPIO_PRT2_INTR
#define FW_LED__MASK 0x01u
#define FW_LED__PC CYREG_GPIO_PRT2_PC
#define FW_LED__PC2 CYREG_GPIO_PRT2_PC2
#define FW_LED__PORT 2u
#define FW_LED__PS CYREG_GPIO_PRT2_PS
#define FW_LED__SHIFT 0u

/* I2C_CFG */
#define I2C_CFG__0__DR CYREG_GPIO_PRT2_DR
#define I2C_CFG__0__DR_CLR CYREG_GPIO_PRT2_DR_CLR
#define I2C_CFG__0__DR_INV CYREG_GPIO_PRT2_DR_INV
#define I2C_CFG__0__DR_SET CYREG_GPIO_PRT2_DR_SET
#define I2C_CFG__0__HSIOM CYREG_HSIOM_PORT_SEL2
#define I2C_CFG__0__HSIOM_MASK 0x000000F0u
#define I2C_CFG__0__HSIOM_SHIFT 4u
#define I2C_CFG__0__INTCFG CYREG_GPIO_PRT2_INTR_CFG
#define I2C_CFG__0__INTR CYREG_GPIO_PRT2_INTR
#define I2C_CFG__0__INTR_CFG CYREG_GPIO_PRT2_INTR_CFG
#define I2C_CFG__0__INTSTAT CYREG_GPIO_PRT2_INTR
#define I2C_CFG__0__MASK 0x02u
#define I2C_CFG__0__PC CYREG_GPIO_PRT2_PC
#define I2C_CFG__0__PC2 CYREG_GPIO_PRT2_PC2
#define I2C_CFG__0__PORT 2u
#define I2C_CFG__0__PS CYREG_GPIO_PRT2_PS
#define I2C_CFG__0__SHIFT 1u
#define I2C_CFG__DR CYREG_GPIO_PRT2_DR
#define I2C_CFG__DR_CLR CYREG_GPIO_PRT2_DR_CLR
#define I2C_CFG__DR_INV CYREG_GPIO_PRT2_DR_INV
#define I2C_CFG__DR_SET CYREG_GPIO_PRT2_DR_SET
#define I2C_CFG__INTCFG CYREG_GPIO_PRT2_INTR_CFG
#define I2C_CFG__INTR CYREG_GPIO_PRT2_INTR
#define I2C_CFG__INTR_CFG CYREG_GPIO_PRT2_INTR_CFG
#define I2C_CFG__INTSTAT CYREG_GPIO_PRT2_INTR
#define I2C_CFG__MASK 0x02u
#define I2C_CFG__PC CYREG_GPIO_PRT2_PC
#define I2C_CFG__PC2 CYREG_GPIO_PRT2_PC2
#define I2C_CFG__PORT 2u
#define I2C_CFG__PS CYREG_GPIO_PRT2_PS
#define I2C_CFG__SHIFT 1u

/* MUX_CTRL_SCB */
#define MUX_CTRL_SCB__CMD_RESP_CTRL CYREG_SCB3_CMD_RESP_CTRL
#define MUX_CTRL_SCB__CMD_RESP_STATUS CYREG_SCB3_CMD_RESP_STATUS
#define MUX_CTRL_SCB__CTRL CYREG_SCB3_CTRL
#define MUX_CTRL_SCB__EZ_DATA0 CYREG_SCB3_EZ_DATA0
#define MUX_CTRL_SCB__EZ_DATA1 CYREG_SCB3_EZ_DATA1
#define MUX_CTRL_SCB__EZ_DATA10 CYREG_SCB3_EZ_DATA10
#define MUX_CTRL_SCB__EZ_DATA100 CYREG_SCB3_EZ_DATA100
#define MUX_CTRL_SCB__EZ_DATA101 CYREG_SCB3_EZ_DATA101
#define MUX_CTRL_SCB__EZ_DATA102 CYREG_SCB3_EZ_DATA102
#define MUX_CTRL_SCB__EZ_DATA103 CYREG_SCB3_EZ_DATA103
#define MUX_CTRL_SCB__EZ_DATA104 CYREG_SCB3_EZ_DATA104
#define MUX_CTRL_SCB__EZ_DATA105 CYREG_SCB3_EZ_DATA105
#define MUX_CTRL_SCB__EZ_DATA106 CYREG_SCB3_EZ_DATA106
#define MUX_CTRL_SCB__EZ_DATA107 CYREG_SCB3_EZ_DATA107
#define MUX_CTRL_SCB__EZ_DATA108 CYREG_SCB3_EZ_DATA108
#define MUX_CTRL_SCB__EZ_DATA109 CYREG_SCB3_EZ_DATA109
#define MUX_CTRL_SCB__EZ_DATA11 CYREG_SCB3_EZ_DATA11
#define MUX_CTRL_SCB__EZ_DATA110 CYREG_SCB3_EZ_DATA110
#define MUX_CTRL_SCB__EZ_DATA111 CYREG_SCB3_EZ_DATA111
#define MUX_CTRL_SCB__EZ_DATA112 CYREG_SCB3_EZ_DATA112
#define MUX_CTRL_SCB__EZ_DATA113 CYREG_SCB3_EZ_DATA113
#define MUX_CTRL_SCB__EZ_DATA114 CYREG_SCB3_EZ_DATA114
#define MUX_CTRL_SCB__EZ_DATA115 CYREG_SCB3_EZ_DATA115
#define MUX_CTRL_SCB__EZ_DATA116 CYREG_SCB3_EZ_DATA116
#define MUX_CTRL_SCB__EZ_DATA117 CYREG_SCB3_EZ_DATA117
#define MUX_CTRL_SCB__EZ_DATA118 CYREG_SCB3_EZ_DATA118
#define MUX_CTRL_SCB__EZ_DATA119 CYREG_SCB3_EZ_DATA119
#define MUX_CTRL_SCB__EZ_DATA12 CYREG_SCB3_EZ_DATA12
#define MUX_CTRL_SCB__EZ_DATA120 CYREG_SCB3_EZ_DATA120
#define MUX_CTRL_SCB__EZ_DATA121 CYREG_SCB3_EZ_DATA121
#define MUX_CTRL_SCB__EZ_DATA122 CYREG_SCB3_EZ_DATA122
#define MUX_CTRL_SCB__EZ_DATA123 CYREG_SCB3_EZ_DATA123
#define MUX_CTRL_SCB__EZ_DATA124 CYREG_SCB3_EZ_DATA124
#define MUX_CTRL_SCB__EZ_DATA125 CYREG_SCB3_EZ_DATA125
#define MUX_CTRL_SCB__EZ_DATA126 CYREG_SCB3_EZ_DATA126
#define MUX_CTRL_SCB__EZ_DATA127 CYREG_SCB3_EZ_DATA127
#define MUX_CTRL_SCB__EZ_DATA128 CYREG_SCB3_EZ_DATA128
#define MUX_CTRL_SCB__EZ_DATA129 CYREG_SCB3_EZ_DATA129
#define MUX_CTRL_SCB__EZ_DATA13 CYREG_SCB3_EZ_DATA13
#define MUX_CTRL_SCB__EZ_DATA130 CYREG_SCB3_EZ_DATA130
#define MUX_CTRL_SCB__EZ_DATA131 CYREG_SCB3_EZ_DATA131
#define MUX_CTRL_SCB__EZ_DATA132 CYREG_SCB3_EZ_DATA132
#define MUX_CTRL_SCB__EZ_DATA133 CYREG_SCB3_EZ_DATA133
#define MUX_CTRL_SCB__EZ_DATA134 CYREG_SCB3_EZ_DATA134
#define MUX_CTRL_SCB__EZ_DATA135 CYREG_SCB3_EZ_DATA135
#define MUX_CTRL_SCB__EZ_DATA136 CYREG_SCB3_EZ_DATA136
#define MUX_CTRL_SCB__EZ_DATA137 CYREG_SCB3_EZ_DATA137
#define MUX_CTRL_SCB__EZ_DATA138 CYREG_SCB3_EZ_DATA138
#define MUX_CTRL_SCB__EZ_DATA139 CYREG_SCB3_EZ_DATA139
#define MUX_CTRL_SCB__EZ_DATA14 CYREG_SCB3_EZ_DATA14
#define MUX_CTRL_SCB__EZ_DATA140 CYREG_SCB3_EZ_DATA140
#define MUX_CTRL_SCB__EZ_DATA141 CYREG_SCB3_EZ_DATA141
#define MUX_CTRL_SCB__EZ_DATA142 CYREG_SCB3_EZ_DATA142
#define MUX_CTRL_SCB__EZ_DATA143 CYREG_SCB3_EZ_DATA143
#define MUX_CTRL_SCB__EZ_DATA144 CYREG_SCB3_EZ_DATA144
#define MUX_CTRL_SCB__EZ_DATA145 CYREG_SCB3_EZ_DATA145
#define MUX_CTRL_SCB__EZ_DATA146 CYREG_SCB3_EZ_DATA146
#define MUX_CTRL_SCB__EZ_DATA147 CYREG_SCB3_EZ_DATA147
#define MUX_CTRL_SCB__EZ_DATA148 CYREG_SCB3_EZ_DATA148
#define MUX_CTRL_SCB__EZ_DATA149 CYREG_SCB3_EZ_DATA149
#define MUX_CTRL_SCB__EZ_DATA15 CYREG_SCB3_EZ_DATA15
#define MUX_CTRL_SCB__EZ_DATA150 CYREG_SCB3_EZ_DATA150
#define MUX_CTRL_SCB__EZ_DATA151 CYREG_SCB3_EZ_DATA151
#define MUX_CTRL_SCB__EZ_DATA152 CYREG_SCB3_EZ_DATA152
#define MUX_CTRL_SCB__EZ_DATA153 CYREG_SCB3_EZ_DATA153
#define MUX_CTRL_SCB__EZ_DATA154 CYREG_SCB3_EZ_DATA154
#define MUX_CTRL_SCB__EZ_DATA155 CYREG_SCB3_EZ_DATA155
#define MUX_CTRL_SCB__EZ_DATA156 CYREG_SCB3_EZ_DATA156
#define MUX_CTRL_SCB__EZ_DATA157 CYREG_SCB3_EZ_DATA157
#define MUX_CTRL_SCB__EZ_DATA158 CYREG_SCB3_EZ_DATA158
#define MUX_CTRL_SCB__EZ_DATA159 CYREG_SCB3_EZ_DATA159
#define MUX_CTRL_SCB__EZ_DATA16 CYREG_SCB3_EZ_DATA16
#define MUX_CTRL_SCB__EZ_DATA160 CYREG_SCB3_EZ_DATA160
#define MUX_CTRL_SCB__EZ_DATA161 CYREG_SCB3_EZ_DATA161
#define MUX_CTRL_SCB__EZ_DATA162 CYREG_SCB3_EZ_DATA162
#define MUX_CTRL_SCB__EZ_DATA163 CYREG_SCB3_EZ_DATA163
#define MUX_CTRL_SCB__EZ_DATA164 CYREG_SCB3_EZ_DATA164
#define MUX_CTRL_SCB__EZ_DATA165 CYREG_SCB3_EZ_DATA165
#define MUX_CTRL_SCB__EZ_DATA166 CYREG_SCB3_EZ_DATA166
#define MUX_CTRL_SCB__EZ_DATA167 CYREG_SCB3_EZ_DATA167
#define MUX_CTRL_SCB__EZ_DATA168 CYREG_SCB3_EZ_DATA168
#define MUX_CTRL_SCB__EZ_DATA169 CYREG_SCB3_EZ_DATA169
#define MUX_CTRL_SCB__EZ_DATA17 CYREG_SCB3_EZ_DATA17
#define MUX_CTRL_SCB__EZ_DATA170 CYREG_SCB3_EZ_DATA170
#define MUX_CTRL_SCB__EZ_DATA171 CYREG_SCB3_EZ_DATA171
#define MUX_CTRL_SCB__EZ_DATA172 CYREG_SCB3_EZ_DATA172
#define MUX_CTRL_SCB__EZ_DATA173 CYREG_SCB3_EZ_DATA173
#define MUX_CTRL_SCB__EZ_DATA174 CYREG_SCB3_EZ_DATA174
#define MUX_CTRL_SCB__EZ_DATA175 CYREG_SCB3_EZ_DATA175
#define MUX_CTRL_SCB__EZ_DATA176 CYREG_SCB3_EZ_DATA176
#define MUX_CTRL_SCB__EZ_DATA177 CYREG_SCB3_EZ_DATA177
#define MUX_CTRL_SCB__EZ_DATA178 CYREG_SCB3_EZ_DATA178
#define MUX_CTRL_SCB__EZ_DATA179 CYREG_SCB3_EZ_DATA179
#define MUX_CTRL_SCB__EZ_DATA18 CYREG_SCB3_EZ_DATA18
#define MUX_CTRL_SCB__EZ_DATA180 CYREG_SCB3_EZ_DATA180
#define MUX_CTRL_SCB__EZ_DATA181 CYREG_SCB3_EZ_DATA181
#define MUX_CTRL_SCB__EZ_DATA182 CYREG_SCB3_EZ_DATA182
#define MUX_CTRL_SCB__EZ_DATA183 CYREG_SCB3_EZ_DATA183
#define MUX_CTRL_SCB__EZ_DATA184 CYREG_SCB3_EZ_DATA184
#define MUX_CTRL_SCB__EZ_DATA185 CYREG_SCB3_EZ_DATA185
#define MUX_CTRL_SCB__EZ_DATA186 CYREG_SCB3_EZ_DATA186
#define MUX_CTRL_SCB__EZ_DATA187 CYREG_SCB3_EZ_DATA187
#define MUX_CTRL_SCB__EZ_DATA188 CYREG_SCB3_EZ_DATA188
#define MUX_CTRL_SCB__EZ_DATA189 CYREG_SCB3_EZ_DATA189
#define MUX_CTRL_SCB__EZ_DATA19 CYREG_SCB3_EZ_DATA19
#define MUX_CTRL_SCB__EZ_DATA190 CYREG_SCB3_EZ_DATA190
#define MUX_CTRL_SCB__EZ_DATA191 CYREG_SCB3_EZ_DATA191
#define MUX_CTRL_SCB__EZ_DATA192 CYREG_SCB3_EZ_DATA192
#define MUX_CTRL_SCB__EZ_DATA193 CYREG_SCB3_EZ_DATA193
#define MUX_CTRL_SCB__EZ_DATA194 CYREG_SCB3_EZ_DATA194
#define MUX_CTRL_SCB__EZ_DATA195 CYREG_SCB3_EZ_DATA195
#define MUX_CTRL_SCB__EZ_DATA196 CYREG_SCB3_EZ_DATA196
#define MUX_CTRL_SCB__EZ_DATA197 CYREG_SCB3_EZ_DATA197
#define MUX_CTRL_SCB__EZ_DATA198 CYREG_SCB3_EZ_DATA198
#define MUX_CTRL_SCB__EZ_DATA199 CYREG_SCB3_EZ_DATA199
#define MUX_CTRL_SCB__EZ_DATA2 CYREG_SCB3_EZ_DATA2
#define MUX_CTRL_SCB__EZ_DATA20 CYREG_SCB3_EZ_DATA20
#define MUX_CTRL_SCB__EZ_DATA200 CYREG_SCB3_EZ_DATA200
#define MUX_CTRL_SCB__EZ_DATA201 CYREG_SCB3_EZ_DATA201
#define MUX_CTRL_SCB__EZ_DATA202 CYREG_SCB3_EZ_DATA202
#define MUX_CTRL_SCB__EZ_DATA203 CYREG_SCB3_EZ_DATA203
#define MUX_CTRL_SCB__EZ_DATA204 CYREG_SCB3_EZ_DATA204
#define MUX_CTRL_SCB__EZ_DATA205 CYREG_SCB3_EZ_DATA205
#define MUX_CTRL_SCB__EZ_DATA206 CYREG_SCB3_EZ_DATA206
#define MUX_CTRL_SCB__EZ_DATA207 CYREG_SCB3_EZ_DATA207
#define MUX_CTRL_SCB__EZ_DATA208 CYREG_SCB3_EZ_DATA208
#define MUX_CTRL_SCB__EZ_DATA209 CYREG_SCB3_EZ_DATA209
#define MUX_CTRL_SCB__EZ_DATA21 CYREG_SCB3_EZ_DATA21
#define MUX_CTRL_SCB__EZ_DATA210 CYREG_SCB3_EZ_DATA210
#define MUX_CTRL_SCB__EZ_DATA211 CYREG_SCB3_EZ_DATA211
#define MUX_CTRL_SCB__EZ_DATA212 CYREG_SCB3_EZ_DATA212
#define MUX_CTRL_SCB__EZ_DATA213 CYREG_SCB3_EZ_DATA213
#define MUX_CTRL_SCB__EZ_DATA214 CYREG_SCB3_EZ_DATA214
#define MUX_CTRL_SCB__EZ_DATA215 CYREG_SCB3_EZ_DATA215
#define MUX_CTRL_SCB__EZ_DATA216 CYREG_SCB3_EZ_DATA216
#define MUX_CTRL_SCB__EZ_DATA217 CYREG_SCB3_EZ_DATA217
#define MUX_CTRL_SCB__EZ_DATA218 CYREG_SCB3_EZ_DATA218
#define MUX_CTRL_SCB__EZ_DATA219 CYREG_SCB3_EZ_DATA219
#define MUX_CTRL_SCB__EZ_DATA22 CYREG_SCB3_EZ_DATA22
#define MUX_CTRL_SCB__EZ_DATA220 CYREG_SCB3_EZ_DATA220
#define MUX_CTRL_SCB__EZ_DATA221 CYREG_SCB3_EZ_DATA221
#define MUX_CTRL_SCB__EZ_DATA222 CYREG_SCB3_EZ_DATA222
#define MUX_CTRL_SCB__EZ_DATA223 CYREG_SCB3_EZ_DATA223
#define MUX_CTRL_SCB__EZ_DATA224 CYREG_SCB3_EZ_DATA224
#define MUX_CTRL_SCB__EZ_DATA225 CYREG_SCB3_EZ_DATA225
#define MUX_CTRL_SCB__EZ_DATA226 CYREG_SCB3_EZ_DATA226
#define MUX_CTRL_SCB__EZ_DATA227 CYREG_SCB3_EZ_DATA227
#define MUX_CTRL_SCB__EZ_DATA228 CYREG_SCB3_EZ_DATA228
#define MUX_CTRL_SCB__EZ_DATA229 CYREG_SCB3_EZ_DATA229
#define MUX_CTRL_SCB__EZ_DATA23 CYREG_SCB3_EZ_DATA23
#define MUX_CTRL_SCB__EZ_DATA230 CYREG_SCB3_EZ_DATA230
#define MUX_CTRL_SCB__EZ_DATA231 CYREG_SCB3_EZ_DATA231
#define MUX_CTRL_SCB__EZ_DATA232 CYREG_SCB3_EZ_DATA232
#define MUX_CTRL_SCB__EZ_DATA233 CYREG_SCB3_EZ_DATA233
#define MUX_CTRL_SCB__EZ_DATA234 CYREG_SCB3_EZ_DATA234
#define MUX_CTRL_SCB__EZ_DATA235 CYREG_SCB3_EZ_DATA235
#define MUX_CTRL_SCB__EZ_DATA236 CYREG_SCB3_EZ_DATA236
#define MUX_CTRL_SCB__EZ_DATA237 CYREG_SCB3_EZ_DATA237
#define MUX_CTRL_SCB__EZ_DATA238 CYREG_SCB3_EZ_DATA238
#define MUX_CTRL_SCB__EZ_DATA239 CYREG_SCB3_EZ_DATA239
#define MUX_CTRL_SCB__EZ_DATA24 CYREG_SCB3_EZ_DATA24
#define MUX_CTRL_SCB__EZ_DATA240 CYREG_SCB3_EZ_DATA240
#define MUX_CTRL_SCB__EZ_DATA241 CYREG_SCB3_EZ_DATA241
#define MUX_CTRL_SCB__EZ_DATA242 CYREG_SCB3_EZ_DATA242
#define MUX_CTRL_SCB__EZ_DATA243 CYREG_SCB3_EZ_DATA243
#define MUX_CTRL_SCB__EZ_DATA244 CYREG_SCB3_EZ_DATA244
#define MUX_CTRL_SCB__EZ_DATA245 CYREG_SCB3_EZ_DATA245
#define MUX_CTRL_SCB__EZ_DATA246 CYREG_SCB3_EZ_DATA246
#define MUX_CTRL_SCB__EZ_DATA247 CYREG_SCB3_EZ_DATA247
#define MUX_CTRL_SCB__EZ_DATA248 CYREG_SCB3_EZ_DATA248
#define MUX_CTRL_SCB__EZ_DATA249 CYREG_SCB3_EZ_DATA249
#define MUX_CTRL_SCB__EZ_DATA25 CYREG_SCB3_EZ_DATA25
#define MUX_CTRL_SCB__EZ_DATA250 CYREG_SCB3_EZ_DATA250
#define MUX_CTRL_SCB__EZ_DATA251 CYREG_SCB3_EZ_DATA251
#define MUX_CTRL_SCB__EZ_DATA252 CYREG_SCB3_EZ_DATA252
#define MUX_CTRL_SCB__EZ_DATA253 CYREG_SCB3_EZ_DATA253
#define MUX_CTRL_SCB__EZ_DATA254 CYREG_SCB3_EZ_DATA254
#define MUX_CTRL_SCB__EZ_DATA255 CYREG_SCB3_EZ_DATA255
#define MUX_CTRL_SCB__EZ_DATA26 CYREG_SCB3_EZ_DATA26
#define MUX_CTRL_SCB__EZ_DATA27 CYREG_SCB3_EZ_DATA27
#define MUX_CTRL_SCB__EZ_DATA28 CYREG_SCB3_EZ_DATA28
#define MUX_CTRL_SCB__EZ_DATA29 CYREG_SCB3_EZ_DATA29
#define MUX_CTRL_SCB__EZ_DATA3 CYREG_SCB3_EZ_DATA3
#define MUX_CTRL_SCB__EZ_DATA30 CYREG_SCB3_EZ_DATA30
#define MUX_CTRL_SCB__EZ_DATA31 CYREG_SCB3_EZ_DATA31
#define MUX_CTRL_SCB__EZ_DATA32 CYREG_SCB3_EZ_DATA32
#define MUX_CTRL_SCB__EZ_DATA33 CYREG_SCB3_EZ_DATA33
#define MUX_CTRL_SCB__EZ_DATA34 CYREG_SCB3_EZ_DATA34
#define MUX_CTRL_SCB__EZ_DATA35 CYREG_SCB3_EZ_DATA35
#define MUX_CTRL_SCB__EZ_DATA36 CYREG_SCB3_EZ_DATA36
#define MUX_CTRL_SCB__EZ_DATA37 CYREG_SCB3_EZ_DATA37
#define MUX_CTRL_SCB__EZ_DATA38 CYREG_SCB3_EZ_DATA38
#define MUX_CTRL_SCB__EZ_DATA39 CYREG_SCB3_EZ_DATA39
#define MUX_CTRL_SCB__EZ_DATA4 CYREG_SCB3_EZ_DATA4
#define MUX_CTRL_SCB__EZ_DATA40 CYREG_SCB3_EZ_DATA40
#define MUX_CTRL_SCB__EZ_DATA41 CYREG_SCB3_EZ_DATA41
#define MUX_CTRL_SCB__EZ_DATA42 CYREG_SCB3_EZ_DATA42
#define MUX_CTRL_SCB__EZ_DATA43 CYREG_SCB3_EZ_DATA43
#define MUX_CTRL_SCB__EZ_DATA44 CYREG_SCB3_EZ_DATA44
#define MUX_CTRL_SCB__EZ_DATA45 CYREG_SCB3_EZ_DATA45
#define MUX_CTRL_SCB__EZ_DATA46 CYREG_SCB3_EZ_DATA46
#define MUX_CTRL_SCB__EZ_DATA47 CYREG_SCB3_EZ_DATA47
#define MUX_CTRL_SCB__EZ_DATA48 CYREG_SCB3_EZ_DATA48
#define MUX_CTRL_SCB__EZ_DATA49 CYREG_SCB3_EZ_DATA49
#define MUX_CTRL_SCB__EZ_DATA5 CYREG_SCB3_EZ_DATA5
#define MUX_CTRL_SCB__EZ_DATA50 CYREG_SCB3_EZ_DATA50
#define MUX_CTRL_SCB__EZ_DATA51 CYREG_SCB3_EZ_DATA51
#define MUX_CTRL_SCB__EZ_DATA52 CYREG_SCB3_EZ_DATA52
#define MUX_CTRL_SCB__EZ_DATA53 CYREG_SCB3_EZ_DATA53
#define MUX_CTRL_SCB__EZ_DATA54 CYREG_SCB3_EZ_DATA54
#define MUX_CTRL_SCB__EZ_DATA55 CYREG_SCB3_EZ_DATA55
#define MUX_CTRL_SCB__EZ_DATA56 CYREG_SCB3_EZ_DATA56
#define MUX_CTRL_SCB__EZ_DATA57 CYREG_SCB3_EZ_DATA57
#define MUX_CTRL_SCB__EZ_DATA58 CYREG_SCB3_EZ_DATA58
#define MUX_CTRL_SCB__EZ_DATA59 CYREG_SCB3_EZ_DATA59
#define MUX_CTRL_SCB__EZ_DATA6 CYREG_SCB3_EZ_DATA6
#define MUX_CTRL_SCB__EZ_DATA60 CYREG_SCB3_EZ_DATA60
#define MUX_CTRL_SCB__EZ_DATA61 CYREG_SCB3_EZ_DATA61
#define MUX_CTRL_SCB__EZ_DATA62 CYREG_SCB3_EZ_DATA62
#define MUX_CTRL_SCB__EZ_DATA63 CYREG_SCB3_EZ_DATA63
#define MUX_CTRL_SCB__EZ_DATA64 CYREG_SCB3_EZ_DATA64
#define MUX_CTRL_SCB__EZ_DATA65 CYREG_SCB3_EZ_DATA65
#define MUX_CTRL_SCB__EZ_DATA66 CYREG_SCB3_EZ_DATA66
#define MUX_CTRL_SCB__EZ_DATA67 CYREG_SCB3_EZ_DATA67
#define MUX_CTRL_SCB__EZ_DATA68 CYREG_SCB3_EZ_DATA68
#define MUX_CTRL_SCB__EZ_DATA69 CYREG_SCB3_EZ_DATA69
#define MUX_CTRL_SCB__EZ_DATA7 CYREG_SCB3_EZ_DATA7
#define MUX_CTRL_SCB__EZ_DATA70 CYREG_SCB3_EZ_DATA70
#define MUX_CTRL_SCB__EZ_DATA71 CYREG_SCB3_EZ_DATA71
#define MUX_CTRL_SCB__EZ_DATA72 CYREG_SCB3_EZ_DATA72
#define MUX_CTRL_SCB__EZ_DATA73 CYREG_SCB3_EZ_DATA73
#define MUX_CTRL_SCB__EZ_DATA74 CYREG_SCB3_EZ_DATA74
#define MUX_CTRL_SCB__EZ_DATA75 CYREG_SCB3_EZ_DATA75
#define MUX_CTRL_SCB__EZ_DATA76 CYREG_SCB3_EZ_DATA76
#define MUX_CTRL_SCB__EZ_DATA77 CYREG_SCB3_EZ_DATA77
#define MUX_CTRL_SCB__EZ_DATA78 CYREG_SCB3_EZ_DATA78
#define MUX_CTRL_SCB__EZ_DATA79 CYREG_SCB3_EZ_DATA79
#define MUX_CTRL_SCB__EZ_DATA8 CYREG_SCB3_EZ_DATA8
#define MUX_CTRL_SCB__EZ_DATA80 CYREG_SCB3_EZ_DATA80
#define MUX_CTRL_SCB__EZ_DATA81 CYREG_SCB3_EZ_DATA81
#define MUX_CTRL_SCB__EZ_DATA82 CYREG_SCB3_EZ_DATA82
#define MUX_CTRL_SCB__EZ_DATA83 CYREG_SCB3_EZ_DATA83
#define MUX_CTRL_SCB__EZ_DATA84 CYREG_SCB3_EZ_DATA84
#define MUX_CTRL_SCB__EZ_DATA85 CYREG_SCB3_EZ_DATA85
#define MUX_CTRL_SCB__EZ_DATA86 CYREG_SCB3_EZ_DATA86
#define MUX_CTRL_SCB__EZ_DATA87 CYREG_SCB3_EZ_DATA87
#define MUX_CTRL_SCB__EZ_DATA88 CYREG_SCB3_EZ_DATA88
#define MUX_CTRL_SCB__EZ_DATA89 CYREG_SCB3_EZ_DATA89
#define MUX_CTRL_SCB__EZ_DATA9 CYREG_SCB3_EZ_DATA9
#define MUX_CTRL_SCB__EZ_DATA90 CYREG_SCB3_EZ_DATA90
#define MUX_CTRL_SCB__EZ_DATA91 CYREG_SCB3_EZ_DATA91
#define MUX_CTRL_SCB__EZ_DATA92 CYREG_SCB3_EZ_DATA92
#define MUX_CTRL_SCB__EZ_DATA93 CYREG_SCB3_EZ_DATA93
#define MUX_CTRL_SCB__EZ_DATA94 CYREG_SCB3_EZ_DATA94
#define MUX_CTRL_SCB__EZ_DATA95 CYREG_SCB3_EZ_DATA95
#define MUX_CTRL_SCB__EZ_DATA96 CYREG_SCB3_EZ_DATA96
#define MUX_CTRL_SCB__EZ_DATA97 CYREG_SCB3_EZ_DATA97
#define MUX_CTRL_SCB__EZ_DATA98 CYREG_SCB3_EZ_DATA98
#define MUX_CTRL_SCB__EZ_DATA99 CYREG_SCB3_EZ_DATA99
#define MUX_CTRL_SCB__I2C_CFG CYREG_SCB3_I2C_CFG
#define MUX_CTRL_SCB__I2C_CTRL CYREG_SCB3_I2C_CTRL
#define MUX_CTRL_SCB__I2C_M_CMD CYREG_SCB3_I2C_M_CMD
#define MUX_CTRL_SCB__I2C_S_CMD CYREG_SCB3_I2C_S_CMD
#define MUX_CTRL_SCB__I2C_STATUS CYREG_SCB3_I2C_STATUS
#define MUX_CTRL_SCB__INTR_CAUSE CYREG_SCB3_INTR_CAUSE
#define MUX_CTRL_SCB__INTR_I2C_EC CYREG_SCB3_INTR_I2C_EC
#define MUX_CTRL_SCB__INTR_I2C_EC_MASK CYREG_SCB3_INTR_I2C_EC_MASK
#define MUX_CTRL_SCB__INTR_I2C_EC_MASKED CYREG_SCB3_INTR_I2C_EC_MASKED
#define MUX_CTRL_SCB__INTR_M CYREG_SCB3_INTR_M
#define MUX_CTRL_SCB__INTR_M_MASK CYREG_SCB3_INTR_M_MASK
#define MUX_CTRL_SCB__INTR_M_MASKED CYREG_SCB3_INTR_M_MASKED
#define MUX_CTRL_SCB__INTR_M_SET CYREG_SCB3_INTR_M_SET
#define MUX_CTRL_SCB__INTR_RX CYREG_SCB3_INTR_RX
#define MUX_CTRL_SCB__INTR_RX_MASK CYREG_SCB3_INTR_RX_MASK
#define MUX_CTRL_SCB__INTR_RX_MASKED CYREG_SCB3_INTR_RX_MASKED
#define MUX_CTRL_SCB__INTR_RX_SET CYREG_SCB3_INTR_RX_SET
#define MUX_CTRL_SCB__INTR_S CYREG_SCB3_INTR_S
#define MUX_CTRL_SCB__INTR_S_MASK CYREG_SCB3_INTR_S_MASK
#define MUX_CTRL_SCB__INTR_S_MASKED CYREG_SCB3_INTR_S_MASKED
#define MUX_CTRL_SCB__INTR_S_SET CYREG_SCB3_INTR_S_SET
#define MUX_CTRL_SCB__INTR_SPI_EC CYREG_SCB3_INTR_SPI_EC
#define MUX_CTRL_SCB__INTR_SPI_EC_MASK CYREG_SCB3_INTR_SPI_EC_MASK
#define MUX_CTRL_SCB__INTR_SPI_EC_MASKED CYREG_SCB3_INTR_SPI_EC_MASKED
#define MUX_CTRL_SCB__INTR_TX CYREG_SCB3_INTR_TX
#define MUX_CTRL_SCB__INTR_TX_MASK CYREG_SCB3_INTR_TX_MASK
#define MUX_CTRL_SCB__INTR_TX_MASKED CYREG_SCB3_INTR_TX_MASKED
#define MUX_CTRL_SCB__INTR_TX_SET CYREG_SCB3_INTR_TX_SET
#define MUX_CTRL_SCB__RX_CTRL CYREG_SCB3_RX_CTRL
#define MUX_CTRL_SCB__RX_FIFO_CTRL CYREG_SCB3_RX_FIFO_CTRL
#define MUX_CTRL_SCB__RX_FIFO_RD CYREG_SCB3_RX_FIFO_RD
#define MUX_CTRL_SCB__RX_FIFO_RD_SILENT CYREG_SCB3_RX_FIFO_RD_SILENT
#define MUX_CTRL_SCB__RX_FIFO_STATUS CYREG_SCB3_RX_FIFO_STATUS
#define MUX_CTRL_SCB__RX_MATCH CYREG_SCB3_RX_MATCH
#define MUX_CTRL_SCB__SPI_CTRL CYREG_SCB3_SPI_CTRL
#define MUX_CTRL_SCB__SPI_STATUS CYREG_SCB3_SPI_STATUS
#define MUX_CTRL_SCB__SS0_POSISTION 0u
#define MUX_CTRL_SCB__SS1_POSISTION 1u
#define MUX_CTRL_SCB__SS2_POSISTION 2u
#define MUX_CTRL_SCB__SS3_POSISTION 3u
#define MUX_CTRL_SCB__STATUS CYREG_SCB3_STATUS
#define MUX_CTRL_SCB__TX_CTRL CYREG_SCB3_TX_CTRL
#define MUX_CTRL_SCB__TX_FIFO_CTRL CYREG_SCB3_TX_FIFO_CTRL
#define MUX_CTRL_SCB__TX_FIFO_STATUS CYREG_SCB3_TX_FIFO_STATUS
#define MUX_CTRL_SCB__TX_FIFO_WR CYREG_SCB3_TX_FIFO_WR
#define MUX_CTRL_SCB__UART_CTRL CYREG_SCB3_UART_CTRL
#define MUX_CTRL_SCB__UART_FLOW_CTRL CYREG_SCB3_UART_FLOW_CTRL
#define MUX_CTRL_SCB__UART_RX_CTRL CYREG_SCB3_UART_RX_CTRL
#define MUX_CTRL_SCB__UART_RX_STATUS CYREG_SCB3_UART_RX_STATUS
#define MUX_CTRL_SCB__UART_TX_CTRL CYREG_SCB3_UART_TX_CTRL

/* MUX_CTRL_SCB_IRQ */
#define MUX_CTRL_SCB_IRQ__INTC_CLR_EN_REG CYREG_CM0_ICER
#define MUX_CTRL_SCB_IRQ__INTC_CLR_PD_REG CYREG_CM0_ICPR
#define MUX_CTRL_SCB_IRQ__INTC_MASK 0x800u
#define MUX_CTRL_SCB_IRQ__INTC_NUMBER 11u
#define MUX_CTRL_SCB_IRQ__INTC_PRIOR_MASK 0xC0000000u
#define MUX_CTRL_SCB_IRQ__INTC_PRIOR_NUM 3u
#define MUX_CTRL_SCB_IRQ__INTC_PRIOR_REG CYREG_CM0_IPR2
#define MUX_CTRL_SCB_IRQ__INTC_SET_EN_REG CYREG_CM0_ISER
#define MUX_CTRL_SCB_IRQ__INTC_SET_PD_REG CYREG_CM0_ISPR

/* MUX_CTRL_SCBCLK */
#define MUX_CTRL_SCBCLK__CTRL_REGISTER CYREG_PERI_PCLK_CTL3
#define MUX_CTRL_SCBCLK__DIV_ID 0x00000003u
#define MUX_CTRL_SCBCLK__DIV_REGISTER CYREG_PERI_DIV_8_CTL3
#define MUX_CTRL_SCBCLK__PA_DIV_ID 0x000000FFu

/* MUX_CTRL_scl */
#define MUX_CTRL_scl__0__DR CYREG_GPIO_PRT1_DR
#define MUX_CTRL_scl__0__DR_CLR CYREG_GPIO_PRT1_DR_CLR
#define MUX_CTRL_scl__0__DR_INV CYREG_GPIO_PRT1_DR_INV
#define MUX_CTRL_scl__0__DR_SET CYREG_GPIO_PRT1_DR_SET
#define MUX_CTRL_scl__0__HSIOM CYREG_HSIOM_PORT_SEL1
#define MUX_CTRL_scl__0__HSIOM_GPIO 0u
#define MUX_CTRL_scl__0__HSIOM_I2C 15u
#define MUX_CTRL_scl__0__HSIOM_I2C_SCL 15u
#define MUX_CTRL_scl__0__HSIOM_MASK 0x00000F00u
#define MUX_CTRL_scl__0__HSIOM_SHIFT 8u
#define MUX_CTRL_scl__0__HSIOM_SPI 14u
#define MUX_CTRL_scl__0__HSIOM_SPI_MOSI 14u
#define MUX_CTRL_scl__0__HSIOM_UART 10u
#define MUX_CTRL_scl__0__HSIOM_UART_CTS 10u
#define MUX_CTRL_scl__0__INTCFG CYREG_GPIO_PRT1_INTR_CFG
#define MUX_CTRL_scl__0__INTR CYREG_GPIO_PRT1_INTR
#define MUX_CTRL_scl__0__INTR_CFG CYREG_GPIO_PRT1_INTR_CFG
#define MUX_CTRL_scl__0__INTSTAT CYREG_GPIO_PRT1_INTR
#define MUX_CTRL_scl__0__MASK 0x04u
#define MUX_CTRL_scl__0__PC CYREG_GPIO_PRT1_PC
#define MUX_CTRL_scl__0__PC2 CYREG_GPIO_PRT1_PC2
#define MUX_CTRL_scl__0__PORT 1u
#define MUX_CTRL_scl__0__PS CYREG_GPIO_PRT1_PS
#define MUX_CTRL_scl__0__SHIFT 2u
#define MUX_CTRL_scl__DR CYREG_GPIO_PRT1_DR
#define MUX_CTRL_scl__DR_CLR CYREG_GPIO_PRT1_DR_CLR
#define MUX_CTRL_scl__DR_INV CYREG_GPIO_PRT1_DR_INV
#define MUX_CTRL_scl__DR_SET CYREG_GPIO_PRT1_DR_SET
#define MUX_CTRL_scl__INTCFG CYREG_GPIO_PRT1_INTR_CFG
#define MUX_CTRL_scl__INTR CYREG_GPIO_PRT1_INTR
#define MUX_CTRL_scl__INTR_CFG CYREG_GPIO_PRT1_INTR_CFG
#define MUX_CTRL_scl__INTSTAT CYREG_GPIO_PRT1_INTR
#define MUX_CTRL_scl__MASK 0x04u
#define MUX_CTRL_scl__PC CYREG_GPIO_PRT1_PC
#define MUX_CTRL_scl__PC2 CYREG_GPIO_PRT1_PC2
#define MUX_CTRL_scl__PORT 1u
#define MUX_CTRL_scl__PS CYREG_GPIO_PRT1_PS
#define MUX_CTRL_scl__SHIFT 2u

/* MUX_CTRL_sda */
#define MUX_CTRL_sda__0__DR CYREG_GPIO_PRT1_DR
#define MUX_CTRL_sda__0__DR_CLR CYREG_GPIO_PRT1_DR_CLR
#define MUX_CTRL_sda__0__DR_INV CYREG_GPIO_PRT1_DR_INV
#define MUX_CTRL_sda__0__DR_SET CYREG_GPIO_PRT1_DR_SET
#define MUX_CTRL_sda__0__HSIOM CYREG_HSIOM_PORT_SEL1
#define MUX_CTRL_sda__0__HSIOM_GPIO 0u
#define MUX_CTRL_sda__0__HSIOM_I2C 15u
#define MUX_CTRL_sda__0__HSIOM_I2C_SDA 15u
#define MUX_CTRL_sda__0__HSIOM_MASK 0x0000F000u
#define MUX_CTRL_sda__0__HSIOM_SHIFT 12u
#define MUX_CTRL_sda__0__HSIOM_SPI 14u
#define MUX_CTRL_sda__0__HSIOM_SPI_CLK 14u
#define MUX_CTRL_sda__0__HSIOM_UART 10u
#define MUX_CTRL_sda__0__HSIOM_UART_RTS 10u
#define MUX_CTRL_sda__0__INTCFG CYREG_GPIO_PRT1_INTR_CFG
#define MUX_CTRL_sda__0__INTR CYREG_GPIO_PRT1_INTR
#define MUX_CTRL_sda__0__INTR_CFG CYREG_GPIO_PRT1_INTR_CFG
#define MUX_CTRL_sda__0__INTSTAT CYREG_GPIO_PRT1_INTR
#define MUX_CTRL_sda__0__MASK 0x08u
#define MUX_CTRL_sda__0__PC CYREG_GPIO_PRT1_PC
#define MUX_CTRL_sda__0__PC2 CYREG_GPIO_PRT1_PC2
#define MUX_CTRL_sda__0__PORT 1u
#define MUX_CTRL_sda__0__PS CYREG_GPIO_PRT1_PS
#define MUX_CTRL_sda__0__SHIFT 3u
#define MUX_CTRL_sda__DR CYREG_GPIO_PRT1_DR
#define MUX_CTRL_sda__DR_CLR CYREG_GPIO_PRT1_DR_CLR
#define MUX_CTRL_sda__DR_INV CYREG_GPIO_PRT1_DR_INV
#define MUX_CTRL_sda__DR_SET CYREG_GPIO_PRT1_DR_SET
#define MUX_CTRL_sda__INTCFG CYREG_GPIO_PRT1_INTR_CFG
#define MUX_CTRL_sda__INTR CYREG_GPIO_PRT1_INTR
#define MUX_CTRL_sda__INTR_CFG CYREG_GPIO_PRT1_INTR_CFG
#define MUX_CTRL_sda__INTSTAT CYREG_GPIO_PRT1_INTR
#define MUX_CTRL_sda__MASK 0x08u
#define MUX_CTRL_sda__PC CYREG_GPIO_PRT1_PC
#define MUX_CTRL_sda__PC2 CYREG_GPIO_PRT1_PC2
#define MUX_CTRL_sda__PORT 1u
#define MUX_CTRL_sda__PS CYREG_GPIO_PRT1_PS
#define MUX_CTRL_sda__SHIFT 3u

/* VSEL1_P1 */
#define VSEL1_P1__0__DR CYREG_GPIO_PRT0_DR
#define VSEL1_P1__0__DR_CLR CYREG_GPIO_PRT0_DR_CLR
#define VSEL1_P1__0__DR_INV CYREG_GPIO_PRT0_DR_INV
#define VSEL1_P1__0__DR_SET CYREG_GPIO_PRT0_DR_SET
#define VSEL1_P1__0__HSIOM CYREG_HSIOM_PORT_SEL0
#define VSEL1_P1__0__HSIOM_MASK 0x000000F0u
#define VSEL1_P1__0__HSIOM_SHIFT 4u
#define VSEL1_P1__0__INTCFG CYREG_GPIO_PRT0_INTR_CFG
#define VSEL1_P1__0__INTR CYREG_GPIO_PRT0_INTR
#define VSEL1_P1__0__INTR_CFG CYREG_GPIO_PRT0_INTR_CFG
#define VSEL1_P1__0__INTSTAT CYREG_GPIO_PRT0_INTR
#define VSEL1_P1__0__MASK 0x02u
#define VSEL1_P1__0__PC CYREG_GPIO_PRT0_PC
#define VSEL1_P1__0__PC2 CYREG_GPIO_PRT0_PC2
#define VSEL1_P1__0__PORT 0u
#define VSEL1_P1__0__PS CYREG_GPIO_PRT0_PS
#define VSEL1_P1__0__SHIFT 1u
#define VSEL1_P1__DR CYREG_GPIO_PRT0_DR
#define VSEL1_P1__DR_CLR CYREG_GPIO_PRT0_DR_CLR
#define VSEL1_P1__DR_INV CYREG_GPIO_PRT0_DR_INV
#define VSEL1_P1__DR_SET CYREG_GPIO_PRT0_DR_SET
#define VSEL1_P1__INTCFG CYREG_GPIO_PRT0_INTR_CFG
#define VSEL1_P1__INTR CYREG_GPIO_PRT0_INTR
#define VSEL1_P1__INTR_CFG CYREG_GPIO_PRT0_INTR_CFG
#define VSEL1_P1__INTSTAT CYREG_GPIO_PRT0_INTR
#define VSEL1_P1__MASK 0x02u
#define VSEL1_P1__PC CYREG_GPIO_PRT0_PC
#define VSEL1_P1__PC2 CYREG_GPIO_PRT0_PC2
#define VSEL1_P1__PORT 0u
#define VSEL1_P1__PS CYREG_GPIO_PRT0_PS
#define VSEL1_P1__SHIFT 1u

/* VSEL2_P1 */
#define VSEL2_P1__0__DR CYREG_GPIO_PRT0_DR
#define VSEL2_P1__0__DR_CLR CYREG_GPIO_PRT0_DR_CLR
#define VSEL2_P1__0__DR_INV CYREG_GPIO_PRT0_DR_INV
#define VSEL2_P1__0__DR_SET CYREG_GPIO_PRT0_DR_SET
#define VSEL2_P1__0__HSIOM CYREG_HSIOM_PORT_SEL0
#define VSEL2_P1__0__HSIOM_MASK 0x0000000Fu
#define VSEL2_P1__0__HSIOM_SHIFT 0u
#define VSEL2_P1__0__INTCFG CYREG_GPIO_PRT0_INTR_CFG
#define VSEL2_P1__0__INTR CYREG_GPIO_PRT0_INTR
#define VSEL2_P1__0__INTR_CFG CYREG_GPIO_PRT0_INTR_CFG
#define VSEL2_P1__0__INTSTAT CYREG_GPIO_PRT0_INTR
#define VSEL2_P1__0__MASK 0x01u
#define VSEL2_P1__0__PC CYREG_GPIO_PRT0_PC
#define VSEL2_P1__0__PC2 CYREG_GPIO_PRT0_PC2
#define VSEL2_P1__0__PORT 0u
#define VSEL2_P1__0__PS CYREG_GPIO_PRT0_PS
#define VSEL2_P1__0__SHIFT 0u
#define VSEL2_P1__DR CYREG_GPIO_PRT0_DR
#define VSEL2_P1__DR_CLR CYREG_GPIO_PRT0_DR_CLR
#define VSEL2_P1__DR_INV CYREG_GPIO_PRT0_DR_INV
#define VSEL2_P1__DR_SET CYREG_GPIO_PRT0_DR_SET
#define VSEL2_P1__INTCFG CYREG_GPIO_PRT0_INTR_CFG
#define VSEL2_P1__INTR CYREG_GPIO_PRT0_INTR
#define VSEL2_P1__INTR_CFG CYREG_GPIO_PRT0_INTR_CFG
#define VSEL2_P1__INTSTAT CYREG_GPIO_PRT0_INTR
#define VSEL2_P1__MASK 0x01u
#define VSEL2_P1__PC CYREG_GPIO_PRT0_PC
#define VSEL2_P1__PC2 CYREG_GPIO_PRT0_PC2
#define VSEL2_P1__PORT 0u
#define VSEL2_P1__PS CYREG_GPIO_PRT0_PS
#define VSEL2_P1__SHIFT 0u

/* PGOOD_LED */
#define PGOOD_LED__0__DR CYREG_GPIO_PRT2_DR
#define PGOOD_LED__0__DR_CLR CYREG_GPIO_PRT2_DR_CLR
#define PGOOD_LED__0__DR_INV CYREG_GPIO_PRT2_DR_INV
#define PGOOD_LED__0__DR_SET CYREG_GPIO_PRT2_DR_SET
#define PGOOD_LED__0__HSIOM CYREG_HSIOM_PORT_SEL2
#define PGOOD_LED__0__HSIOM_MASK 0x000F0000u
#define PGOOD_LED__0__HSIOM_SHIFT 16u
#define PGOOD_LED__0__INTCFG CYREG_GPIO_PRT2_INTR_CFG
#define PGOOD_LED__0__INTR CYREG_GPIO_PRT2_INTR
#define PGOOD_LED__0__INTR_CFG CYREG_GPIO_PRT2_INTR_CFG
#define PGOOD_LED__0__INTSTAT CYREG_GPIO_PRT2_INTR
#define PGOOD_LED__0__MASK 0x10u
#define PGOOD_LED__0__PC CYREG_GPIO_PRT2_PC
#define PGOOD_LED__0__PC2 CYREG_GPIO_PRT2_PC2
#define PGOOD_LED__0__PORT 2u
#define PGOOD_LED__0__PS CYREG_GPIO_PRT2_PS
#define PGOOD_LED__0__SHIFT 4u
#define PGOOD_LED__DR CYREG_GPIO_PRT2_DR
#define PGOOD_LED__DR_CLR CYREG_GPIO_PRT2_DR_CLR
#define PGOOD_LED__DR_INV CYREG_GPIO_PRT2_DR_INV
#define PGOOD_LED__DR_SET CYREG_GPIO_PRT2_DR_SET
#define PGOOD_LED__INTCFG CYREG_GPIO_PRT2_INTR_CFG
#define PGOOD_LED__INTR CYREG_GPIO_PRT2_INTR
#define PGOOD_LED__INTR_CFG CYREG_GPIO_PRT2_INTR_CFG
#define PGOOD_LED__INTSTAT CYREG_GPIO_PRT2_INTR
#define PGOOD_LED__MASK 0x10u
#define PGOOD_LED__PC CYREG_GPIO_PRT2_PC
#define PGOOD_LED__PC2 CYREG_GPIO_PRT2_PC2
#define PGOOD_LED__PORT 2u
#define PGOOD_LED__PS CYREG_GPIO_PRT2_PS
#define PGOOD_LED__SHIFT 4u

/* SMBALERTB */
#define SMBALERTB__0__DR CYREG_GPIO_PRT3_DR
#define SMBALERTB__0__DR_CLR CYREG_GPIO_PRT3_DR_CLR
#define SMBALERTB__0__DR_INV CYREG_GPIO_PRT3_DR_INV
#define SMBALERTB__0__DR_SET CYREG_GPIO_PRT3_DR_SET
#define SMBALERTB__0__HSIOM CYREG_HSIOM_PORT_SEL3
#define SMBALERTB__0__HSIOM_MASK 0x0F000000u
#define SMBALERTB__0__HSIOM_SHIFT 24u
#define SMBALERTB__0__INTCFG CYREG_GPIO_PRT3_INTR_CFG
#define SMBALERTB__0__INTR CYREG_GPIO_PRT3_INTR
#define SMBALERTB__0__INTR_CFG CYREG_GPIO_PRT3_INTR_CFG
#define SMBALERTB__0__INTSTAT CYREG_GPIO_PRT3_INTR
#define SMBALERTB__0__MASK 0x40u
#define SMBALERTB__0__PC CYREG_GPIO_PRT3_PC
#define SMBALERTB__0__PC2 CYREG_GPIO_PRT3_PC2
#define SMBALERTB__0__PORT 3u
#define SMBALERTB__0__PS CYREG_GPIO_PRT3_PS
#define SMBALERTB__0__SHIFT 6u
#define SMBALERTB__DR CYREG_GPIO_PRT3_DR
#define SMBALERTB__DR_CLR CYREG_GPIO_PRT3_DR_CLR
#define SMBALERTB__DR_INV CYREG_GPIO_PRT3_DR_INV
#define SMBALERTB__DR_SET CYREG_GPIO_PRT3_DR_SET
#define SMBALERTB__INTCFG CYREG_GPIO_PRT3_INTR_CFG
#define SMBALERTB__INTR CYREG_GPIO_PRT3_INTR
#define SMBALERTB__INTR_CFG CYREG_GPIO_PRT3_INTR_CFG
#define SMBALERTB__INTSTAT CYREG_GPIO_PRT3_INTR
#define SMBALERTB__MASK 0x40u
#define SMBALERTB__PC CYREG_GPIO_PRT3_PC
#define SMBALERTB__PC2 CYREG_GPIO_PRT3_PC2
#define SMBALERTB__PORT 3u
#define SMBALERTB__PS CYREG_GPIO_PRT3_PS
#define SMBALERTB__SHIFT 6u

/* I2C_master_SCB */
#define I2C_master_SCB__CMD_RESP_CTRL CYREG_SCB2_CMD_RESP_CTRL
#define I2C_master_SCB__CMD_RESP_STATUS CYREG_SCB2_CMD_RESP_STATUS
#define I2C_master_SCB__CTRL CYREG_SCB2_CTRL
#define I2C_master_SCB__EZ_DATA0 CYREG_SCB2_EZ_DATA0
#define I2C_master_SCB__EZ_DATA1 CYREG_SCB2_EZ_DATA1
#define I2C_master_SCB__EZ_DATA10 CYREG_SCB2_EZ_DATA10
#define I2C_master_SCB__EZ_DATA100 CYREG_SCB2_EZ_DATA100
#define I2C_master_SCB__EZ_DATA101 CYREG_SCB2_EZ_DATA101
#define I2C_master_SCB__EZ_DATA102 CYREG_SCB2_EZ_DATA102
#define I2C_master_SCB__EZ_DATA103 CYREG_SCB2_EZ_DATA103
#define I2C_master_SCB__EZ_DATA104 CYREG_SCB2_EZ_DATA104
#define I2C_master_SCB__EZ_DATA105 CYREG_SCB2_EZ_DATA105
#define I2C_master_SCB__EZ_DATA106 CYREG_SCB2_EZ_DATA106
#define I2C_master_SCB__EZ_DATA107 CYREG_SCB2_EZ_DATA107
#define I2C_master_SCB__EZ_DATA108 CYREG_SCB2_EZ_DATA108
#define I2C_master_SCB__EZ_DATA109 CYREG_SCB2_EZ_DATA109
#define I2C_master_SCB__EZ_DATA11 CYREG_SCB2_EZ_DATA11
#define I2C_master_SCB__EZ_DATA110 CYREG_SCB2_EZ_DATA110
#define I2C_master_SCB__EZ_DATA111 CYREG_SCB2_EZ_DATA111
#define I2C_master_SCB__EZ_DATA112 CYREG_SCB2_EZ_DATA112
#define I2C_master_SCB__EZ_DATA113 CYREG_SCB2_EZ_DATA113
#define I2C_master_SCB__EZ_DATA114 CYREG_SCB2_EZ_DATA114
#define I2C_master_SCB__EZ_DATA115 CYREG_SCB2_EZ_DATA115
#define I2C_master_SCB__EZ_DATA116 CYREG_SCB2_EZ_DATA116
#define I2C_master_SCB__EZ_DATA117 CYREG_SCB2_EZ_DATA117
#define I2C_master_SCB__EZ_DATA118 CYREG_SCB2_EZ_DATA118
#define I2C_master_SCB__EZ_DATA119 CYREG_SCB2_EZ_DATA119
#define I2C_master_SCB__EZ_DATA12 CYREG_SCB2_EZ_DATA12
#define I2C_master_SCB__EZ_DATA120 CYREG_SCB2_EZ_DATA120
#define I2C_master_SCB__EZ_DATA121 CYREG_SCB2_EZ_DATA121
#define I2C_master_SCB__EZ_DATA122 CYREG_SCB2_EZ_DATA122
#define I2C_master_SCB__EZ_DATA123 CYREG_SCB2_EZ_DATA123
#define I2C_master_SCB__EZ_DATA124 CYREG_SCB2_EZ_DATA124
#define I2C_master_SCB__EZ_DATA125 CYREG_SCB2_EZ_DATA125
#define I2C_master_SCB__EZ_DATA126 CYREG_SCB2_EZ_DATA126
#define I2C_master_SCB__EZ_DATA127 CYREG_SCB2_EZ_DATA127
#define I2C_master_SCB__EZ_DATA128 CYREG_SCB2_EZ_DATA128
#define I2C_master_SCB__EZ_DATA129 CYREG_SCB2_EZ_DATA129
#define I2C_master_SCB__EZ_DATA13 CYREG_SCB2_EZ_DATA13
#define I2C_master_SCB__EZ_DATA130 CYREG_SCB2_EZ_DATA130
#define I2C_master_SCB__EZ_DATA131 CYREG_SCB2_EZ_DATA131
#define I2C_master_SCB__EZ_DATA132 CYREG_SCB2_EZ_DATA132
#define I2C_master_SCB__EZ_DATA133 CYREG_SCB2_EZ_DATA133
#define I2C_master_SCB__EZ_DATA134 CYREG_SCB2_EZ_DATA134
#define I2C_master_SCB__EZ_DATA135 CYREG_SCB2_EZ_DATA135
#define I2C_master_SCB__EZ_DATA136 CYREG_SCB2_EZ_DATA136
#define I2C_master_SCB__EZ_DATA137 CYREG_SCB2_EZ_DATA137
#define I2C_master_SCB__EZ_DATA138 CYREG_SCB2_EZ_DATA138
#define I2C_master_SCB__EZ_DATA139 CYREG_SCB2_EZ_DATA139
#define I2C_master_SCB__EZ_DATA14 CYREG_SCB2_EZ_DATA14
#define I2C_master_SCB__EZ_DATA140 CYREG_SCB2_EZ_DATA140
#define I2C_master_SCB__EZ_DATA141 CYREG_SCB2_EZ_DATA141
#define I2C_master_SCB__EZ_DATA142 CYREG_SCB2_EZ_DATA142
#define I2C_master_SCB__EZ_DATA143 CYREG_SCB2_EZ_DATA143
#define I2C_master_SCB__EZ_DATA144 CYREG_SCB2_EZ_DATA144
#define I2C_master_SCB__EZ_DATA145 CYREG_SCB2_EZ_DATA145
#define I2C_master_SCB__EZ_DATA146 CYREG_SCB2_EZ_DATA146
#define I2C_master_SCB__EZ_DATA147 CYREG_SCB2_EZ_DATA147
#define I2C_master_SCB__EZ_DATA148 CYREG_SCB2_EZ_DATA148
#define I2C_master_SCB__EZ_DATA149 CYREG_SCB2_EZ_DATA149
#define I2C_master_SCB__EZ_DATA15 CYREG_SCB2_EZ_DATA15
#define I2C_master_SCB__EZ_DATA150 CYREG_SCB2_EZ_DATA150
#define I2C_master_SCB__EZ_DATA151 CYREG_SCB2_EZ_DATA151
#define I2C_master_SCB__EZ_DATA152 CYREG_SCB2_EZ_DATA152
#define I2C_master_SCB__EZ_DATA153 CYREG_SCB2_EZ_DATA153
#define I2C_master_SCB__EZ_DATA154 CYREG_SCB2_EZ_DATA154
#define I2C_master_SCB__EZ_DATA155 CYREG_SCB2_EZ_DATA155
#define I2C_master_SCB__EZ_DATA156 CYREG_SCB2_EZ_DATA156
#define I2C_master_SCB__EZ_DATA157 CYREG_SCB2_EZ_DATA157
#define I2C_master_SCB__EZ_DATA158 CYREG_SCB2_EZ_DATA158
#define I2C_master_SCB__EZ_DATA159 CYREG_SCB2_EZ_DATA159
#define I2C_master_SCB__EZ_DATA16 CYREG_SCB2_EZ_DATA16
#define I2C_master_SCB__EZ_DATA160 CYREG_SCB2_EZ_DATA160
#define I2C_master_SCB__EZ_DATA161 CYREG_SCB2_EZ_DATA161
#define I2C_master_SCB__EZ_DATA162 CYREG_SCB2_EZ_DATA162
#define I2C_master_SCB__EZ_DATA163 CYREG_SCB2_EZ_DATA163
#define I2C_master_SCB__EZ_DATA164 CYREG_SCB2_EZ_DATA164
#define I2C_master_SCB__EZ_DATA165 CYREG_SCB2_EZ_DATA165
#define I2C_master_SCB__EZ_DATA166 CYREG_SCB2_EZ_DATA166
#define I2C_master_SCB__EZ_DATA167 CYREG_SCB2_EZ_DATA167
#define I2C_master_SCB__EZ_DATA168 CYREG_SCB2_EZ_DATA168
#define I2C_master_SCB__EZ_DATA169 CYREG_SCB2_EZ_DATA169
#define I2C_master_SCB__EZ_DATA17 CYREG_SCB2_EZ_DATA17
#define I2C_master_SCB__EZ_DATA170 CYREG_SCB2_EZ_DATA170
#define I2C_master_SCB__EZ_DATA171 CYREG_SCB2_EZ_DATA171
#define I2C_master_SCB__EZ_DATA172 CYREG_SCB2_EZ_DATA172
#define I2C_master_SCB__EZ_DATA173 CYREG_SCB2_EZ_DATA173
#define I2C_master_SCB__EZ_DATA174 CYREG_SCB2_EZ_DATA174
#define I2C_master_SCB__EZ_DATA175 CYREG_SCB2_EZ_DATA175
#define I2C_master_SCB__EZ_DATA176 CYREG_SCB2_EZ_DATA176
#define I2C_master_SCB__EZ_DATA177 CYREG_SCB2_EZ_DATA177
#define I2C_master_SCB__EZ_DATA178 CYREG_SCB2_EZ_DATA178
#define I2C_master_SCB__EZ_DATA179 CYREG_SCB2_EZ_DATA179
#define I2C_master_SCB__EZ_DATA18 CYREG_SCB2_EZ_DATA18
#define I2C_master_SCB__EZ_DATA180 CYREG_SCB2_EZ_DATA180
#define I2C_master_SCB__EZ_DATA181 CYREG_SCB2_EZ_DATA181
#define I2C_master_SCB__EZ_DATA182 CYREG_SCB2_EZ_DATA182
#define I2C_master_SCB__EZ_DATA183 CYREG_SCB2_EZ_DATA183
#define I2C_master_SCB__EZ_DATA184 CYREG_SCB2_EZ_DATA184
#define I2C_master_SCB__EZ_DATA185 CYREG_SCB2_EZ_DATA185
#define I2C_master_SCB__EZ_DATA186 CYREG_SCB2_EZ_DATA186
#define I2C_master_SCB__EZ_DATA187 CYREG_SCB2_EZ_DATA187
#define I2C_master_SCB__EZ_DATA188 CYREG_SCB2_EZ_DATA188
#define I2C_master_SCB__EZ_DATA189 CYREG_SCB2_EZ_DATA189
#define I2C_master_SCB__EZ_DATA19 CYREG_SCB2_EZ_DATA19
#define I2C_master_SCB__EZ_DATA190 CYREG_SCB2_EZ_DATA190
#define I2C_master_SCB__EZ_DATA191 CYREG_SCB2_EZ_DATA191
#define I2C_master_SCB__EZ_DATA192 CYREG_SCB2_EZ_DATA192
#define I2C_master_SCB__EZ_DATA193 CYREG_SCB2_EZ_DATA193
#define I2C_master_SCB__EZ_DATA194 CYREG_SCB2_EZ_DATA194
#define I2C_master_SCB__EZ_DATA195 CYREG_SCB2_EZ_DATA195
#define I2C_master_SCB__EZ_DATA196 CYREG_SCB2_EZ_DATA196
#define I2C_master_SCB__EZ_DATA197 CYREG_SCB2_EZ_DATA197
#define I2C_master_SCB__EZ_DATA198 CYREG_SCB2_EZ_DATA198
#define I2C_master_SCB__EZ_DATA199 CYREG_SCB2_EZ_DATA199
#define I2C_master_SCB__EZ_DATA2 CYREG_SCB2_EZ_DATA2
#define I2C_master_SCB__EZ_DATA20 CYREG_SCB2_EZ_DATA20
#define I2C_master_SCB__EZ_DATA200 CYREG_SCB2_EZ_DATA200
#define I2C_master_SCB__EZ_DATA201 CYREG_SCB2_EZ_DATA201
#define I2C_master_SCB__EZ_DATA202 CYREG_SCB2_EZ_DATA202
#define I2C_master_SCB__EZ_DATA203 CYREG_SCB2_EZ_DATA203
#define I2C_master_SCB__EZ_DATA204 CYREG_SCB2_EZ_DATA204
#define I2C_master_SCB__EZ_DATA205 CYREG_SCB2_EZ_DATA205
#define I2C_master_SCB__EZ_DATA206 CYREG_SCB2_EZ_DATA206
#define I2C_master_SCB__EZ_DATA207 CYREG_SCB2_EZ_DATA207
#define I2C_master_SCB__EZ_DATA208 CYREG_SCB2_EZ_DATA208
#define I2C_master_SCB__EZ_DATA209 CYREG_SCB2_EZ_DATA209
#define I2C_master_SCB__EZ_DATA21 CYREG_SCB2_EZ_DATA21
#define I2C_master_SCB__EZ_DATA210 CYREG_SCB2_EZ_DATA210
#define I2C_master_SCB__EZ_DATA211 CYREG_SCB2_EZ_DATA211
#define I2C_master_SCB__EZ_DATA212 CYREG_SCB2_EZ_DATA212
#define I2C_master_SCB__EZ_DATA213 CYREG_SCB2_EZ_DATA213
#define I2C_master_SCB__EZ_DATA214 CYREG_SCB2_EZ_DATA214
#define I2C_master_SCB__EZ_DATA215 CYREG_SCB2_EZ_DATA215
#define I2C_master_SCB__EZ_DATA216 CYREG_SCB2_EZ_DATA216
#define I2C_master_SCB__EZ_DATA217 CYREG_SCB2_EZ_DATA217
#define I2C_master_SCB__EZ_DATA218 CYREG_SCB2_EZ_DATA218
#define I2C_master_SCB__EZ_DATA219 CYREG_SCB2_EZ_DATA219
#define I2C_master_SCB__EZ_DATA22 CYREG_SCB2_EZ_DATA22
#define I2C_master_SCB__EZ_DATA220 CYREG_SCB2_EZ_DATA220
#define I2C_master_SCB__EZ_DATA221 CYREG_SCB2_EZ_DATA221
#define I2C_master_SCB__EZ_DATA222 CYREG_SCB2_EZ_DATA222
#define I2C_master_SCB__EZ_DATA223 CYREG_SCB2_EZ_DATA223
#define I2C_master_SCB__EZ_DATA224 CYREG_SCB2_EZ_DATA224
#define I2C_master_SCB__EZ_DATA225 CYREG_SCB2_EZ_DATA225
#define I2C_master_SCB__EZ_DATA226 CYREG_SCB2_EZ_DATA226
#define I2C_master_SCB__EZ_DATA227 CYREG_SCB2_EZ_DATA227
#define I2C_master_SCB__EZ_DATA228 CYREG_SCB2_EZ_DATA228
#define I2C_master_SCB__EZ_DATA229 CYREG_SCB2_EZ_DATA229
#define I2C_master_SCB__EZ_DATA23 CYREG_SCB2_EZ_DATA23
#define I2C_master_SCB__EZ_DATA230 CYREG_SCB2_EZ_DATA230
#define I2C_master_SCB__EZ_DATA231 CYREG_SCB2_EZ_DATA231
#define I2C_master_SCB__EZ_DATA232 CYREG_SCB2_EZ_DATA232
#define I2C_master_SCB__EZ_DATA233 CYREG_SCB2_EZ_DATA233
#define I2C_master_SCB__EZ_DATA234 CYREG_SCB2_EZ_DATA234
#define I2C_master_SCB__EZ_DATA235 CYREG_SCB2_EZ_DATA235
#define I2C_master_SCB__EZ_DATA236 CYREG_SCB2_EZ_DATA236
#define I2C_master_SCB__EZ_DATA237 CYREG_SCB2_EZ_DATA237
#define I2C_master_SCB__EZ_DATA238 CYREG_SCB2_EZ_DATA238
#define I2C_master_SCB__EZ_DATA239 CYREG_SCB2_EZ_DATA239
#define I2C_master_SCB__EZ_DATA24 CYREG_SCB2_EZ_DATA24
#define I2C_master_SCB__EZ_DATA240 CYREG_SCB2_EZ_DATA240
#define I2C_master_SCB__EZ_DATA241 CYREG_SCB2_EZ_DATA241
#define I2C_master_SCB__EZ_DATA242 CYREG_SCB2_EZ_DATA242
#define I2C_master_SCB__EZ_DATA243 CYREG_SCB2_EZ_DATA243
#define I2C_master_SCB__EZ_DATA244 CYREG_SCB2_EZ_DATA244
#define I2C_master_SCB__EZ_DATA245 CYREG_SCB2_EZ_DATA245
#define I2C_master_SCB__EZ_DATA246 CYREG_SCB2_EZ_DATA246
#define I2C_master_SCB__EZ_DATA247 CYREG_SCB2_EZ_DATA247
#define I2C_master_SCB__EZ_DATA248 CYREG_SCB2_EZ_DATA248
#define I2C_master_SCB__EZ_DATA249 CYREG_SCB2_EZ_DATA249
#define I2C_master_SCB__EZ_DATA25 CYREG_SCB2_EZ_DATA25
#define I2C_master_SCB__EZ_DATA250 CYREG_SCB2_EZ_DATA250
#define I2C_master_SCB__EZ_DATA251 CYREG_SCB2_EZ_DATA251
#define I2C_master_SCB__EZ_DATA252 CYREG_SCB2_EZ_DATA252
#define I2C_master_SCB__EZ_DATA253 CYREG_SCB2_EZ_DATA253
#define I2C_master_SCB__EZ_DATA254 CYREG_SCB2_EZ_DATA254
#define I2C_master_SCB__EZ_DATA255 CYREG_SCB2_EZ_DATA255
#define I2C_master_SCB__EZ_DATA26 CYREG_SCB2_EZ_DATA26
#define I2C_master_SCB__EZ_DATA27 CYREG_SCB2_EZ_DATA27
#define I2C_master_SCB__EZ_DATA28 CYREG_SCB2_EZ_DATA28
#define I2C_master_SCB__EZ_DATA29 CYREG_SCB2_EZ_DATA29
#define I2C_master_SCB__EZ_DATA3 CYREG_SCB2_EZ_DATA3
#define I2C_master_SCB__EZ_DATA30 CYREG_SCB2_EZ_DATA30
#define I2C_master_SCB__EZ_DATA31 CYREG_SCB2_EZ_DATA31
#define I2C_master_SCB__EZ_DATA32 CYREG_SCB2_EZ_DATA32
#define I2C_master_SCB__EZ_DATA33 CYREG_SCB2_EZ_DATA33
#define I2C_master_SCB__EZ_DATA34 CYREG_SCB2_EZ_DATA34
#define I2C_master_SCB__EZ_DATA35 CYREG_SCB2_EZ_DATA35
#define I2C_master_SCB__EZ_DATA36 CYREG_SCB2_EZ_DATA36
#define I2C_master_SCB__EZ_DATA37 CYREG_SCB2_EZ_DATA37
#define I2C_master_SCB__EZ_DATA38 CYREG_SCB2_EZ_DATA38
#define I2C_master_SCB__EZ_DATA39 CYREG_SCB2_EZ_DATA39
#define I2C_master_SCB__EZ_DATA4 CYREG_SCB2_EZ_DATA4
#define I2C_master_SCB__EZ_DATA40 CYREG_SCB2_EZ_DATA40
#define I2C_master_SCB__EZ_DATA41 CYREG_SCB2_EZ_DATA41
#define I2C_master_SCB__EZ_DATA42 CYREG_SCB2_EZ_DATA42
#define I2C_master_SCB__EZ_DATA43 CYREG_SCB2_EZ_DATA43
#define I2C_master_SCB__EZ_DATA44 CYREG_SCB2_EZ_DATA44
#define I2C_master_SCB__EZ_DATA45 CYREG_SCB2_EZ_DATA45
#define I2C_master_SCB__EZ_DATA46 CYREG_SCB2_EZ_DATA46
#define I2C_master_SCB__EZ_DATA47 CYREG_SCB2_EZ_DATA47
#define I2C_master_SCB__EZ_DATA48 CYREG_SCB2_EZ_DATA48
#define I2C_master_SCB__EZ_DATA49 CYREG_SCB2_EZ_DATA49
#define I2C_master_SCB__EZ_DATA5 CYREG_SCB2_EZ_DATA5
#define I2C_master_SCB__EZ_DATA50 CYREG_SCB2_EZ_DATA50
#define I2C_master_SCB__EZ_DATA51 CYREG_SCB2_EZ_DATA51
#define I2C_master_SCB__EZ_DATA52 CYREG_SCB2_EZ_DATA52
#define I2C_master_SCB__EZ_DATA53 CYREG_SCB2_EZ_DATA53
#define I2C_master_SCB__EZ_DATA54 CYREG_SCB2_EZ_DATA54
#define I2C_master_SCB__EZ_DATA55 CYREG_SCB2_EZ_DATA55
#define I2C_master_SCB__EZ_DATA56 CYREG_SCB2_EZ_DATA56
#define I2C_master_SCB__EZ_DATA57 CYREG_SCB2_EZ_DATA57
#define I2C_master_SCB__EZ_DATA58 CYREG_SCB2_EZ_DATA58
#define I2C_master_SCB__EZ_DATA59 CYREG_SCB2_EZ_DATA59
#define I2C_master_SCB__EZ_DATA6 CYREG_SCB2_EZ_DATA6
#define I2C_master_SCB__EZ_DATA60 CYREG_SCB2_EZ_DATA60
#define I2C_master_SCB__EZ_DATA61 CYREG_SCB2_EZ_DATA61
#define I2C_master_SCB__EZ_DATA62 CYREG_SCB2_EZ_DATA62
#define I2C_master_SCB__EZ_DATA63 CYREG_SCB2_EZ_DATA63
#define I2C_master_SCB__EZ_DATA64 CYREG_SCB2_EZ_DATA64
#define I2C_master_SCB__EZ_DATA65 CYREG_SCB2_EZ_DATA65
#define I2C_master_SCB__EZ_DATA66 CYREG_SCB2_EZ_DATA66
#define I2C_master_SCB__EZ_DATA67 CYREG_SCB2_EZ_DATA67
#define I2C_master_SCB__EZ_DATA68 CYREG_SCB2_EZ_DATA68
#define I2C_master_SCB__EZ_DATA69 CYREG_SCB2_EZ_DATA69
#define I2C_master_SCB__EZ_DATA7 CYREG_SCB2_EZ_DATA7
#define I2C_master_SCB__EZ_DATA70 CYREG_SCB2_EZ_DATA70
#define I2C_master_SCB__EZ_DATA71 CYREG_SCB2_EZ_DATA71
#define I2C_master_SCB__EZ_DATA72 CYREG_SCB2_EZ_DATA72
#define I2C_master_SCB__EZ_DATA73 CYREG_SCB2_EZ_DATA73
#define I2C_master_SCB__EZ_DATA74 CYREG_SCB2_EZ_DATA74
#define I2C_master_SCB__EZ_DATA75 CYREG_SCB2_EZ_DATA75
#define I2C_master_SCB__EZ_DATA76 CYREG_SCB2_EZ_DATA76
#define I2C_master_SCB__EZ_DATA77 CYREG_SCB2_EZ_DATA77
#define I2C_master_SCB__EZ_DATA78 CYREG_SCB2_EZ_DATA78
#define I2C_master_SCB__EZ_DATA79 CYREG_SCB2_EZ_DATA79
#define I2C_master_SCB__EZ_DATA8 CYREG_SCB2_EZ_DATA8
#define I2C_master_SCB__EZ_DATA80 CYREG_SCB2_EZ_DATA80
#define I2C_master_SCB__EZ_DATA81 CYREG_SCB2_EZ_DATA81
#define I2C_master_SCB__EZ_DATA82 CYREG_SCB2_EZ_DATA82
#define I2C_master_SCB__EZ_DATA83 CYREG_SCB2_EZ_DATA83
#define I2C_master_SCB__EZ_DATA84 CYREG_SCB2_EZ_DATA84
#define I2C_master_SCB__EZ_DATA85 CYREG_SCB2_EZ_DATA85
#define I2C_master_SCB__EZ_DATA86 CYREG_SCB2_EZ_DATA86
#define I2C_master_SCB__EZ_DATA87 CYREG_SCB2_EZ_DATA87
#define I2C_master_SCB__EZ_DATA88 CYREG_SCB2_EZ_DATA88
#define I2C_master_SCB__EZ_DATA89 CYREG_SCB2_EZ_DATA89
#define I2C_master_SCB__EZ_DATA9 CYREG_SCB2_EZ_DATA9
#define I2C_master_SCB__EZ_DATA90 CYREG_SCB2_EZ_DATA90
#define I2C_master_SCB__EZ_DATA91 CYREG_SCB2_EZ_DATA91
#define I2C_master_SCB__EZ_DATA92 CYREG_SCB2_EZ_DATA92
#define I2C_master_SCB__EZ_DATA93 CYREG_SCB2_EZ_DATA93
#define I2C_master_SCB__EZ_DATA94 CYREG_SCB2_EZ_DATA94
#define I2C_master_SCB__EZ_DATA95 CYREG_SCB2_EZ_DATA95
#define I2C_master_SCB__EZ_DATA96 CYREG_SCB2_EZ_DATA96
#define I2C_master_SCB__EZ_DATA97 CYREG_SCB2_EZ_DATA97
#define I2C_master_SCB__EZ_DATA98 CYREG_SCB2_EZ_DATA98
#define I2C_master_SCB__EZ_DATA99 CYREG_SCB2_EZ_DATA99
#define I2C_master_SCB__I2C_CFG CYREG_SCB2_I2C_CFG
#define I2C_master_SCB__I2C_CTRL CYREG_SCB2_I2C_CTRL
#define I2C_master_SCB__I2C_M_CMD CYREG_SCB2_I2C_M_CMD
#define I2C_master_SCB__I2C_S_CMD CYREG_SCB2_I2C_S_CMD
#define I2C_master_SCB__I2C_STATUS CYREG_SCB2_I2C_STATUS
#define I2C_master_SCB__INTR_CAUSE CYREG_SCB2_INTR_CAUSE
#define I2C_master_SCB__INTR_I2C_EC CYREG_SCB2_INTR_I2C_EC
#define I2C_master_SCB__INTR_I2C_EC_MASK CYREG_SCB2_INTR_I2C_EC_MASK
#define I2C_master_SCB__INTR_I2C_EC_MASKED CYREG_SCB2_INTR_I2C_EC_MASKED
#define I2C_master_SCB__INTR_M CYREG_SCB2_INTR_M
#define I2C_master_SCB__INTR_M_MASK CYREG_SCB2_INTR_M_MASK
#define I2C_master_SCB__INTR_M_MASKED CYREG_SCB2_INTR_M_MASKED
#define I2C_master_SCB__INTR_M_SET CYREG_SCB2_INTR_M_SET
#define I2C_master_SCB__INTR_RX CYREG_SCB2_INTR_RX
#define I2C_master_SCB__INTR_RX_MASK CYREG_SCB2_INTR_RX_MASK
#define I2C_master_SCB__INTR_RX_MASKED CYREG_SCB2_INTR_RX_MASKED
#define I2C_master_SCB__INTR_RX_SET CYREG_SCB2_INTR_RX_SET
#define I2C_master_SCB__INTR_S CYREG_SCB2_INTR_S
#define I2C_master_SCB__INTR_S_MASK CYREG_SCB2_INTR_S_MASK
#define I2C_master_SCB__INTR_S_MASKED CYREG_SCB2_INTR_S_MASKED
#define I2C_master_SCB__INTR_S_SET CYREG_SCB2_INTR_S_SET
#define I2C_master_SCB__INTR_SPI_EC CYREG_SCB2_INTR_SPI_EC
#define I2C_master_SCB__INTR_SPI_EC_MASK CYREG_SCB2_INTR_SPI_EC_MASK
#define I2C_master_SCB__INTR_SPI_EC_MASKED CYREG_SCB2_INTR_SPI_EC_MASKED
#define I2C_master_SCB__INTR_TX CYREG_SCB2_INTR_TX
#define I2C_master_SCB__INTR_TX_MASK CYREG_SCB2_INTR_TX_MASK
#define I2C_master_SCB__INTR_TX_MASKED CYREG_SCB2_INTR_TX_MASKED
#define I2C_master_SCB__INTR_TX_SET CYREG_SCB2_INTR_TX_SET
#define I2C_master_SCB__RX_CTRL CYREG_SCB2_RX_CTRL
#define I2C_master_SCB__RX_FIFO_CTRL CYREG_SCB2_RX_FIFO_CTRL
#define I2C_master_SCB__RX_FIFO_RD CYREG_SCB2_RX_FIFO_RD
#define I2C_master_SCB__RX_FIFO_RD_SILENT CYREG_SCB2_RX_FIFO_RD_SILENT
#define I2C_master_SCB__RX_FIFO_STATUS CYREG_SCB2_RX_FIFO_STATUS
#define I2C_master_SCB__RX_MATCH CYREG_SCB2_RX_MATCH
#define I2C_master_SCB__SPI_CTRL CYREG_SCB2_SPI_CTRL
#define I2C_master_SCB__SPI_STATUS CYREG_SCB2_SPI_STATUS
#define I2C_master_SCB__SS0_POSISTION 0u
#define I2C_master_SCB__SS1_POSISTION 1u
#define I2C_master_SCB__SS2_POSISTION 2u
#define I2C_master_SCB__SS3_POSISTION 3u
#define I2C_master_SCB__STATUS CYREG_SCB2_STATUS
#define I2C_master_SCB__TX_CTRL CYREG_SCB2_TX_CTRL
#define I2C_master_SCB__TX_FIFO_CTRL CYREG_SCB2_TX_FIFO_CTRL
#define I2C_master_SCB__TX_FIFO_STATUS CYREG_SCB2_TX_FIFO_STATUS
#define I2C_master_SCB__TX_FIFO_WR CYREG_SCB2_TX_FIFO_WR
#define I2C_master_SCB__UART_CTRL CYREG_SCB2_UART_CTRL
#define I2C_master_SCB__UART_FLOW_CTRL CYREG_SCB2_UART_FLOW_CTRL
#define I2C_master_SCB__UART_RX_CTRL CYREG_SCB2_UART_RX_CTRL
#define I2C_master_SCB__UART_RX_STATUS CYREG_SCB2_UART_RX_STATUS
#define I2C_master_SCB__UART_TX_CTRL CYREG_SCB2_UART_TX_CTRL

/* I2C_master_SCB_IRQ */
#define I2C_master_SCB_IRQ__INTC_CLR_EN_REG CYREG_CM0_ICER
#define I2C_master_SCB_IRQ__INTC_CLR_PD_REG CYREG_CM0_ICPR
#define I2C_master_SCB_IRQ__INTC_MASK 0x400u
#define I2C_master_SCB_IRQ__INTC_NUMBER 10u
#define I2C_master_SCB_IRQ__INTC_PRIOR_MASK 0xC00000u
#define I2C_master_SCB_IRQ__INTC_PRIOR_NUM 3u
#define I2C_master_SCB_IRQ__INTC_PRIOR_REG CYREG_CM0_IPR2
#define I2C_master_SCB_IRQ__INTC_SET_EN_REG CYREG_CM0_ISER
#define I2C_master_SCB_IRQ__INTC_SET_PD_REG CYREG_CM0_ISPR

/* I2C_master_SCBCLK */
#define I2C_master_SCBCLK__CTRL_REGISTER CYREG_PERI_PCLK_CTL2
#define I2C_master_SCBCLK__DIV_ID 0x00000001u
#define I2C_master_SCBCLK__DIV_REGISTER CYREG_PERI_DIV_8_CTL1
#define I2C_master_SCBCLK__PA_DIV_ID 0x000000FFu

/* I2C_master_scl */
#define I2C_master_scl__0__DR CYREG_GPIO_PRT3_DR
#define I2C_master_scl__0__DR_CLR CYREG_GPIO_PRT3_DR_CLR
#define I2C_master_scl__0__DR_INV CYREG_GPIO_PRT3_DR_INV
#define I2C_master_scl__0__DR_SET CYREG_GPIO_PRT3_DR_SET
#define I2C_master_scl__0__HSIOM CYREG_HSIOM_PORT_SEL3
#define I2C_master_scl__0__HSIOM_GPIO 0u
#define I2C_master_scl__0__HSIOM_I2C 15u
#define I2C_master_scl__0__HSIOM_I2C_SCL 15u
#define I2C_master_scl__0__HSIOM_MASK 0x00F00000u
#define I2C_master_scl__0__HSIOM_SHIFT 20u
#define I2C_master_scl__0__HSIOM_SPI 14u
#define I2C_master_scl__0__HSIOM_SPI_CLK 14u
#define I2C_master_scl__0__HSIOM_UART 10u
#define I2C_master_scl__0__HSIOM_UART_RTS 10u
#define I2C_master_scl__0__INTCFG CYREG_GPIO_PRT3_INTR_CFG
#define I2C_master_scl__0__INTR CYREG_GPIO_PRT3_INTR
#define I2C_master_scl__0__INTR_CFG CYREG_GPIO_PRT3_INTR_CFG
#define I2C_master_scl__0__INTSTAT CYREG_GPIO_PRT3_INTR
#define I2C_master_scl__0__MASK 0x20u
#define I2C_master_scl__0__PC CYREG_GPIO_PRT3_PC
#define I2C_master_scl__0__PC2 CYREG_GPIO_PRT3_PC2
#define I2C_master_scl__0__PORT 3u
#define I2C_master_scl__0__PS CYREG_GPIO_PRT3_PS
#define I2C_master_scl__0__SHIFT 5u
#define I2C_master_scl__DR CYREG_GPIO_PRT3_DR
#define I2C_master_scl__DR_CLR CYREG_GPIO_PRT3_DR_CLR
#define I2C_master_scl__DR_INV CYREG_GPIO_PRT3_DR_INV
#define I2C_master_scl__DR_SET CYREG_GPIO_PRT3_DR_SET
#define I2C_master_scl__INTCFG CYREG_GPIO_PRT3_INTR_CFG
#define I2C_master_scl__INTR CYREG_GPIO_PRT3_INTR
#define I2C_master_scl__INTR_CFG CYREG_GPIO_PRT3_INTR_CFG
#define I2C_master_scl__INTSTAT CYREG_GPIO_PRT3_INTR
#define I2C_master_scl__MASK 0x20u
#define I2C_master_scl__PC CYREG_GPIO_PRT3_PC
#define I2C_master_scl__PC2 CYREG_GPIO_PRT3_PC2
#define I2C_master_scl__PORT 3u
#define I2C_master_scl__PS CYREG_GPIO_PRT3_PS
#define I2C_master_scl__SHIFT 5u

/* I2C_master_sda */
#define I2C_master_sda__0__DR CYREG_GPIO_PRT3_DR
#define I2C_master_sda__0__DR_CLR CYREG_GPIO_PRT3_DR_CLR
#define I2C_master_sda__0__DR_INV CYREG_GPIO_PRT3_DR_INV
#define I2C_master_sda__0__DR_SET CYREG_GPIO_PRT3_DR_SET
#define I2C_master_sda__0__HSIOM CYREG_HSIOM_PORT_SEL3
#define I2C_master_sda__0__HSIOM_GPIO 0u
#define I2C_master_sda__0__HSIOM_I2C 15u
#define I2C_master_sda__0__HSIOM_I2C_SDA 15u
#define I2C_master_sda__0__HSIOM_MASK 0x000F0000u
#define I2C_master_sda__0__HSIOM_SHIFT 16u
#define I2C_master_sda__0__HSIOM_SPI 14u
#define I2C_master_sda__0__HSIOM_SPI_MOSI 14u
#define I2C_master_sda__0__HSIOM_UART 10u
#define I2C_master_sda__0__HSIOM_UART_CTS 10u
#define I2C_master_sda__0__INTCFG CYREG_GPIO_PRT3_INTR_CFG
#define I2C_master_sda__0__INTR CYREG_GPIO_PRT3_INTR
#define I2C_master_sda__0__INTR_CFG CYREG_GPIO_PRT3_INTR_CFG
#define I2C_master_sda__0__INTSTAT CYREG_GPIO_PRT3_INTR
#define I2C_master_sda__0__MASK 0x10u
#define I2C_master_sda__0__PC CYREG_GPIO_PRT3_PC
#define I2C_master_sda__0__PC2 CYREG_GPIO_PRT3_PC2
#define I2C_master_sda__0__PORT 3u
#define I2C_master_sda__0__PS CYREG_GPIO_PRT3_PS
#define I2C_master_sda__0__SHIFT 4u
#define I2C_master_sda__DR CYREG_GPIO_PRT3_DR
#define I2C_master_sda__DR_CLR CYREG_GPIO_PRT3_DR_CLR
#define I2C_master_sda__DR_INV CYREG_GPIO_PRT3_DR_INV
#define I2C_master_sda__DR_SET CYREG_GPIO_PRT3_DR_SET
#define I2C_master_sda__INTCFG CYREG_GPIO_PRT3_INTR_CFG
#define I2C_master_sda__INTR CYREG_GPIO_PRT3_INTR
#define I2C_master_sda__INTR_CFG CYREG_GPIO_PRT3_INTR_CFG
#define I2C_master_sda__INTSTAT CYREG_GPIO_PRT3_INTR
#define I2C_master_sda__MASK 0x10u
#define I2C_master_sda__PC CYREG_GPIO_PRT3_PC
#define I2C_master_sda__PC2 CYREG_GPIO_PRT3_PC2
#define I2C_master_sda__PORT 3u
#define I2C_master_sda__PS CYREG_GPIO_PRT3_PS
#define I2C_master_sda__SHIFT 4u

/* PDSS_PORT0_RX_CLK */
#define PDSS_PORT0_RX_CLK__DIV_ID 0x00000000u
#define PDSS_PORT0_RX_CLK__DIV_REGISTER CYREG_PERI_DIV_8_CTL0
#define PDSS_PORT0_RX_CLK__PA_DIV_ID 0x000000FFu

/* PDSS_PORT0_TX_CLK */
#define PDSS_PORT0_TX_CLK__DIV_ID 0x00000041u
#define PDSS_PORT0_TX_CLK__DIV_REGISTER CYREG_PERI_DIV_16_CTL1
#define PDSS_PORT0_TX_CLK__PA_DIV_ID 0x000000FFu

/* PDSS_PORT0_SAR_CLK */
#define PDSS_PORT0_SAR_CLK__DIV_ID 0x00000040u
#define PDSS_PORT0_SAR_CLK__DIV_REGISTER CYREG_PERI_DIV_16_CTL0
#define PDSS_PORT0_SAR_CLK__PA_DIV_ID 0x000000FFu

/* PDSS_PORT0_SWAP_CLK */
#define PDSS_PORT0_SWAP_CLK__DIV_ID 0x00000002u
#define PDSS_PORT0_SWAP_CLK__DIV_REGISTER CYREG_PERI_DIV_8_CTL2
#define PDSS_PORT0_SWAP_CLK__PA_DIV_ID 0x000000FFu

/* Miscellaneous */
#define CY_PROJECT_NAME "Generic_Example_Project"
#define CY_VERSION "PSoC Creator  3.3 DP1"
#define CYDEV_BANDGAP_VOLTAGE 1.200
#define CYDEV_BCLK__HFCLK__HZ 48000000U
#define CYDEV_BCLK__HFCLK__KHZ 48000U
#define CYDEV_BCLK__HFCLK__MHZ 48U
#define CYDEV_BCLK__SYSCLK__HZ 48000000U
#define CYDEV_BCLK__SYSCLK__KHZ 48000U
#define CYDEV_BCLK__SYSCLK__MHZ 48U
#define CYDEV_CHIP_DIE_LEOPARD 1u
#define CYDEV_CHIP_DIE_PANTHER 19u
#define CYDEV_CHIP_DIE_PSOC4A 11u
#define CYDEV_CHIP_DIE_PSOC5LP 18u
#define CYDEV_CHIP_DIE_TMA4 2u
#define CYDEV_CHIP_DIE_UNKNOWN 0u
#define CYDEV_CHIP_FAMILY_PSOC3 1u
#define CYDEV_CHIP_FAMILY_PSOC4 2u
#define CYDEV_CHIP_FAMILY_PSOC5 3u
#define CYDEV_CHIP_FAMILY_UNKNOWN 0u
#define CYDEV_CHIP_FAMILY_USED CYDEV_CHIP_FAMILY_PSOC4
#define CYDEV_CHIP_JTAG_ID 0x1D0411ADu
#define CYDEV_CHIP_MEMBER_3A 1u
#define CYDEV_CHIP_MEMBER_4A 11u
#define CYDEV_CHIP_MEMBER_4C 16u
#define CYDEV_CHIP_MEMBER_4D 7u
#define CYDEV_CHIP_MEMBER_4E 4u
#define CYDEV_CHIP_MEMBER_4F 12u
#define CYDEV_CHIP_MEMBER_4G 2u
#define CYDEV_CHIP_MEMBER_4H 10u
#define CYDEV_CHIP_MEMBER_4I 15u
#define CYDEV_CHIP_MEMBER_4J 8u
#define CYDEV_CHIP_MEMBER_4K 9u
#define CYDEV_CHIP_MEMBER_4L 14u
#define CYDEV_CHIP_MEMBER_4M 13u
#define CYDEV_CHIP_MEMBER_4N 6u
#define CYDEV_CHIP_MEMBER_4O 5u
#define CYDEV_CHIP_MEMBER_4U 3u
#define CYDEV_CHIP_MEMBER_5A 18u
#define CYDEV_CHIP_MEMBER_5B 17u
#define CYDEV_CHIP_MEMBER_UNKNOWN 0u
#define CYDEV_CHIP_MEMBER_USED CYDEV_CHIP_MEMBER_4O
#define CYDEV_CHIP_DIE_EXPECT CYDEV_CHIP_MEMBER_USED
#define CYDEV_CHIP_DIE_ACTUAL CYDEV_CHIP_DIE_EXPECT
#define CYDEV_CHIP_REV_LEOPARD_ES1 0u
#define CYDEV_CHIP_REV_LEOPARD_ES2 1u
#define CYDEV_CHIP_REV_LEOPARD_ES3 3u
#define CYDEV_CHIP_REV_LEOPARD_PRODUCTION 3u
#define CYDEV_CHIP_REV_PANTHER_ES0 0u
#define CYDEV_CHIP_REV_PANTHER_ES1 1u
#define CYDEV_CHIP_REV_PANTHER_PRODUCTION 1u
#define CYDEV_CHIP_REV_PSOC4A_ES0 17u
#define CYDEV_CHIP_REV_PSOC4A_PRODUCTION 17u
#define CYDEV_CHIP_REV_PSOC5LP_ES0 0u
#define CYDEV_CHIP_REV_PSOC5LP_PRODUCTION 0u
#define CYDEV_CHIP_REV_TMA4_ES 17u
#define CYDEV_CHIP_REV_TMA4_ES2 33u
#define CYDEV_CHIP_REV_TMA4_PRODUCTION 17u
#define CYDEV_CHIP_REVISION_3A_ES1 0u
#define CYDEV_CHIP_REVISION_3A_ES2 1u
#define CYDEV_CHIP_REVISION_3A_ES3 3u
#define CYDEV_CHIP_REVISION_3A_PRODUCTION 3u
#define CYDEV_CHIP_REVISION_4A_ES0 17u
#define CYDEV_CHIP_REVISION_4A_PRODUCTION 17u
#define CYDEV_CHIP_REVISION_4C_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4D_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4E_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4F_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4F_PRODUCTION_256DMA 0u
#define CYDEV_CHIP_REVISION_4F_PRODUCTION_256K 0u
#define CYDEV_CHIP_REVISION_4G_ES 17u
#define CYDEV_CHIP_REVISION_4G_ES2 33u
#define CYDEV_CHIP_REVISION_4G_PRODUCTION 17u
#define CYDEV_CHIP_REVISION_4H_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4I_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4J_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4K_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4L_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4M_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4N_ES 0u
#define CYDEV_CHIP_REVISION_4N_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4O_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4U_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_5A_ES0 0u
#define CYDEV_CHIP_REVISION_5A_ES1 1u
#define CYDEV_CHIP_REVISION_5A_PRODUCTION 1u
#define CYDEV_CHIP_REVISION_5B_ES0 0u
#define CYDEV_CHIP_REVISION_5B_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_USED CYDEV_CHIP_REVISION_4O_PRODUCTION
#define CYDEV_CHIP_REV_EXPECT CYDEV_CHIP_REVISION_USED
#define CYDEV_CONFIG_READ_ACCELERATOR 1
#define CYDEV_CONFIG_UNUSED_IO_AllowButWarn 0
#define CYDEV_CONFIG_UNUSED_IO_AllowWithInfo 1
#define CYDEV_CONFIG_UNUSED_IO_Disallowed 2
#define CYDEV_CONFIGURATION_COMPRESSED 1
#define CYDEV_CONFIGURATION_MODE_COMPRESSED 0
#define CYDEV_CONFIGURATION_MODE CYDEV_CONFIGURATION_MODE_COMPRESSED
#define CYDEV_CONFIGURATION_MODE_DMA 2
#define CYDEV_CONFIGURATION_MODE_UNCOMPRESSED 1
#define CYDEV_DEBUG_PROTECT_KILL 4
#define CYDEV_DEBUG_PROTECT_OPEN 1
#define CYDEV_DEBUG_PROTECT CYDEV_DEBUG_PROTECT_OPEN
#define CYDEV_DEBUG_PROTECT_PROTECTED 2
#define CYDEV_DEBUGGING_DPS_Disable 3
#define CYDEV_DEBUGGING_DPS CYDEV_DEBUGGING_DPS_Disable
#define CYDEV_DEBUGGING_DPS_SWD 2
#define CYDEV_DEBUGGING_ENABLE 0
#define CYDEV_DFT_SELECT_CLK0 8u
#define CYDEV_DFT_SELECT_CLK1 9u
#define CYDEV_HEAP_SIZE 0x80
#define CYDEV_IMO_TRIMMED_BY_USB 0u
#define CYDEV_IMO_TRIMMED_BY_WCO 0u
#define CYDEV_IS_EXPORTING_CODE 0
#define CYDEV_IS_IMPORTING_CODE 0
#define CYDEV_PROJ_TYPE 2
#define CYDEV_PROJ_TYPE_BOOTLOADER 1
#define CYDEV_PROJ_TYPE_LAUNCHER 5
#define CYDEV_PROJ_TYPE_LOADABLE 2
#define CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER 4
#define CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER 3
#define CYDEV_PROJ_TYPE_STANDARD 0
#define CYDEV_STACK_SIZE 0x0800
#define CYDEV_USE_BUNDLED_CMSIS 1
#define CYDEV_VARIABLE_VDDA 1
#define CYDEV_VDDD 3.3
#define CYDEV_VDDD_MV 3300
#define CYDEV_VDDIO 3.3
#define CYDEV_VDDIO_MV 3300
#define CYDEV_WDT_GENERATE_ISR 0u
#define CYIPBLOCK_m0s8cpussv3_VERSION 1
#define CYIPBLOCK_m0s8crypto_VERSION 2
#define CYIPBLOCK_m0s8ioss_VERSION 1
#define CYIPBLOCK_m0s8peri_VERSION 1
#define CYIPBLOCK_m0s8scb_VERSION 2
#define CYIPBLOCK_m0s8tcpwm_VERSION 2
#define CYIPBLOCK_m0s8usbdss_VERSION 2
#define CYIPBLOCK_m0s8usbpd_VERSION 2
#define CYIPBLOCK_s8srsslt_VERSION 1
#define CYDEV_BOOTLOADER_ENABLE 0

#endif /* INCLUDED_CYFITTER_H */
