.ifndef INCLUDED_CYFITTERGNU_INC
.set INCLUDED_CYFITTERGNU_INC, 1
.include "cydevicegnu_trm.inc"

/* HPD */
.set HPD__0__DR, CYREG_GPIO_PRT3_DR
.set HPD__0__DR_CLR, CYREG_GPIO_PRT3_DR_CLR
.set HPD__0__DR_INV, CYREG_GPIO_PRT3_DR_INV
.set HPD__0__DR_SET, CYREG_GPIO_PRT3_DR_SET
.set HPD__0__HSIOM, CYREG_HSIOM_PORT_SEL3
.set HPD__0__HSIOM_MASK, 0x0000F000
.set HPD__0__HSIOM_SHIFT, 12
.set HPD__0__INTCFG, CYREG_GPIO_PRT3_INTR_CFG
.set HPD__0__INTR, CYREG_GPIO_PRT3_INTR
.set HPD__0__INTR_CFG, CYREG_GPIO_PRT3_INTR_CFG
.set HPD__0__INTSTAT, CYREG_GPIO_PRT3_INTR
.set HPD__0__MASK, 0x08
.set HPD__0__PC, CYREG_GPIO_PRT3_PC
.set HPD__0__PC2, CYREG_GPIO_PRT3_PC2
.set HPD__0__PORT, 3
.set HPD__0__PS, CYREG_GPIO_PRT3_PS
.set HPD__0__SHIFT, 3
.set HPD__DR, CYREG_GPIO_PRT3_DR
.set HPD__DR_CLR, CYREG_GPIO_PRT3_DR_CLR
.set HPD__DR_INV, CYREG_GPIO_PRT3_DR_INV
.set HPD__DR_SET, CYREG_GPIO_PRT3_DR_SET
.set HPD__INTCFG, CYREG_GPIO_PRT3_INTR_CFG
.set HPD__INTR, CYREG_GPIO_PRT3_INTR
.set HPD__INTR_CFG, CYREG_GPIO_PRT3_INTR_CFG
.set HPD__INTSTAT, CYREG_GPIO_PRT3_INTR
.set HPD__MASK, 0x08
.set HPD__PC, CYREG_GPIO_PRT3_PC
.set HPD__PC2, CYREG_GPIO_PRT3_PC2
.set HPD__PORT, 3
.set HPD__PS, CYREG_GPIO_PRT3_PS
.set HPD__SHIFT, 3

/* EC_INT */
.set EC_INT__0__DR, CYREG_GPIO_PRT3_DR
.set EC_INT__0__DR_CLR, CYREG_GPIO_PRT3_DR_CLR
.set EC_INT__0__DR_INV, CYREG_GPIO_PRT3_DR_INV
.set EC_INT__0__DR_SET, CYREG_GPIO_PRT3_DR_SET
.set EC_INT__0__HSIOM, CYREG_HSIOM_PORT_SEL3
.set EC_INT__0__HSIOM_MASK, 0x00000F00
.set EC_INT__0__HSIOM_SHIFT, 8
.set EC_INT__0__INTCFG, CYREG_GPIO_PRT3_INTR_CFG
.set EC_INT__0__INTR, CYREG_GPIO_PRT3_INTR
.set EC_INT__0__INTR_CFG, CYREG_GPIO_PRT3_INTR_CFG
.set EC_INT__0__INTSTAT, CYREG_GPIO_PRT3_INTR
.set EC_INT__0__MASK, 0x04
.set EC_INT__0__PC, CYREG_GPIO_PRT3_PC
.set EC_INT__0__PC2, CYREG_GPIO_PRT3_PC2
.set EC_INT__0__PORT, 3
.set EC_INT__0__PS, CYREG_GPIO_PRT3_PS
.set EC_INT__0__SHIFT, 2
.set EC_INT__DR, CYREG_GPIO_PRT3_DR
.set EC_INT__DR_CLR, CYREG_GPIO_PRT3_DR_CLR
.set EC_INT__DR_INV, CYREG_GPIO_PRT3_DR_INV
.set EC_INT__DR_SET, CYREG_GPIO_PRT3_DR_SET
.set EC_INT__INTCFG, CYREG_GPIO_PRT3_INTR_CFG
.set EC_INT__INTR, CYREG_GPIO_PRT3_INTR
.set EC_INT__INTR_CFG, CYREG_GPIO_PRT3_INTR_CFG
.set EC_INT__INTSTAT, CYREG_GPIO_PRT3_INTR
.set EC_INT__MASK, 0x04
.set EC_INT__PC, CYREG_GPIO_PRT3_PC
.set EC_INT__PC2, CYREG_GPIO_PRT3_PC2
.set EC_INT__PORT, 3
.set EC_INT__PS, CYREG_GPIO_PRT3_PS
.set EC_INT__SHIFT, 2

/* FW_LED */
.set FW_LED__0__DR, CYREG_GPIO_PRT2_DR
.set FW_LED__0__DR_CLR, CYREG_GPIO_PRT2_DR_CLR
.set FW_LED__0__DR_INV, CYREG_GPIO_PRT2_DR_INV
.set FW_LED__0__DR_SET, CYREG_GPIO_PRT2_DR_SET
.set FW_LED__0__HSIOM, CYREG_HSIOM_PORT_SEL2
.set FW_LED__0__HSIOM_MASK, 0x0000000F
.set FW_LED__0__HSIOM_SHIFT, 0
.set FW_LED__0__INTCFG, CYREG_GPIO_PRT2_INTR_CFG
.set FW_LED__0__INTR, CYREG_GPIO_PRT2_INTR
.set FW_LED__0__INTR_CFG, CYREG_GPIO_PRT2_INTR_CFG
.set FW_LED__0__INTSTAT, CYREG_GPIO_PRT2_INTR
.set FW_LED__0__MASK, 0x01
.set FW_LED__0__PC, CYREG_GPIO_PRT2_PC
.set FW_LED__0__PC2, CYREG_GPIO_PRT2_PC2
.set FW_LED__0__PORT, 2
.set FW_LED__0__PS, CYREG_GPIO_PRT2_PS
.set FW_LED__0__SHIFT, 0
.set FW_LED__DR, CYREG_GPIO_PRT2_DR
.set FW_LED__DR_CLR, CYREG_GPIO_PRT2_DR_CLR
.set FW_LED__DR_INV, CYREG_GPIO_PRT2_DR_INV
.set FW_LED__DR_SET, CYREG_GPIO_PRT2_DR_SET
.set FW_LED__INTCFG, CYREG_GPIO_PRT2_INTR_CFG
.set FW_LED__INTR, CYREG_GPIO_PRT2_INTR
.set FW_LED__INTR_CFG, CYREG_GPIO_PRT2_INTR_CFG
.set FW_LED__INTSTAT, CYREG_GPIO_PRT2_INTR
.set FW_LED__MASK, 0x01
.set FW_LED__PC, CYREG_GPIO_PRT2_PC
.set FW_LED__PC2, CYREG_GPIO_PRT2_PC2
.set FW_LED__PORT, 2
.set FW_LED__PS, CYREG_GPIO_PRT2_PS
.set FW_LED__SHIFT, 0

/* I2C_CFG */
.set I2C_CFG__0__DR, CYREG_GPIO_PRT2_DR
.set I2C_CFG__0__DR_CLR, CYREG_GPIO_PRT2_DR_CLR
.set I2C_CFG__0__DR_INV, CYREG_GPIO_PRT2_DR_INV
.set I2C_CFG__0__DR_SET, CYREG_GPIO_PRT2_DR_SET
.set I2C_CFG__0__HSIOM, CYREG_HSIOM_PORT_SEL2
.set I2C_CFG__0__HSIOM_MASK, 0x000000F0
.set I2C_CFG__0__HSIOM_SHIFT, 4
.set I2C_CFG__0__INTCFG, CYREG_GPIO_PRT2_INTR_CFG
.set I2C_CFG__0__INTR, CYREG_GPIO_PRT2_INTR
.set I2C_CFG__0__INTR_CFG, CYREG_GPIO_PRT2_INTR_CFG
.set I2C_CFG__0__INTSTAT, CYREG_GPIO_PRT2_INTR
.set I2C_CFG__0__MASK, 0x02
.set I2C_CFG__0__PC, CYREG_GPIO_PRT2_PC
.set I2C_CFG__0__PC2, CYREG_GPIO_PRT2_PC2
.set I2C_CFG__0__PORT, 2
.set I2C_CFG__0__PS, CYREG_GPIO_PRT2_PS
.set I2C_CFG__0__SHIFT, 1
.set I2C_CFG__DR, CYREG_GPIO_PRT2_DR
.set I2C_CFG__DR_CLR, CYREG_GPIO_PRT2_DR_CLR
.set I2C_CFG__DR_INV, CYREG_GPIO_PRT2_DR_INV
.set I2C_CFG__DR_SET, CYREG_GPIO_PRT2_DR_SET
.set I2C_CFG__INTCFG, CYREG_GPIO_PRT2_INTR_CFG
.set I2C_CFG__INTR, CYREG_GPIO_PRT2_INTR
.set I2C_CFG__INTR_CFG, CYREG_GPIO_PRT2_INTR_CFG
.set I2C_CFG__INTSTAT, CYREG_GPIO_PRT2_INTR
.set I2C_CFG__MASK, 0x02
.set I2C_CFG__PC, CYREG_GPIO_PRT2_PC
.set I2C_CFG__PC2, CYREG_GPIO_PRT2_PC2
.set I2C_CFG__PORT, 2
.set I2C_CFG__PS, CYREG_GPIO_PRT2_PS
.set I2C_CFG__SHIFT, 1

/* MUX_CTRL_SCB */
.set MUX_CTRL_SCB__CMD_RESP_CTRL, CYREG_SCB3_CMD_RESP_CTRL
.set MUX_CTRL_SCB__CMD_RESP_STATUS, CYREG_SCB3_CMD_RESP_STATUS
.set MUX_CTRL_SCB__CTRL, CYREG_SCB3_CTRL
.set MUX_CTRL_SCB__EZ_DATA0, CYREG_SCB3_EZ_DATA0
.set MUX_CTRL_SCB__EZ_DATA1, CYREG_SCB3_EZ_DATA1
.set MUX_CTRL_SCB__EZ_DATA10, CYREG_SCB3_EZ_DATA10
.set MUX_CTRL_SCB__EZ_DATA100, CYREG_SCB3_EZ_DATA100
.set MUX_CTRL_SCB__EZ_DATA101, CYREG_SCB3_EZ_DATA101
.set MUX_CTRL_SCB__EZ_DATA102, CYREG_SCB3_EZ_DATA102
.set MUX_CTRL_SCB__EZ_DATA103, CYREG_SCB3_EZ_DATA103
.set MUX_CTRL_SCB__EZ_DATA104, CYREG_SCB3_EZ_DATA104
.set MUX_CTRL_SCB__EZ_DATA105, CYREG_SCB3_EZ_DATA105
.set MUX_CTRL_SCB__EZ_DATA106, CYREG_SCB3_EZ_DATA106
.set MUX_CTRL_SCB__EZ_DATA107, CYREG_SCB3_EZ_DATA107
.set MUX_CTRL_SCB__EZ_DATA108, CYREG_SCB3_EZ_DATA108
.set MUX_CTRL_SCB__EZ_DATA109, CYREG_SCB3_EZ_DATA109
.set MUX_CTRL_SCB__EZ_DATA11, CYREG_SCB3_EZ_DATA11
.set MUX_CTRL_SCB__EZ_DATA110, CYREG_SCB3_EZ_DATA110
.set MUX_CTRL_SCB__EZ_DATA111, CYREG_SCB3_EZ_DATA111
.set MUX_CTRL_SCB__EZ_DATA112, CYREG_SCB3_EZ_DATA112
.set MUX_CTRL_SCB__EZ_DATA113, CYREG_SCB3_EZ_DATA113
.set MUX_CTRL_SCB__EZ_DATA114, CYREG_SCB3_EZ_DATA114
.set MUX_CTRL_SCB__EZ_DATA115, CYREG_SCB3_EZ_DATA115
.set MUX_CTRL_SCB__EZ_DATA116, CYREG_SCB3_EZ_DATA116
.set MUX_CTRL_SCB__EZ_DATA117, CYREG_SCB3_EZ_DATA117
.set MUX_CTRL_SCB__EZ_DATA118, CYREG_SCB3_EZ_DATA118
.set MUX_CTRL_SCB__EZ_DATA119, CYREG_SCB3_EZ_DATA119
.set MUX_CTRL_SCB__EZ_DATA12, CYREG_SCB3_EZ_DATA12
.set MUX_CTRL_SCB__EZ_DATA120, CYREG_SCB3_EZ_DATA120
.set MUX_CTRL_SCB__EZ_DATA121, CYREG_SCB3_EZ_DATA121
.set MUX_CTRL_SCB__EZ_DATA122, CYREG_SCB3_EZ_DATA122
.set MUX_CTRL_SCB__EZ_DATA123, CYREG_SCB3_EZ_DATA123
.set MUX_CTRL_SCB__EZ_DATA124, CYREG_SCB3_EZ_DATA124
.set MUX_CTRL_SCB__EZ_DATA125, CYREG_SCB3_EZ_DATA125
.set MUX_CTRL_SCB__EZ_DATA126, CYREG_SCB3_EZ_DATA126
.set MUX_CTRL_SCB__EZ_DATA127, CYREG_SCB3_EZ_DATA127
.set MUX_CTRL_SCB__EZ_DATA128, CYREG_SCB3_EZ_DATA128
.set MUX_CTRL_SCB__EZ_DATA129, CYREG_SCB3_EZ_DATA129
.set MUX_CTRL_SCB__EZ_DATA13, CYREG_SCB3_EZ_DATA13
.set MUX_CTRL_SCB__EZ_DATA130, CYREG_SCB3_EZ_DATA130
.set MUX_CTRL_SCB__EZ_DATA131, CYREG_SCB3_EZ_DATA131
.set MUX_CTRL_SCB__EZ_DATA132, CYREG_SCB3_EZ_DATA132
.set MUX_CTRL_SCB__EZ_DATA133, CYREG_SCB3_EZ_DATA133
.set MUX_CTRL_SCB__EZ_DATA134, CYREG_SCB3_EZ_DATA134
.set MUX_CTRL_SCB__EZ_DATA135, CYREG_SCB3_EZ_DATA135
.set MUX_CTRL_SCB__EZ_DATA136, CYREG_SCB3_EZ_DATA136
.set MUX_CTRL_SCB__EZ_DATA137, CYREG_SCB3_EZ_DATA137
.set MUX_CTRL_SCB__EZ_DATA138, CYREG_SCB3_EZ_DATA138
.set MUX_CTRL_SCB__EZ_DATA139, CYREG_SCB3_EZ_DATA139
.set MUX_CTRL_SCB__EZ_DATA14, CYREG_SCB3_EZ_DATA14
.set MUX_CTRL_SCB__EZ_DATA140, CYREG_SCB3_EZ_DATA140
.set MUX_CTRL_SCB__EZ_DATA141, CYREG_SCB3_EZ_DATA141
.set MUX_CTRL_SCB__EZ_DATA142, CYREG_SCB3_EZ_DATA142
.set MUX_CTRL_SCB__EZ_DATA143, CYREG_SCB3_EZ_DATA143
.set MUX_CTRL_SCB__EZ_DATA144, CYREG_SCB3_EZ_DATA144
.set MUX_CTRL_SCB__EZ_DATA145, CYREG_SCB3_EZ_DATA145
.set MUX_CTRL_SCB__EZ_DATA146, CYREG_SCB3_EZ_DATA146
.set MUX_CTRL_SCB__EZ_DATA147, CYREG_SCB3_EZ_DATA147
.set MUX_CTRL_SCB__EZ_DATA148, CYREG_SCB3_EZ_DATA148
.set MUX_CTRL_SCB__EZ_DATA149, CYREG_SCB3_EZ_DATA149
.set MUX_CTRL_SCB__EZ_DATA15, CYREG_SCB3_EZ_DATA15
.set MUX_CTRL_SCB__EZ_DATA150, CYREG_SCB3_EZ_DATA150
.set MUX_CTRL_SCB__EZ_DATA151, CYREG_SCB3_EZ_DATA151
.set MUX_CTRL_SCB__EZ_DATA152, CYREG_SCB3_EZ_DATA152
.set MUX_CTRL_SCB__EZ_DATA153, CYREG_SCB3_EZ_DATA153
.set MUX_CTRL_SCB__EZ_DATA154, CYREG_SCB3_EZ_DATA154
.set MUX_CTRL_SCB__EZ_DATA155, CYREG_SCB3_EZ_DATA155
.set MUX_CTRL_SCB__EZ_DATA156, CYREG_SCB3_EZ_DATA156
.set MUX_CTRL_SCB__EZ_DATA157, CYREG_SCB3_EZ_DATA157
.set MUX_CTRL_SCB__EZ_DATA158, CYREG_SCB3_EZ_DATA158
.set MUX_CTRL_SCB__EZ_DATA159, CYREG_SCB3_EZ_DATA159
.set MUX_CTRL_SCB__EZ_DATA16, CYREG_SCB3_EZ_DATA16
.set MUX_CTRL_SCB__EZ_DATA160, CYREG_SCB3_EZ_DATA160
.set MUX_CTRL_SCB__EZ_DATA161, CYREG_SCB3_EZ_DATA161
.set MUX_CTRL_SCB__EZ_DATA162, CYREG_SCB3_EZ_DATA162
.set MUX_CTRL_SCB__EZ_DATA163, CYREG_SCB3_EZ_DATA163
.set MUX_CTRL_SCB__EZ_DATA164, CYREG_SCB3_EZ_DATA164
.set MUX_CTRL_SCB__EZ_DATA165, CYREG_SCB3_EZ_DATA165
.set MUX_CTRL_SCB__EZ_DATA166, CYREG_SCB3_EZ_DATA166
.set MUX_CTRL_SCB__EZ_DATA167, CYREG_SCB3_EZ_DATA167
.set MUX_CTRL_SCB__EZ_DATA168, CYREG_SCB3_EZ_DATA168
.set MUX_CTRL_SCB__EZ_DATA169, CYREG_SCB3_EZ_DATA169
.set MUX_CTRL_SCB__EZ_DATA17, CYREG_SCB3_EZ_DATA17
.set MUX_CTRL_SCB__EZ_DATA170, CYREG_SCB3_EZ_DATA170
.set MUX_CTRL_SCB__EZ_DATA171, CYREG_SCB3_EZ_DATA171
.set MUX_CTRL_SCB__EZ_DATA172, CYREG_SCB3_EZ_DATA172
.set MUX_CTRL_SCB__EZ_DATA173, CYREG_SCB3_EZ_DATA173
.set MUX_CTRL_SCB__EZ_DATA174, CYREG_SCB3_EZ_DATA174
.set MUX_CTRL_SCB__EZ_DATA175, CYREG_SCB3_EZ_DATA175
.set MUX_CTRL_SCB__EZ_DATA176, CYREG_SCB3_EZ_DATA176
.set MUX_CTRL_SCB__EZ_DATA177, CYREG_SCB3_EZ_DATA177
.set MUX_CTRL_SCB__EZ_DATA178, CYREG_SCB3_EZ_DATA178
.set MUX_CTRL_SCB__EZ_DATA179, CYREG_SCB3_EZ_DATA179
.set MUX_CTRL_SCB__EZ_DATA18, CYREG_SCB3_EZ_DATA18
.set MUX_CTRL_SCB__EZ_DATA180, CYREG_SCB3_EZ_DATA180
.set MUX_CTRL_SCB__EZ_DATA181, CYREG_SCB3_EZ_DATA181
.set MUX_CTRL_SCB__EZ_DATA182, CYREG_SCB3_EZ_DATA182
.set MUX_CTRL_SCB__EZ_DATA183, CYREG_SCB3_EZ_DATA183
.set MUX_CTRL_SCB__EZ_DATA184, CYREG_SCB3_EZ_DATA184
.set MUX_CTRL_SCB__EZ_DATA185, CYREG_SCB3_EZ_DATA185
.set MUX_CTRL_SCB__EZ_DATA186, CYREG_SCB3_EZ_DATA186
.set MUX_CTRL_SCB__EZ_DATA187, CYREG_SCB3_EZ_DATA187
.set MUX_CTRL_SCB__EZ_DATA188, CYREG_SCB3_EZ_DATA188
.set MUX_CTRL_SCB__EZ_DATA189, CYREG_SCB3_EZ_DATA189
.set MUX_CTRL_SCB__EZ_DATA19, CYREG_SCB3_EZ_DATA19
.set MUX_CTRL_SCB__EZ_DATA190, CYREG_SCB3_EZ_DATA190
.set MUX_CTRL_SCB__EZ_DATA191, CYREG_SCB3_EZ_DATA191
.set MUX_CTRL_SCB__EZ_DATA192, CYREG_SCB3_EZ_DATA192
.set MUX_CTRL_SCB__EZ_DATA193, CYREG_SCB3_EZ_DATA193
.set MUX_CTRL_SCB__EZ_DATA194, CYREG_SCB3_EZ_DATA194
.set MUX_CTRL_SCB__EZ_DATA195, CYREG_SCB3_EZ_DATA195
.set MUX_CTRL_SCB__EZ_DATA196, CYREG_SCB3_EZ_DATA196
.set MUX_CTRL_SCB__EZ_DATA197, CYREG_SCB3_EZ_DATA197
.set MUX_CTRL_SCB__EZ_DATA198, CYREG_SCB3_EZ_DATA198
.set MUX_CTRL_SCB__EZ_DATA199, CYREG_SCB3_EZ_DATA199
.set MUX_CTRL_SCB__EZ_DATA2, CYREG_SCB3_EZ_DATA2
.set MUX_CTRL_SCB__EZ_DATA20, CYREG_SCB3_EZ_DATA20
.set MUX_CTRL_SCB__EZ_DATA200, CYREG_SCB3_EZ_DATA200
.set MUX_CTRL_SCB__EZ_DATA201, CYREG_SCB3_EZ_DATA201
.set MUX_CTRL_SCB__EZ_DATA202, CYREG_SCB3_EZ_DATA202
.set MUX_CTRL_SCB__EZ_DATA203, CYREG_SCB3_EZ_DATA203
.set MUX_CTRL_SCB__EZ_DATA204, CYREG_SCB3_EZ_DATA204
.set MUX_CTRL_SCB__EZ_DATA205, CYREG_SCB3_EZ_DATA205
.set MUX_CTRL_SCB__EZ_DATA206, CYREG_SCB3_EZ_DATA206
.set MUX_CTRL_SCB__EZ_DATA207, CYREG_SCB3_EZ_DATA207
.set MUX_CTRL_SCB__EZ_DATA208, CYREG_SCB3_EZ_DATA208
.set MUX_CTRL_SCB__EZ_DATA209, CYREG_SCB3_EZ_DATA209
.set MUX_CTRL_SCB__EZ_DATA21, CYREG_SCB3_EZ_DATA21
.set MUX_CTRL_SCB__EZ_DATA210, CYREG_SCB3_EZ_DATA210
.set MUX_CTRL_SCB__EZ_DATA211, CYREG_SCB3_EZ_DATA211
.set MUX_CTRL_SCB__EZ_DATA212, CYREG_SCB3_EZ_DATA212
.set MUX_CTRL_SCB__EZ_DATA213, CYREG_SCB3_EZ_DATA213
.set MUX_CTRL_SCB__EZ_DATA214, CYREG_SCB3_EZ_DATA214
.set MUX_CTRL_SCB__EZ_DATA215, CYREG_SCB3_EZ_DATA215
.set MUX_CTRL_SCB__EZ_DATA216, CYREG_SCB3_EZ_DATA216
.set MUX_CTRL_SCB__EZ_DATA217, CYREG_SCB3_EZ_DATA217
.set MUX_CTRL_SCB__EZ_DATA218, CYREG_SCB3_EZ_DATA218
.set MUX_CTRL_SCB__EZ_DATA219, CYREG_SCB3_EZ_DATA219
.set MUX_CTRL_SCB__EZ_DATA22, CYREG_SCB3_EZ_DATA22
.set MUX_CTRL_SCB__EZ_DATA220, CYREG_SCB3_EZ_DATA220
.set MUX_CTRL_SCB__EZ_DATA221, CYREG_SCB3_EZ_DATA221
.set MUX_CTRL_SCB__EZ_DATA222, CYREG_SCB3_EZ_DATA222
.set MUX_CTRL_SCB__EZ_DATA223, CYREG_SCB3_EZ_DATA223
.set MUX_CTRL_SCB__EZ_DATA224, CYREG_SCB3_EZ_DATA224
.set MUX_CTRL_SCB__EZ_DATA225, CYREG_SCB3_EZ_DATA225
.set MUX_CTRL_SCB__EZ_DATA226, CYREG_SCB3_EZ_DATA226
.set MUX_CTRL_SCB__EZ_DATA227, CYREG_SCB3_EZ_DATA227
.set MUX_CTRL_SCB__EZ_DATA228, CYREG_SCB3_EZ_DATA228
.set MUX_CTRL_SCB__EZ_DATA229, CYREG_SCB3_EZ_DATA229
.set MUX_CTRL_SCB__EZ_DATA23, CYREG_SCB3_EZ_DATA23
.set MUX_CTRL_SCB__EZ_DATA230, CYREG_SCB3_EZ_DATA230
.set MUX_CTRL_SCB__EZ_DATA231, CYREG_SCB3_EZ_DATA231
.set MUX_CTRL_SCB__EZ_DATA232, CYREG_SCB3_EZ_DATA232
.set MUX_CTRL_SCB__EZ_DATA233, CYREG_SCB3_EZ_DATA233
.set MUX_CTRL_SCB__EZ_DATA234, CYREG_SCB3_EZ_DATA234
.set MUX_CTRL_SCB__EZ_DATA235, CYREG_SCB3_EZ_DATA235
.set MUX_CTRL_SCB__EZ_DATA236, CYREG_SCB3_EZ_DATA236
.set MUX_CTRL_SCB__EZ_DATA237, CYREG_SCB3_EZ_DATA237
.set MUX_CTRL_SCB__EZ_DATA238, CYREG_SCB3_EZ_DATA238
.set MUX_CTRL_SCB__EZ_DATA239, CYREG_SCB3_EZ_DATA239
.set MUX_CTRL_SCB__EZ_DATA24, CYREG_SCB3_EZ_DATA24
.set MUX_CTRL_SCB__EZ_DATA240, CYREG_SCB3_EZ_DATA240
.set MUX_CTRL_SCB__EZ_DATA241, CYREG_SCB3_EZ_DATA241
.set MUX_CTRL_SCB__EZ_DATA242, CYREG_SCB3_EZ_DATA242
.set MUX_CTRL_SCB__EZ_DATA243, CYREG_SCB3_EZ_DATA243
.set MUX_CTRL_SCB__EZ_DATA244, CYREG_SCB3_EZ_DATA244
.set MUX_CTRL_SCB__EZ_DATA245, CYREG_SCB3_EZ_DATA245
.set MUX_CTRL_SCB__EZ_DATA246, CYREG_SCB3_EZ_DATA246
.set MUX_CTRL_SCB__EZ_DATA247, CYREG_SCB3_EZ_DATA247
.set MUX_CTRL_SCB__EZ_DATA248, CYREG_SCB3_EZ_DATA248
.set MUX_CTRL_SCB__EZ_DATA249, CYREG_SCB3_EZ_DATA249
.set MUX_CTRL_SCB__EZ_DATA25, CYREG_SCB3_EZ_DATA25
.set MUX_CTRL_SCB__EZ_DATA250, CYREG_SCB3_EZ_DATA250
.set MUX_CTRL_SCB__EZ_DATA251, CYREG_SCB3_EZ_DATA251
.set MUX_CTRL_SCB__EZ_DATA252, CYREG_SCB3_EZ_DATA252
.set MUX_CTRL_SCB__EZ_DATA253, CYREG_SCB3_EZ_DATA253
.set MUX_CTRL_SCB__EZ_DATA254, CYREG_SCB3_EZ_DATA254
.set MUX_CTRL_SCB__EZ_DATA255, CYREG_SCB3_EZ_DATA255
.set MUX_CTRL_SCB__EZ_DATA26, CYREG_SCB3_EZ_DATA26
.set MUX_CTRL_SCB__EZ_DATA27, CYREG_SCB3_EZ_DATA27
.set MUX_CTRL_SCB__EZ_DATA28, CYREG_SCB3_EZ_DATA28
.set MUX_CTRL_SCB__EZ_DATA29, CYREG_SCB3_EZ_DATA29
.set MUX_CTRL_SCB__EZ_DATA3, CYREG_SCB3_EZ_DATA3
.set MUX_CTRL_SCB__EZ_DATA30, CYREG_SCB3_EZ_DATA30
.set MUX_CTRL_SCB__EZ_DATA31, CYREG_SCB3_EZ_DATA31
.set MUX_CTRL_SCB__EZ_DATA32, CYREG_SCB3_EZ_DATA32
.set MUX_CTRL_SCB__EZ_DATA33, CYREG_SCB3_EZ_DATA33
.set MUX_CTRL_SCB__EZ_DATA34, CYREG_SCB3_EZ_DATA34
.set MUX_CTRL_SCB__EZ_DATA35, CYREG_SCB3_EZ_DATA35
.set MUX_CTRL_SCB__EZ_DATA36, CYREG_SCB3_EZ_DATA36
.set MUX_CTRL_SCB__EZ_DATA37, CYREG_SCB3_EZ_DATA37
.set MUX_CTRL_SCB__EZ_DATA38, CYREG_SCB3_EZ_DATA38
.set MUX_CTRL_SCB__EZ_DATA39, CYREG_SCB3_EZ_DATA39
.set MUX_CTRL_SCB__EZ_DATA4, CYREG_SCB3_EZ_DATA4
.set MUX_CTRL_SCB__EZ_DATA40, CYREG_SCB3_EZ_DATA40
.set MUX_CTRL_SCB__EZ_DATA41, CYREG_SCB3_EZ_DATA41
.set MUX_CTRL_SCB__EZ_DATA42, CYREG_SCB3_EZ_DATA42
.set MUX_CTRL_SCB__EZ_DATA43, CYREG_SCB3_EZ_DATA43
.set MUX_CTRL_SCB__EZ_DATA44, CYREG_SCB3_EZ_DATA44
.set MUX_CTRL_SCB__EZ_DATA45, CYREG_SCB3_EZ_DATA45
.set MUX_CTRL_SCB__EZ_DATA46, CYREG_SCB3_EZ_DATA46
.set MUX_CTRL_SCB__EZ_DATA47, CYREG_SCB3_EZ_DATA47
.set MUX_CTRL_SCB__EZ_DATA48, CYREG_SCB3_EZ_DATA48
.set MUX_CTRL_SCB__EZ_DATA49, CYREG_SCB3_EZ_DATA49
.set MUX_CTRL_SCB__EZ_DATA5, CYREG_SCB3_EZ_DATA5
.set MUX_CTRL_SCB__EZ_DATA50, CYREG_SCB3_EZ_DATA50
.set MUX_CTRL_SCB__EZ_DATA51, CYREG_SCB3_EZ_DATA51
.set MUX_CTRL_SCB__EZ_DATA52, CYREG_SCB3_EZ_DATA52
.set MUX_CTRL_SCB__EZ_DATA53, CYREG_SCB3_EZ_DATA53
.set MUX_CTRL_SCB__EZ_DATA54, CYREG_SCB3_EZ_DATA54
.set MUX_CTRL_SCB__EZ_DATA55, CYREG_SCB3_EZ_DATA55
.set MUX_CTRL_SCB__EZ_DATA56, CYREG_SCB3_EZ_DATA56
.set MUX_CTRL_SCB__EZ_DATA57, CYREG_SCB3_EZ_DATA57
.set MUX_CTRL_SCB__EZ_DATA58, CYREG_SCB3_EZ_DATA58
.set MUX_CTRL_SCB__EZ_DATA59, CYREG_SCB3_EZ_DATA59
.set MUX_CTRL_SCB__EZ_DATA6, CYREG_SCB3_EZ_DATA6
.set MUX_CTRL_SCB__EZ_DATA60, CYREG_SCB3_EZ_DATA60
.set MUX_CTRL_SCB__EZ_DATA61, CYREG_SCB3_EZ_DATA61
.set MUX_CTRL_SCB__EZ_DATA62, CYREG_SCB3_EZ_DATA62
.set MUX_CTRL_SCB__EZ_DATA63, CYREG_SCB3_EZ_DATA63
.set MUX_CTRL_SCB__EZ_DATA64, CYREG_SCB3_EZ_DATA64
.set MUX_CTRL_SCB__EZ_DATA65, CYREG_SCB3_EZ_DATA65
.set MUX_CTRL_SCB__EZ_DATA66, CYREG_SCB3_EZ_DATA66
.set MUX_CTRL_SCB__EZ_DATA67, CYREG_SCB3_EZ_DATA67
.set MUX_CTRL_SCB__EZ_DATA68, CYREG_SCB3_EZ_DATA68
.set MUX_CTRL_SCB__EZ_DATA69, CYREG_SCB3_EZ_DATA69
.set MUX_CTRL_SCB__EZ_DATA7, CYREG_SCB3_EZ_DATA7
.set MUX_CTRL_SCB__EZ_DATA70, CYREG_SCB3_EZ_DATA70
.set MUX_CTRL_SCB__EZ_DATA71, CYREG_SCB3_EZ_DATA71
.set MUX_CTRL_SCB__EZ_DATA72, CYREG_SCB3_EZ_DATA72
.set MUX_CTRL_SCB__EZ_DATA73, CYREG_SCB3_EZ_DATA73
.set MUX_CTRL_SCB__EZ_DATA74, CYREG_SCB3_EZ_DATA74
.set MUX_CTRL_SCB__EZ_DATA75, CYREG_SCB3_EZ_DATA75
.set MUX_CTRL_SCB__EZ_DATA76, CYREG_SCB3_EZ_DATA76
.set MUX_CTRL_SCB__EZ_DATA77, CYREG_SCB3_EZ_DATA77
.set MUX_CTRL_SCB__EZ_DATA78, CYREG_SCB3_EZ_DATA78
.set MUX_CTRL_SCB__EZ_DATA79, CYREG_SCB3_EZ_DATA79
.set MUX_CTRL_SCB__EZ_DATA8, CYREG_SCB3_EZ_DATA8
.set MUX_CTRL_SCB__EZ_DATA80, CYREG_SCB3_EZ_DATA80
.set MUX_CTRL_SCB__EZ_DATA81, CYREG_SCB3_EZ_DATA81
.set MUX_CTRL_SCB__EZ_DATA82, CYREG_SCB3_EZ_DATA82
.set MUX_CTRL_SCB__EZ_DATA83, CYREG_SCB3_EZ_DATA83
.set MUX_CTRL_SCB__EZ_DATA84, CYREG_SCB3_EZ_DATA84
.set MUX_CTRL_SCB__EZ_DATA85, CYREG_SCB3_EZ_DATA85
.set MUX_CTRL_SCB__EZ_DATA86, CYREG_SCB3_EZ_DATA86
.set MUX_CTRL_SCB__EZ_DATA87, CYREG_SCB3_EZ_DATA87
.set MUX_CTRL_SCB__EZ_DATA88, CYREG_SCB3_EZ_DATA88
.set MUX_CTRL_SCB__EZ_DATA89, CYREG_SCB3_EZ_DATA89
.set MUX_CTRL_SCB__EZ_DATA9, CYREG_SCB3_EZ_DATA9
.set MUX_CTRL_SCB__EZ_DATA90, CYREG_SCB3_EZ_DATA90
.set MUX_CTRL_SCB__EZ_DATA91, CYREG_SCB3_EZ_DATA91
.set MUX_CTRL_SCB__EZ_DATA92, CYREG_SCB3_EZ_DATA92
.set MUX_CTRL_SCB__EZ_DATA93, CYREG_SCB3_EZ_DATA93
.set MUX_CTRL_SCB__EZ_DATA94, CYREG_SCB3_EZ_DATA94
.set MUX_CTRL_SCB__EZ_DATA95, CYREG_SCB3_EZ_DATA95
.set MUX_CTRL_SCB__EZ_DATA96, CYREG_SCB3_EZ_DATA96
.set MUX_CTRL_SCB__EZ_DATA97, CYREG_SCB3_EZ_DATA97
.set MUX_CTRL_SCB__EZ_DATA98, CYREG_SCB3_EZ_DATA98
.set MUX_CTRL_SCB__EZ_DATA99, CYREG_SCB3_EZ_DATA99
.set MUX_CTRL_SCB__I2C_CFG, CYREG_SCB3_I2C_CFG
.set MUX_CTRL_SCB__I2C_CTRL, CYREG_SCB3_I2C_CTRL
.set MUX_CTRL_SCB__I2C_M_CMD, CYREG_SCB3_I2C_M_CMD
.set MUX_CTRL_SCB__I2C_S_CMD, CYREG_SCB3_I2C_S_CMD
.set MUX_CTRL_SCB__I2C_STATUS, CYREG_SCB3_I2C_STATUS
.set MUX_CTRL_SCB__INTR_CAUSE, CYREG_SCB3_INTR_CAUSE
.set MUX_CTRL_SCB__INTR_I2C_EC, CYREG_SCB3_INTR_I2C_EC
.set MUX_CTRL_SCB__INTR_I2C_EC_MASK, CYREG_SCB3_INTR_I2C_EC_MASK
.set MUX_CTRL_SCB__INTR_I2C_EC_MASKED, CYREG_SCB3_INTR_I2C_EC_MASKED
.set MUX_CTRL_SCB__INTR_M, CYREG_SCB3_INTR_M
.set MUX_CTRL_SCB__INTR_M_MASK, CYREG_SCB3_INTR_M_MASK
.set MUX_CTRL_SCB__INTR_M_MASKED, CYREG_SCB3_INTR_M_MASKED
.set MUX_CTRL_SCB__INTR_M_SET, CYREG_SCB3_INTR_M_SET
.set MUX_CTRL_SCB__INTR_RX, CYREG_SCB3_INTR_RX
.set MUX_CTRL_SCB__INTR_RX_MASK, CYREG_SCB3_INTR_RX_MASK
.set MUX_CTRL_SCB__INTR_RX_MASKED, CYREG_SCB3_INTR_RX_MASKED
.set MUX_CTRL_SCB__INTR_RX_SET, CYREG_SCB3_INTR_RX_SET
.set MUX_CTRL_SCB__INTR_S, CYREG_SCB3_INTR_S
.set MUX_CTRL_SCB__INTR_S_MASK, CYREG_SCB3_INTR_S_MASK
.set MUX_CTRL_SCB__INTR_S_MASKED, CYREG_SCB3_INTR_S_MASKED
.set MUX_CTRL_SCB__INTR_S_SET, CYREG_SCB3_INTR_S_SET
.set MUX_CTRL_SCB__INTR_SPI_EC, CYREG_SCB3_INTR_SPI_EC
.set MUX_CTRL_SCB__INTR_SPI_EC_MASK, CYREG_SCB3_INTR_SPI_EC_MASK
.set MUX_CTRL_SCB__INTR_SPI_EC_MASKED, CYREG_SCB3_INTR_SPI_EC_MASKED
.set MUX_CTRL_SCB__INTR_TX, CYREG_SCB3_INTR_TX
.set MUX_CTRL_SCB__INTR_TX_MASK, CYREG_SCB3_INTR_TX_MASK
.set MUX_CTRL_SCB__INTR_TX_MASKED, CYREG_SCB3_INTR_TX_MASKED
.set MUX_CTRL_SCB__INTR_TX_SET, CYREG_SCB3_INTR_TX_SET
.set MUX_CTRL_SCB__RX_CTRL, CYREG_SCB3_RX_CTRL
.set MUX_CTRL_SCB__RX_FIFO_CTRL, CYREG_SCB3_RX_FIFO_CTRL
.set MUX_CTRL_SCB__RX_FIFO_RD, CYREG_SCB3_RX_FIFO_RD
.set MUX_CTRL_SCB__RX_FIFO_RD_SILENT, CYREG_SCB3_RX_FIFO_RD_SILENT
.set MUX_CTRL_SCB__RX_FIFO_STATUS, CYREG_SCB3_RX_FIFO_STATUS
.set MUX_CTRL_SCB__RX_MATCH, CYREG_SCB3_RX_MATCH
.set MUX_CTRL_SCB__SPI_CTRL, CYREG_SCB3_SPI_CTRL
.set MUX_CTRL_SCB__SPI_STATUS, CYREG_SCB3_SPI_STATUS
.set MUX_CTRL_SCB__SS0_POSISTION, 0
.set MUX_CTRL_SCB__SS1_POSISTION, 1
.set MUX_CTRL_SCB__SS2_POSISTION, 2
.set MUX_CTRL_SCB__SS3_POSISTION, 3
.set MUX_CTRL_SCB__STATUS, CYREG_SCB3_STATUS
.set MUX_CTRL_SCB__TX_CTRL, CYREG_SCB3_TX_CTRL
.set MUX_CTRL_SCB__TX_FIFO_CTRL, CYREG_SCB3_TX_FIFO_CTRL
.set MUX_CTRL_SCB__TX_FIFO_STATUS, CYREG_SCB3_TX_FIFO_STATUS
.set MUX_CTRL_SCB__TX_FIFO_WR, CYREG_SCB3_TX_FIFO_WR
.set MUX_CTRL_SCB__UART_CTRL, CYREG_SCB3_UART_CTRL
.set MUX_CTRL_SCB__UART_FLOW_CTRL, CYREG_SCB3_UART_FLOW_CTRL
.set MUX_CTRL_SCB__UART_RX_CTRL, CYREG_SCB3_UART_RX_CTRL
.set MUX_CTRL_SCB__UART_RX_STATUS, CYREG_SCB3_UART_RX_STATUS
.set MUX_CTRL_SCB__UART_TX_CTRL, CYREG_SCB3_UART_TX_CTRL

/* MUX_CTRL_SCB_IRQ */
.set MUX_CTRL_SCB_IRQ__INTC_CLR_EN_REG, CYREG_CM0_ICER
.set MUX_CTRL_SCB_IRQ__INTC_CLR_PD_REG, CYREG_CM0_ICPR
.set MUX_CTRL_SCB_IRQ__INTC_MASK, 0x800
.set MUX_CTRL_SCB_IRQ__INTC_NUMBER, 11
.set MUX_CTRL_SCB_IRQ__INTC_PRIOR_MASK, 0xC0000000
.set MUX_CTRL_SCB_IRQ__INTC_PRIOR_NUM, 3
.set MUX_CTRL_SCB_IRQ__INTC_PRIOR_REG, CYREG_CM0_IPR2
.set MUX_CTRL_SCB_IRQ__INTC_SET_EN_REG, CYREG_CM0_ISER
.set MUX_CTRL_SCB_IRQ__INTC_SET_PD_REG, CYREG_CM0_ISPR

/* MUX_CTRL_SCBCLK */
.set MUX_CTRL_SCBCLK__CTRL_REGISTER, CYREG_PERI_PCLK_CTL3
.set MUX_CTRL_SCBCLK__DIV_ID, 0x00000003
.set MUX_CTRL_SCBCLK__DIV_REGISTER, CYREG_PERI_DIV_8_CTL3
.set MUX_CTRL_SCBCLK__PA_DIV_ID, 0x000000FF

/* MUX_CTRL_scl */
.set MUX_CTRL_scl__0__DR, CYREG_GPIO_PRT1_DR
.set MUX_CTRL_scl__0__DR_CLR, CYREG_GPIO_PRT1_DR_CLR
.set MUX_CTRL_scl__0__DR_INV, CYREG_GPIO_PRT1_DR_INV
.set MUX_CTRL_scl__0__DR_SET, CYREG_GPIO_PRT1_DR_SET
.set MUX_CTRL_scl__0__HSIOM, CYREG_HSIOM_PORT_SEL1
.set MUX_CTRL_scl__0__HSIOM_GPIO, 0
.set MUX_CTRL_scl__0__HSIOM_I2C, 15
.set MUX_CTRL_scl__0__HSIOM_I2C_SCL, 15
.set MUX_CTRL_scl__0__HSIOM_MASK, 0x00000F00
.set MUX_CTRL_scl__0__HSIOM_SHIFT, 8
.set MUX_CTRL_scl__0__HSIOM_SPI, 14
.set MUX_CTRL_scl__0__HSIOM_SPI_MOSI, 14
.set MUX_CTRL_scl__0__HSIOM_UART, 10
.set MUX_CTRL_scl__0__HSIOM_UART_CTS, 10
.set MUX_CTRL_scl__0__INTCFG, CYREG_GPIO_PRT1_INTR_CFG
.set MUX_CTRL_scl__0__INTR, CYREG_GPIO_PRT1_INTR
.set MUX_CTRL_scl__0__INTR_CFG, CYREG_GPIO_PRT1_INTR_CFG
.set MUX_CTRL_scl__0__INTSTAT, CYREG_GPIO_PRT1_INTR
.set MUX_CTRL_scl__0__MASK, 0x04
.set MUX_CTRL_scl__0__PC, CYREG_GPIO_PRT1_PC
.set MUX_CTRL_scl__0__PC2, CYREG_GPIO_PRT1_PC2
.set MUX_CTRL_scl__0__PORT, 1
.set MUX_CTRL_scl__0__PS, CYREG_GPIO_PRT1_PS
.set MUX_CTRL_scl__0__SHIFT, 2
.set MUX_CTRL_scl__DR, CYREG_GPIO_PRT1_DR
.set MUX_CTRL_scl__DR_CLR, CYREG_GPIO_PRT1_DR_CLR
.set MUX_CTRL_scl__DR_INV, CYREG_GPIO_PRT1_DR_INV
.set MUX_CTRL_scl__DR_SET, CYREG_GPIO_PRT1_DR_SET
.set MUX_CTRL_scl__INTCFG, CYREG_GPIO_PRT1_INTR_CFG
.set MUX_CTRL_scl__INTR, CYREG_GPIO_PRT1_INTR
.set MUX_CTRL_scl__INTR_CFG, CYREG_GPIO_PRT1_INTR_CFG
.set MUX_CTRL_scl__INTSTAT, CYREG_GPIO_PRT1_INTR
.set MUX_CTRL_scl__MASK, 0x04
.set MUX_CTRL_scl__PC, CYREG_GPIO_PRT1_PC
.set MUX_CTRL_scl__PC2, CYREG_GPIO_PRT1_PC2
.set MUX_CTRL_scl__PORT, 1
.set MUX_CTRL_scl__PS, CYREG_GPIO_PRT1_PS
.set MUX_CTRL_scl__SHIFT, 2

/* MUX_CTRL_sda */
.set MUX_CTRL_sda__0__DR, CYREG_GPIO_PRT1_DR
.set MUX_CTRL_sda__0__DR_CLR, CYREG_GPIO_PRT1_DR_CLR
.set MUX_CTRL_sda__0__DR_INV, CYREG_GPIO_PRT1_DR_INV
.set MUX_CTRL_sda__0__DR_SET, CYREG_GPIO_PRT1_DR_SET
.set MUX_CTRL_sda__0__HSIOM, CYREG_HSIOM_PORT_SEL1
.set MUX_CTRL_sda__0__HSIOM_GPIO, 0
.set MUX_CTRL_sda__0__HSIOM_I2C, 15
.set MUX_CTRL_sda__0__HSIOM_I2C_SDA, 15
.set MUX_CTRL_sda__0__HSIOM_MASK, 0x0000F000
.set MUX_CTRL_sda__0__HSIOM_SHIFT, 12
.set MUX_CTRL_sda__0__HSIOM_SPI, 14
.set MUX_CTRL_sda__0__HSIOM_SPI_CLK, 14
.set MUX_CTRL_sda__0__HSIOM_UART, 10
.set MUX_CTRL_sda__0__HSIOM_UART_RTS, 10
.set MUX_CTRL_sda__0__INTCFG, CYREG_GPIO_PRT1_INTR_CFG
.set MUX_CTRL_sda__0__INTR, CYREG_GPIO_PRT1_INTR
.set MUX_CTRL_sda__0__INTR_CFG, CYREG_GPIO_PRT1_INTR_CFG
.set MUX_CTRL_sda__0__INTSTAT, CYREG_GPIO_PRT1_INTR
.set MUX_CTRL_sda__0__MASK, 0x08
.set MUX_CTRL_sda__0__PC, CYREG_GPIO_PRT1_PC
.set MUX_CTRL_sda__0__PC2, CYREG_GPIO_PRT1_PC2
.set MUX_CTRL_sda__0__PORT, 1
.set MUX_CTRL_sda__0__PS, CYREG_GPIO_PRT1_PS
.set MUX_CTRL_sda__0__SHIFT, 3
.set MUX_CTRL_sda__DR, CYREG_GPIO_PRT1_DR
.set MUX_CTRL_sda__DR_CLR, CYREG_GPIO_PRT1_DR_CLR
.set MUX_CTRL_sda__DR_INV, CYREG_GPIO_PRT1_DR_INV
.set MUX_CTRL_sda__DR_SET, CYREG_GPIO_PRT1_DR_SET
.set MUX_CTRL_sda__INTCFG, CYREG_GPIO_PRT1_INTR_CFG
.set MUX_CTRL_sda__INTR, CYREG_GPIO_PRT1_INTR
.set MUX_CTRL_sda__INTR_CFG, CYREG_GPIO_PRT1_INTR_CFG
.set MUX_CTRL_sda__INTSTAT, CYREG_GPIO_PRT1_INTR
.set MUX_CTRL_sda__MASK, 0x08
.set MUX_CTRL_sda__PC, CYREG_GPIO_PRT1_PC
.set MUX_CTRL_sda__PC2, CYREG_GPIO_PRT1_PC2
.set MUX_CTRL_sda__PORT, 1
.set MUX_CTRL_sda__PS, CYREG_GPIO_PRT1_PS
.set MUX_CTRL_sda__SHIFT, 3

/* VSEL1_P1 */
.set VSEL1_P1__0__DR, CYREG_GPIO_PRT0_DR
.set VSEL1_P1__0__DR_CLR, CYREG_GPIO_PRT0_DR_CLR
.set VSEL1_P1__0__DR_INV, CYREG_GPIO_PRT0_DR_INV
.set VSEL1_P1__0__DR_SET, CYREG_GPIO_PRT0_DR_SET
.set VSEL1_P1__0__HSIOM, CYREG_HSIOM_PORT_SEL0
.set VSEL1_P1__0__HSIOM_MASK, 0x000000F0
.set VSEL1_P1__0__HSIOM_SHIFT, 4
.set VSEL1_P1__0__INTCFG, CYREG_GPIO_PRT0_INTR_CFG
.set VSEL1_P1__0__INTR, CYREG_GPIO_PRT0_INTR
.set VSEL1_P1__0__INTR_CFG, CYREG_GPIO_PRT0_INTR_CFG
.set VSEL1_P1__0__INTSTAT, CYREG_GPIO_PRT0_INTR
.set VSEL1_P1__0__MASK, 0x02
.set VSEL1_P1__0__PC, CYREG_GPIO_PRT0_PC
.set VSEL1_P1__0__PC2, CYREG_GPIO_PRT0_PC2
.set VSEL1_P1__0__PORT, 0
.set VSEL1_P1__0__PS, CYREG_GPIO_PRT0_PS
.set VSEL1_P1__0__SHIFT, 1
.set VSEL1_P1__DR, CYREG_GPIO_PRT0_DR
.set VSEL1_P1__DR_CLR, CYREG_GPIO_PRT0_DR_CLR
.set VSEL1_P1__DR_INV, CYREG_GPIO_PRT0_DR_INV
.set VSEL1_P1__DR_SET, CYREG_GPIO_PRT0_DR_SET
.set VSEL1_P1__INTCFG, CYREG_GPIO_PRT0_INTR_CFG
.set VSEL1_P1__INTR, CYREG_GPIO_PRT0_INTR
.set VSEL1_P1__INTR_CFG, CYREG_GPIO_PRT0_INTR_CFG
.set VSEL1_P1__INTSTAT, CYREG_GPIO_PRT0_INTR
.set VSEL1_P1__MASK, 0x02
.set VSEL1_P1__PC, CYREG_GPIO_PRT0_PC
.set VSEL1_P1__PC2, CYREG_GPIO_PRT0_PC2
.set VSEL1_P1__PORT, 0
.set VSEL1_P1__PS, CYREG_GPIO_PRT0_PS
.set VSEL1_P1__SHIFT, 1

/* VSEL2_P1 */
.set VSEL2_P1__0__DR, CYREG_GPIO_PRT0_DR
.set VSEL2_P1__0__DR_CLR, CYREG_GPIO_PRT0_DR_CLR
.set VSEL2_P1__0__DR_INV, CYREG_GPIO_PRT0_DR_INV
.set VSEL2_P1__0__DR_SET, CYREG_GPIO_PRT0_DR_SET
.set VSEL2_P1__0__HSIOM, CYREG_HSIOM_PORT_SEL0
.set VSEL2_P1__0__HSIOM_MASK, 0x0000000F
.set VSEL2_P1__0__HSIOM_SHIFT, 0
.set VSEL2_P1__0__INTCFG, CYREG_GPIO_PRT0_INTR_CFG
.set VSEL2_P1__0__INTR, CYREG_GPIO_PRT0_INTR
.set VSEL2_P1__0__INTR_CFG, CYREG_GPIO_PRT0_INTR_CFG
.set VSEL2_P1__0__INTSTAT, CYREG_GPIO_PRT0_INTR
.set VSEL2_P1__0__MASK, 0x01
.set VSEL2_P1__0__PC, CYREG_GPIO_PRT0_PC
.set VSEL2_P1__0__PC2, CYREG_GPIO_PRT0_PC2
.set VSEL2_P1__0__PORT, 0
.set VSEL2_P1__0__PS, CYREG_GPIO_PRT0_PS
.set VSEL2_P1__0__SHIFT, 0
.set VSEL2_P1__DR, CYREG_GPIO_PRT0_DR
.set VSEL2_P1__DR_CLR, CYREG_GPIO_PRT0_DR_CLR
.set VSEL2_P1__DR_INV, CYREG_GPIO_PRT0_DR_INV
.set VSEL2_P1__DR_SET, CYREG_GPIO_PRT0_DR_SET
.set VSEL2_P1__INTCFG, CYREG_GPIO_PRT0_INTR_CFG
.set VSEL2_P1__INTR, CYREG_GPIO_PRT0_INTR
.set VSEL2_P1__INTR_CFG, CYREG_GPIO_PRT0_INTR_CFG
.set VSEL2_P1__INTSTAT, CYREG_GPIO_PRT0_INTR
.set VSEL2_P1__MASK, 0x01
.set VSEL2_P1__PC, CYREG_GPIO_PRT0_PC
.set VSEL2_P1__PC2, CYREG_GPIO_PRT0_PC2
.set VSEL2_P1__PORT, 0
.set VSEL2_P1__PS, CYREG_GPIO_PRT0_PS
.set VSEL2_P1__SHIFT, 0

/* PGOOD_LED */
.set PGOOD_LED__0__DR, CYREG_GPIO_PRT2_DR
.set PGOOD_LED__0__DR_CLR, CYREG_GPIO_PRT2_DR_CLR
.set PGOOD_LED__0__DR_INV, CYREG_GPIO_PRT2_DR_INV
.set PGOOD_LED__0__DR_SET, CYREG_GPIO_PRT2_DR_SET
.set PGOOD_LED__0__HSIOM, CYREG_HSIOM_PORT_SEL2
.set PGOOD_LED__0__HSIOM_MASK, 0x000F0000
.set PGOOD_LED__0__HSIOM_SHIFT, 16
.set PGOOD_LED__0__INTCFG, CYREG_GPIO_PRT2_INTR_CFG
.set PGOOD_LED__0__INTR, CYREG_GPIO_PRT2_INTR
.set PGOOD_LED__0__INTR_CFG, CYREG_GPIO_PRT2_INTR_CFG
.set PGOOD_LED__0__INTSTAT, CYREG_GPIO_PRT2_INTR
.set PGOOD_LED__0__MASK, 0x10
.set PGOOD_LED__0__PC, CYREG_GPIO_PRT2_PC
.set PGOOD_LED__0__PC2, CYREG_GPIO_PRT2_PC2
.set PGOOD_LED__0__PORT, 2
.set PGOOD_LED__0__PS, CYREG_GPIO_PRT2_PS
.set PGOOD_LED__0__SHIFT, 4
.set PGOOD_LED__DR, CYREG_GPIO_PRT2_DR
.set PGOOD_LED__DR_CLR, CYREG_GPIO_PRT2_DR_CLR
.set PGOOD_LED__DR_INV, CYREG_GPIO_PRT2_DR_INV
.set PGOOD_LED__DR_SET, CYREG_GPIO_PRT2_DR_SET
.set PGOOD_LED__INTCFG, CYREG_GPIO_PRT2_INTR_CFG
.set PGOOD_LED__INTR, CYREG_GPIO_PRT2_INTR
.set PGOOD_LED__INTR_CFG, CYREG_GPIO_PRT2_INTR_CFG
.set PGOOD_LED__INTSTAT, CYREG_GPIO_PRT2_INTR
.set PGOOD_LED__MASK, 0x10
.set PGOOD_LED__PC, CYREG_GPIO_PRT2_PC
.set PGOOD_LED__PC2, CYREG_GPIO_PRT2_PC2
.set PGOOD_LED__PORT, 2
.set PGOOD_LED__PS, CYREG_GPIO_PRT2_PS
.set PGOOD_LED__SHIFT, 4

/* SMBALERTB */
.set SMBALERTB__0__DR, CYREG_GPIO_PRT3_DR
.set SMBALERTB__0__DR_CLR, CYREG_GPIO_PRT3_DR_CLR
.set SMBALERTB__0__DR_INV, CYREG_GPIO_PRT3_DR_INV
.set SMBALERTB__0__DR_SET, CYREG_GPIO_PRT3_DR_SET
.set SMBALERTB__0__HSIOM, CYREG_HSIOM_PORT_SEL3
.set SMBALERTB__0__HSIOM_MASK, 0x0F000000
.set SMBALERTB__0__HSIOM_SHIFT, 24
.set SMBALERTB__0__INTCFG, CYREG_GPIO_PRT3_INTR_CFG
.set SMBALERTB__0__INTR, CYREG_GPIO_PRT3_INTR
.set SMBALERTB__0__INTR_CFG, CYREG_GPIO_PRT3_INTR_CFG
.set SMBALERTB__0__INTSTAT, CYREG_GPIO_PRT3_INTR
.set SMBALERTB__0__MASK, 0x40
.set SMBALERTB__0__PC, CYREG_GPIO_PRT3_PC
.set SMBALERTB__0__PC2, CYREG_GPIO_PRT3_PC2
.set SMBALERTB__0__PORT, 3
.set SMBALERTB__0__PS, CYREG_GPIO_PRT3_PS
.set SMBALERTB__0__SHIFT, 6
.set SMBALERTB__DR, CYREG_GPIO_PRT3_DR
.set SMBALERTB__DR_CLR, CYREG_GPIO_PRT3_DR_CLR
.set SMBALERTB__DR_INV, CYREG_GPIO_PRT3_DR_INV
.set SMBALERTB__DR_SET, CYREG_GPIO_PRT3_DR_SET
.set SMBALERTB__INTCFG, CYREG_GPIO_PRT3_INTR_CFG
.set SMBALERTB__INTR, CYREG_GPIO_PRT3_INTR
.set SMBALERTB__INTR_CFG, CYREG_GPIO_PRT3_INTR_CFG
.set SMBALERTB__INTSTAT, CYREG_GPIO_PRT3_INTR
.set SMBALERTB__MASK, 0x40
.set SMBALERTB__PC, CYREG_GPIO_PRT3_PC
.set SMBALERTB__PC2, CYREG_GPIO_PRT3_PC2
.set SMBALERTB__PORT, 3
.set SMBALERTB__PS, CYREG_GPIO_PRT3_PS
.set SMBALERTB__SHIFT, 6

/* I2C_master_SCB */
.set I2C_master_SCB__CMD_RESP_CTRL, CYREG_SCB2_CMD_RESP_CTRL
.set I2C_master_SCB__CMD_RESP_STATUS, CYREG_SCB2_CMD_RESP_STATUS
.set I2C_master_SCB__CTRL, CYREG_SCB2_CTRL
.set I2C_master_SCB__EZ_DATA0, CYREG_SCB2_EZ_DATA0
.set I2C_master_SCB__EZ_DATA1, CYREG_SCB2_EZ_DATA1
.set I2C_master_SCB__EZ_DATA10, CYREG_SCB2_EZ_DATA10
.set I2C_master_SCB__EZ_DATA100, CYREG_SCB2_EZ_DATA100
.set I2C_master_SCB__EZ_DATA101, CYREG_SCB2_EZ_DATA101
.set I2C_master_SCB__EZ_DATA102, CYREG_SCB2_EZ_DATA102
.set I2C_master_SCB__EZ_DATA103, CYREG_SCB2_EZ_DATA103
.set I2C_master_SCB__EZ_DATA104, CYREG_SCB2_EZ_DATA104
.set I2C_master_SCB__EZ_DATA105, CYREG_SCB2_EZ_DATA105
.set I2C_master_SCB__EZ_DATA106, CYREG_SCB2_EZ_DATA106
.set I2C_master_SCB__EZ_DATA107, CYREG_SCB2_EZ_DATA107
.set I2C_master_SCB__EZ_DATA108, CYREG_SCB2_EZ_DATA108
.set I2C_master_SCB__EZ_DATA109, CYREG_SCB2_EZ_DATA109
.set I2C_master_SCB__EZ_DATA11, CYREG_SCB2_EZ_DATA11
.set I2C_master_SCB__EZ_DATA110, CYREG_SCB2_EZ_DATA110
.set I2C_master_SCB__EZ_DATA111, CYREG_SCB2_EZ_DATA111
.set I2C_master_SCB__EZ_DATA112, CYREG_SCB2_EZ_DATA112
.set I2C_master_SCB__EZ_DATA113, CYREG_SCB2_EZ_DATA113
.set I2C_master_SCB__EZ_DATA114, CYREG_SCB2_EZ_DATA114
.set I2C_master_SCB__EZ_DATA115, CYREG_SCB2_EZ_DATA115
.set I2C_master_SCB__EZ_DATA116, CYREG_SCB2_EZ_DATA116
.set I2C_master_SCB__EZ_DATA117, CYREG_SCB2_EZ_DATA117
.set I2C_master_SCB__EZ_DATA118, CYREG_SCB2_EZ_DATA118
.set I2C_master_SCB__EZ_DATA119, CYREG_SCB2_EZ_DATA119
.set I2C_master_SCB__EZ_DATA12, CYREG_SCB2_EZ_DATA12
.set I2C_master_SCB__EZ_DATA120, CYREG_SCB2_EZ_DATA120
.set I2C_master_SCB__EZ_DATA121, CYREG_SCB2_EZ_DATA121
.set I2C_master_SCB__EZ_DATA122, CYREG_SCB2_EZ_DATA122
.set I2C_master_SCB__EZ_DATA123, CYREG_SCB2_EZ_DATA123
.set I2C_master_SCB__EZ_DATA124, CYREG_SCB2_EZ_DATA124
.set I2C_master_SCB__EZ_DATA125, CYREG_SCB2_EZ_DATA125
.set I2C_master_SCB__EZ_DATA126, CYREG_SCB2_EZ_DATA126
.set I2C_master_SCB__EZ_DATA127, CYREG_SCB2_EZ_DATA127
.set I2C_master_SCB__EZ_DATA128, CYREG_SCB2_EZ_DATA128
.set I2C_master_SCB__EZ_DATA129, CYREG_SCB2_EZ_DATA129
.set I2C_master_SCB__EZ_DATA13, CYREG_SCB2_EZ_DATA13
.set I2C_master_SCB__EZ_DATA130, CYREG_SCB2_EZ_DATA130
.set I2C_master_SCB__EZ_DATA131, CYREG_SCB2_EZ_DATA131
.set I2C_master_SCB__EZ_DATA132, CYREG_SCB2_EZ_DATA132
.set I2C_master_SCB__EZ_DATA133, CYREG_SCB2_EZ_DATA133
.set I2C_master_SCB__EZ_DATA134, CYREG_SCB2_EZ_DATA134
.set I2C_master_SCB__EZ_DATA135, CYREG_SCB2_EZ_DATA135
.set I2C_master_SCB__EZ_DATA136, CYREG_SCB2_EZ_DATA136
.set I2C_master_SCB__EZ_DATA137, CYREG_SCB2_EZ_DATA137
.set I2C_master_SCB__EZ_DATA138, CYREG_SCB2_EZ_DATA138
.set I2C_master_SCB__EZ_DATA139, CYREG_SCB2_EZ_DATA139
.set I2C_master_SCB__EZ_DATA14, CYREG_SCB2_EZ_DATA14
.set I2C_master_SCB__EZ_DATA140, CYREG_SCB2_EZ_DATA140
.set I2C_master_SCB__EZ_DATA141, CYREG_SCB2_EZ_DATA141
.set I2C_master_SCB__EZ_DATA142, CYREG_SCB2_EZ_DATA142
.set I2C_master_SCB__EZ_DATA143, CYREG_SCB2_EZ_DATA143
.set I2C_master_SCB__EZ_DATA144, CYREG_SCB2_EZ_DATA144
.set I2C_master_SCB__EZ_DATA145, CYREG_SCB2_EZ_DATA145
.set I2C_master_SCB__EZ_DATA146, CYREG_SCB2_EZ_DATA146
.set I2C_master_SCB__EZ_DATA147, CYREG_SCB2_EZ_DATA147
.set I2C_master_SCB__EZ_DATA148, CYREG_SCB2_EZ_DATA148
.set I2C_master_SCB__EZ_DATA149, CYREG_SCB2_EZ_DATA149
.set I2C_master_SCB__EZ_DATA15, CYREG_SCB2_EZ_DATA15
.set I2C_master_SCB__EZ_DATA150, CYREG_SCB2_EZ_DATA150
.set I2C_master_SCB__EZ_DATA151, CYREG_SCB2_EZ_DATA151
.set I2C_master_SCB__EZ_DATA152, CYREG_SCB2_EZ_DATA152
.set I2C_master_SCB__EZ_DATA153, CYREG_SCB2_EZ_DATA153
.set I2C_master_SCB__EZ_DATA154, CYREG_SCB2_EZ_DATA154
.set I2C_master_SCB__EZ_DATA155, CYREG_SCB2_EZ_DATA155
.set I2C_master_SCB__EZ_DATA156, CYREG_SCB2_EZ_DATA156
.set I2C_master_SCB__EZ_DATA157, CYREG_SCB2_EZ_DATA157
.set I2C_master_SCB__EZ_DATA158, CYREG_SCB2_EZ_DATA158
.set I2C_master_SCB__EZ_DATA159, CYREG_SCB2_EZ_DATA159
.set I2C_master_SCB__EZ_DATA16, CYREG_SCB2_EZ_DATA16
.set I2C_master_SCB__EZ_DATA160, CYREG_SCB2_EZ_DATA160
.set I2C_master_SCB__EZ_DATA161, CYREG_SCB2_EZ_DATA161
.set I2C_master_SCB__EZ_DATA162, CYREG_SCB2_EZ_DATA162
.set I2C_master_SCB__EZ_DATA163, CYREG_SCB2_EZ_DATA163
.set I2C_master_SCB__EZ_DATA164, CYREG_SCB2_EZ_DATA164
.set I2C_master_SCB__EZ_DATA165, CYREG_SCB2_EZ_DATA165
.set I2C_master_SCB__EZ_DATA166, CYREG_SCB2_EZ_DATA166
.set I2C_master_SCB__EZ_DATA167, CYREG_SCB2_EZ_DATA167
.set I2C_master_SCB__EZ_DATA168, CYREG_SCB2_EZ_DATA168
.set I2C_master_SCB__EZ_DATA169, CYREG_SCB2_EZ_DATA169
.set I2C_master_SCB__EZ_DATA17, CYREG_SCB2_EZ_DATA17
.set I2C_master_SCB__EZ_DATA170, CYREG_SCB2_EZ_DATA170
.set I2C_master_SCB__EZ_DATA171, CYREG_SCB2_EZ_DATA171
.set I2C_master_SCB__EZ_DATA172, CYREG_SCB2_EZ_DATA172
.set I2C_master_SCB__EZ_DATA173, CYREG_SCB2_EZ_DATA173
.set I2C_master_SCB__EZ_DATA174, CYREG_SCB2_EZ_DATA174
.set I2C_master_SCB__EZ_DATA175, CYREG_SCB2_EZ_DATA175
.set I2C_master_SCB__EZ_DATA176, CYREG_SCB2_EZ_DATA176
.set I2C_master_SCB__EZ_DATA177, CYREG_SCB2_EZ_DATA177
.set I2C_master_SCB__EZ_DATA178, CYREG_SCB2_EZ_DATA178
.set I2C_master_SCB__EZ_DATA179, CYREG_SCB2_EZ_DATA179
.set I2C_master_SCB__EZ_DATA18, CYREG_SCB2_EZ_DATA18
.set I2C_master_SCB__EZ_DATA180, CYREG_SCB2_EZ_DATA180
.set I2C_master_SCB__EZ_DATA181, CYREG_SCB2_EZ_DATA181
.set I2C_master_SCB__EZ_DATA182, CYREG_SCB2_EZ_DATA182
.set I2C_master_SCB__EZ_DATA183, CYREG_SCB2_EZ_DATA183
.set I2C_master_SCB__EZ_DATA184, CYREG_SCB2_EZ_DATA184
.set I2C_master_SCB__EZ_DATA185, CYREG_SCB2_EZ_DATA185
.set I2C_master_SCB__EZ_DATA186, CYREG_SCB2_EZ_DATA186
.set I2C_master_SCB__EZ_DATA187, CYREG_SCB2_EZ_DATA187
.set I2C_master_SCB__EZ_DATA188, CYREG_SCB2_EZ_DATA188
.set I2C_master_SCB__EZ_DATA189, CYREG_SCB2_EZ_DATA189
.set I2C_master_SCB__EZ_DATA19, CYREG_SCB2_EZ_DATA19
.set I2C_master_SCB__EZ_DATA190, CYREG_SCB2_EZ_DATA190
.set I2C_master_SCB__EZ_DATA191, CYREG_SCB2_EZ_DATA191
.set I2C_master_SCB__EZ_DATA192, CYREG_SCB2_EZ_DATA192
.set I2C_master_SCB__EZ_DATA193, CYREG_SCB2_EZ_DATA193
.set I2C_master_SCB__EZ_DATA194, CYREG_SCB2_EZ_DATA194
.set I2C_master_SCB__EZ_DATA195, CYREG_SCB2_EZ_DATA195
.set I2C_master_SCB__EZ_DATA196, CYREG_SCB2_EZ_DATA196
.set I2C_master_SCB__EZ_DATA197, CYREG_SCB2_EZ_DATA197
.set I2C_master_SCB__EZ_DATA198, CYREG_SCB2_EZ_DATA198
.set I2C_master_SCB__EZ_DATA199, CYREG_SCB2_EZ_DATA199
.set I2C_master_SCB__EZ_DATA2, CYREG_SCB2_EZ_DATA2
.set I2C_master_SCB__EZ_DATA20, CYREG_SCB2_EZ_DATA20
.set I2C_master_SCB__EZ_DATA200, CYREG_SCB2_EZ_DATA200
.set I2C_master_SCB__EZ_DATA201, CYREG_SCB2_EZ_DATA201
.set I2C_master_SCB__EZ_DATA202, CYREG_SCB2_EZ_DATA202
.set I2C_master_SCB__EZ_DATA203, CYREG_SCB2_EZ_DATA203
.set I2C_master_SCB__EZ_DATA204, CYREG_SCB2_EZ_DATA204
.set I2C_master_SCB__EZ_DATA205, CYREG_SCB2_EZ_DATA205
.set I2C_master_SCB__EZ_DATA206, CYREG_SCB2_EZ_DATA206
.set I2C_master_SCB__EZ_DATA207, CYREG_SCB2_EZ_DATA207
.set I2C_master_SCB__EZ_DATA208, CYREG_SCB2_EZ_DATA208
.set I2C_master_SCB__EZ_DATA209, CYREG_SCB2_EZ_DATA209
.set I2C_master_SCB__EZ_DATA21, CYREG_SCB2_EZ_DATA21
.set I2C_master_SCB__EZ_DATA210, CYREG_SCB2_EZ_DATA210
.set I2C_master_SCB__EZ_DATA211, CYREG_SCB2_EZ_DATA211
.set I2C_master_SCB__EZ_DATA212, CYREG_SCB2_EZ_DATA212
.set I2C_master_SCB__EZ_DATA213, CYREG_SCB2_EZ_DATA213
.set I2C_master_SCB__EZ_DATA214, CYREG_SCB2_EZ_DATA214
.set I2C_master_SCB__EZ_DATA215, CYREG_SCB2_EZ_DATA215
.set I2C_master_SCB__EZ_DATA216, CYREG_SCB2_EZ_DATA216
.set I2C_master_SCB__EZ_DATA217, CYREG_SCB2_EZ_DATA217
.set I2C_master_SCB__EZ_DATA218, CYREG_SCB2_EZ_DATA218
.set I2C_master_SCB__EZ_DATA219, CYREG_SCB2_EZ_DATA219
.set I2C_master_SCB__EZ_DATA22, CYREG_SCB2_EZ_DATA22
.set I2C_master_SCB__EZ_DATA220, CYREG_SCB2_EZ_DATA220
.set I2C_master_SCB__EZ_DATA221, CYREG_SCB2_EZ_DATA221
.set I2C_master_SCB__EZ_DATA222, CYREG_SCB2_EZ_DATA222
.set I2C_master_SCB__EZ_DATA223, CYREG_SCB2_EZ_DATA223
.set I2C_master_SCB__EZ_DATA224, CYREG_SCB2_EZ_DATA224
.set I2C_master_SCB__EZ_DATA225, CYREG_SCB2_EZ_DATA225
.set I2C_master_SCB__EZ_DATA226, CYREG_SCB2_EZ_DATA226
.set I2C_master_SCB__EZ_DATA227, CYREG_SCB2_EZ_DATA227
.set I2C_master_SCB__EZ_DATA228, CYREG_SCB2_EZ_DATA228
.set I2C_master_SCB__EZ_DATA229, CYREG_SCB2_EZ_DATA229
.set I2C_master_SCB__EZ_DATA23, CYREG_SCB2_EZ_DATA23
.set I2C_master_SCB__EZ_DATA230, CYREG_SCB2_EZ_DATA230
.set I2C_master_SCB__EZ_DATA231, CYREG_SCB2_EZ_DATA231
.set I2C_master_SCB__EZ_DATA232, CYREG_SCB2_EZ_DATA232
.set I2C_master_SCB__EZ_DATA233, CYREG_SCB2_EZ_DATA233
.set I2C_master_SCB__EZ_DATA234, CYREG_SCB2_EZ_DATA234
.set I2C_master_SCB__EZ_DATA235, CYREG_SCB2_EZ_DATA235
.set I2C_master_SCB__EZ_DATA236, CYREG_SCB2_EZ_DATA236
.set I2C_master_SCB__EZ_DATA237, CYREG_SCB2_EZ_DATA237
.set I2C_master_SCB__EZ_DATA238, CYREG_SCB2_EZ_DATA238
.set I2C_master_SCB__EZ_DATA239, CYREG_SCB2_EZ_DATA239
.set I2C_master_SCB__EZ_DATA24, CYREG_SCB2_EZ_DATA24
.set I2C_master_SCB__EZ_DATA240, CYREG_SCB2_EZ_DATA240
.set I2C_master_SCB__EZ_DATA241, CYREG_SCB2_EZ_DATA241
.set I2C_master_SCB__EZ_DATA242, CYREG_SCB2_EZ_DATA242
.set I2C_master_SCB__EZ_DATA243, CYREG_SCB2_EZ_DATA243
.set I2C_master_SCB__EZ_DATA244, CYREG_SCB2_EZ_DATA244
.set I2C_master_SCB__EZ_DATA245, CYREG_SCB2_EZ_DATA245
.set I2C_master_SCB__EZ_DATA246, CYREG_SCB2_EZ_DATA246
.set I2C_master_SCB__EZ_DATA247, CYREG_SCB2_EZ_DATA247
.set I2C_master_SCB__EZ_DATA248, CYREG_SCB2_EZ_DATA248
.set I2C_master_SCB__EZ_DATA249, CYREG_SCB2_EZ_DATA249
.set I2C_master_SCB__EZ_DATA25, CYREG_SCB2_EZ_DATA25
.set I2C_master_SCB__EZ_DATA250, CYREG_SCB2_EZ_DATA250
.set I2C_master_SCB__EZ_DATA251, CYREG_SCB2_EZ_DATA251
.set I2C_master_SCB__EZ_DATA252, CYREG_SCB2_EZ_DATA252
.set I2C_master_SCB__EZ_DATA253, CYREG_SCB2_EZ_DATA253
.set I2C_master_SCB__EZ_DATA254, CYREG_SCB2_EZ_DATA254
.set I2C_master_SCB__EZ_DATA255, CYREG_SCB2_EZ_DATA255
.set I2C_master_SCB__EZ_DATA26, CYREG_SCB2_EZ_DATA26
.set I2C_master_SCB__EZ_DATA27, CYREG_SCB2_EZ_DATA27
.set I2C_master_SCB__EZ_DATA28, CYREG_SCB2_EZ_DATA28
.set I2C_master_SCB__EZ_DATA29, CYREG_SCB2_EZ_DATA29
.set I2C_master_SCB__EZ_DATA3, CYREG_SCB2_EZ_DATA3
.set I2C_master_SCB__EZ_DATA30, CYREG_SCB2_EZ_DATA30
.set I2C_master_SCB__EZ_DATA31, CYREG_SCB2_EZ_DATA31
.set I2C_master_SCB__EZ_DATA32, CYREG_SCB2_EZ_DATA32
.set I2C_master_SCB__EZ_DATA33, CYREG_SCB2_EZ_DATA33
.set I2C_master_SCB__EZ_DATA34, CYREG_SCB2_EZ_DATA34
.set I2C_master_SCB__EZ_DATA35, CYREG_SCB2_EZ_DATA35
.set I2C_master_SCB__EZ_DATA36, CYREG_SCB2_EZ_DATA36
.set I2C_master_SCB__EZ_DATA37, CYREG_SCB2_EZ_DATA37
.set I2C_master_SCB__EZ_DATA38, CYREG_SCB2_EZ_DATA38
.set I2C_master_SCB__EZ_DATA39, CYREG_SCB2_EZ_DATA39
.set I2C_master_SCB__EZ_DATA4, CYREG_SCB2_EZ_DATA4
.set I2C_master_SCB__EZ_DATA40, CYREG_SCB2_EZ_DATA40
.set I2C_master_SCB__EZ_DATA41, CYREG_SCB2_EZ_DATA41
.set I2C_master_SCB__EZ_DATA42, CYREG_SCB2_EZ_DATA42
.set I2C_master_SCB__EZ_DATA43, CYREG_SCB2_EZ_DATA43
.set I2C_master_SCB__EZ_DATA44, CYREG_SCB2_EZ_DATA44
.set I2C_master_SCB__EZ_DATA45, CYREG_SCB2_EZ_DATA45
.set I2C_master_SCB__EZ_DATA46, CYREG_SCB2_EZ_DATA46
.set I2C_master_SCB__EZ_DATA47, CYREG_SCB2_EZ_DATA47
.set I2C_master_SCB__EZ_DATA48, CYREG_SCB2_EZ_DATA48
.set I2C_master_SCB__EZ_DATA49, CYREG_SCB2_EZ_DATA49
.set I2C_master_SCB__EZ_DATA5, CYREG_SCB2_EZ_DATA5
.set I2C_master_SCB__EZ_DATA50, CYREG_SCB2_EZ_DATA50
.set I2C_master_SCB__EZ_DATA51, CYREG_SCB2_EZ_DATA51
.set I2C_master_SCB__EZ_DATA52, CYREG_SCB2_EZ_DATA52
.set I2C_master_SCB__EZ_DATA53, CYREG_SCB2_EZ_DATA53
.set I2C_master_SCB__EZ_DATA54, CYREG_SCB2_EZ_DATA54
.set I2C_master_SCB__EZ_DATA55, CYREG_SCB2_EZ_DATA55
.set I2C_master_SCB__EZ_DATA56, CYREG_SCB2_EZ_DATA56
.set I2C_master_SCB__EZ_DATA57, CYREG_SCB2_EZ_DATA57
.set I2C_master_SCB__EZ_DATA58, CYREG_SCB2_EZ_DATA58
.set I2C_master_SCB__EZ_DATA59, CYREG_SCB2_EZ_DATA59
.set I2C_master_SCB__EZ_DATA6, CYREG_SCB2_EZ_DATA6
.set I2C_master_SCB__EZ_DATA60, CYREG_SCB2_EZ_DATA60
.set I2C_master_SCB__EZ_DATA61, CYREG_SCB2_EZ_DATA61
.set I2C_master_SCB__EZ_DATA62, CYREG_SCB2_EZ_DATA62
.set I2C_master_SCB__EZ_DATA63, CYREG_SCB2_EZ_DATA63
.set I2C_master_SCB__EZ_DATA64, CYREG_SCB2_EZ_DATA64
.set I2C_master_SCB__EZ_DATA65, CYREG_SCB2_EZ_DATA65
.set I2C_master_SCB__EZ_DATA66, CYREG_SCB2_EZ_DATA66
.set I2C_master_SCB__EZ_DATA67, CYREG_SCB2_EZ_DATA67
.set I2C_master_SCB__EZ_DATA68, CYREG_SCB2_EZ_DATA68
.set I2C_master_SCB__EZ_DATA69, CYREG_SCB2_EZ_DATA69
.set I2C_master_SCB__EZ_DATA7, CYREG_SCB2_EZ_DATA7
.set I2C_master_SCB__EZ_DATA70, CYREG_SCB2_EZ_DATA70
.set I2C_master_SCB__EZ_DATA71, CYREG_SCB2_EZ_DATA71
.set I2C_master_SCB__EZ_DATA72, CYREG_SCB2_EZ_DATA72
.set I2C_master_SCB__EZ_DATA73, CYREG_SCB2_EZ_DATA73
.set I2C_master_SCB__EZ_DATA74, CYREG_SCB2_EZ_DATA74
.set I2C_master_SCB__EZ_DATA75, CYREG_SCB2_EZ_DATA75
.set I2C_master_SCB__EZ_DATA76, CYREG_SCB2_EZ_DATA76
.set I2C_master_SCB__EZ_DATA77, CYREG_SCB2_EZ_DATA77
.set I2C_master_SCB__EZ_DATA78, CYREG_SCB2_EZ_DATA78
.set I2C_master_SCB__EZ_DATA79, CYREG_SCB2_EZ_DATA79
.set I2C_master_SCB__EZ_DATA8, CYREG_SCB2_EZ_DATA8
.set I2C_master_SCB__EZ_DATA80, CYREG_SCB2_EZ_DATA80
.set I2C_master_SCB__EZ_DATA81, CYREG_SCB2_EZ_DATA81
.set I2C_master_SCB__EZ_DATA82, CYREG_SCB2_EZ_DATA82
.set I2C_master_SCB__EZ_DATA83, CYREG_SCB2_EZ_DATA83
.set I2C_master_SCB__EZ_DATA84, CYREG_SCB2_EZ_DATA84
.set I2C_master_SCB__EZ_DATA85, CYREG_SCB2_EZ_DATA85
.set I2C_master_SCB__EZ_DATA86, CYREG_SCB2_EZ_DATA86
.set I2C_master_SCB__EZ_DATA87, CYREG_SCB2_EZ_DATA87
.set I2C_master_SCB__EZ_DATA88, CYREG_SCB2_EZ_DATA88
.set I2C_master_SCB__EZ_DATA89, CYREG_SCB2_EZ_DATA89
.set I2C_master_SCB__EZ_DATA9, CYREG_SCB2_EZ_DATA9
.set I2C_master_SCB__EZ_DATA90, CYREG_SCB2_EZ_DATA90
.set I2C_master_SCB__EZ_DATA91, CYREG_SCB2_EZ_DATA91
.set I2C_master_SCB__EZ_DATA92, CYREG_SCB2_EZ_DATA92
.set I2C_master_SCB__EZ_DATA93, CYREG_SCB2_EZ_DATA93
.set I2C_master_SCB__EZ_DATA94, CYREG_SCB2_EZ_DATA94
.set I2C_master_SCB__EZ_DATA95, CYREG_SCB2_EZ_DATA95
.set I2C_master_SCB__EZ_DATA96, CYREG_SCB2_EZ_DATA96
.set I2C_master_SCB__EZ_DATA97, CYREG_SCB2_EZ_DATA97
.set I2C_master_SCB__EZ_DATA98, CYREG_SCB2_EZ_DATA98
.set I2C_master_SCB__EZ_DATA99, CYREG_SCB2_EZ_DATA99
.set I2C_master_SCB__I2C_CFG, CYREG_SCB2_I2C_CFG
.set I2C_master_SCB__I2C_CTRL, CYREG_SCB2_I2C_CTRL
.set I2C_master_SCB__I2C_M_CMD, CYREG_SCB2_I2C_M_CMD
.set I2C_master_SCB__I2C_S_CMD, CYREG_SCB2_I2C_S_CMD
.set I2C_master_SCB__I2C_STATUS, CYREG_SCB2_I2C_STATUS
.set I2C_master_SCB__INTR_CAUSE, CYREG_SCB2_INTR_CAUSE
.set I2C_master_SCB__INTR_I2C_EC, CYREG_SCB2_INTR_I2C_EC
.set I2C_master_SCB__INTR_I2C_EC_MASK, CYREG_SCB2_INTR_I2C_EC_MASK
.set I2C_master_SCB__INTR_I2C_EC_MASKED, CYREG_SCB2_INTR_I2C_EC_MASKED
.set I2C_master_SCB__INTR_M, CYREG_SCB2_INTR_M
.set I2C_master_SCB__INTR_M_MASK, CYREG_SCB2_INTR_M_MASK
.set I2C_master_SCB__INTR_M_MASKED, CYREG_SCB2_INTR_M_MASKED
.set I2C_master_SCB__INTR_M_SET, CYREG_SCB2_INTR_M_SET
.set I2C_master_SCB__INTR_RX, CYREG_SCB2_INTR_RX
.set I2C_master_SCB__INTR_RX_MASK, CYREG_SCB2_INTR_RX_MASK
.set I2C_master_SCB__INTR_RX_MASKED, CYREG_SCB2_INTR_RX_MASKED
.set I2C_master_SCB__INTR_RX_SET, CYREG_SCB2_INTR_RX_SET
.set I2C_master_SCB__INTR_S, CYREG_SCB2_INTR_S
.set I2C_master_SCB__INTR_S_MASK, CYREG_SCB2_INTR_S_MASK
.set I2C_master_SCB__INTR_S_MASKED, CYREG_SCB2_INTR_S_MASKED
.set I2C_master_SCB__INTR_S_SET, CYREG_SCB2_INTR_S_SET
.set I2C_master_SCB__INTR_SPI_EC, CYREG_SCB2_INTR_SPI_EC
.set I2C_master_SCB__INTR_SPI_EC_MASK, CYREG_SCB2_INTR_SPI_EC_MASK
.set I2C_master_SCB__INTR_SPI_EC_MASKED, CYREG_SCB2_INTR_SPI_EC_MASKED
.set I2C_master_SCB__INTR_TX, CYREG_SCB2_INTR_TX
.set I2C_master_SCB__INTR_TX_MASK, CYREG_SCB2_INTR_TX_MASK
.set I2C_master_SCB__INTR_TX_MASKED, CYREG_SCB2_INTR_TX_MASKED
.set I2C_master_SCB__INTR_TX_SET, CYREG_SCB2_INTR_TX_SET
.set I2C_master_SCB__RX_CTRL, CYREG_SCB2_RX_CTRL
.set I2C_master_SCB__RX_FIFO_CTRL, CYREG_SCB2_RX_FIFO_CTRL
.set I2C_master_SCB__RX_FIFO_RD, CYREG_SCB2_RX_FIFO_RD
.set I2C_master_SCB__RX_FIFO_RD_SILENT, CYREG_SCB2_RX_FIFO_RD_SILENT
.set I2C_master_SCB__RX_FIFO_STATUS, CYREG_SCB2_RX_FIFO_STATUS
.set I2C_master_SCB__RX_MATCH, CYREG_SCB2_RX_MATCH
.set I2C_master_SCB__SPI_CTRL, CYREG_SCB2_SPI_CTRL
.set I2C_master_SCB__SPI_STATUS, CYREG_SCB2_SPI_STATUS
.set I2C_master_SCB__SS0_POSISTION, 0
.set I2C_master_SCB__SS1_POSISTION, 1
.set I2C_master_SCB__SS2_POSISTION, 2
.set I2C_master_SCB__SS3_POSISTION, 3
.set I2C_master_SCB__STATUS, CYREG_SCB2_STATUS
.set I2C_master_SCB__TX_CTRL, CYREG_SCB2_TX_CTRL
.set I2C_master_SCB__TX_FIFO_CTRL, CYREG_SCB2_TX_FIFO_CTRL
.set I2C_master_SCB__TX_FIFO_STATUS, CYREG_SCB2_TX_FIFO_STATUS
.set I2C_master_SCB__TX_FIFO_WR, CYREG_SCB2_TX_FIFO_WR
.set I2C_master_SCB__UART_CTRL, CYREG_SCB2_UART_CTRL
.set I2C_master_SCB__UART_FLOW_CTRL, CYREG_SCB2_UART_FLOW_CTRL
.set I2C_master_SCB__UART_RX_CTRL, CYREG_SCB2_UART_RX_CTRL
.set I2C_master_SCB__UART_RX_STATUS, CYREG_SCB2_UART_RX_STATUS
.set I2C_master_SCB__UART_TX_CTRL, CYREG_SCB2_UART_TX_CTRL

/* I2C_master_SCB_IRQ */
.set I2C_master_SCB_IRQ__INTC_CLR_EN_REG, CYREG_CM0_ICER
.set I2C_master_SCB_IRQ__INTC_CLR_PD_REG, CYREG_CM0_ICPR
.set I2C_master_SCB_IRQ__INTC_MASK, 0x400
.set I2C_master_SCB_IRQ__INTC_NUMBER, 10
.set I2C_master_SCB_IRQ__INTC_PRIOR_MASK, 0xC00000
.set I2C_master_SCB_IRQ__INTC_PRIOR_NUM, 3
.set I2C_master_SCB_IRQ__INTC_PRIOR_REG, CYREG_CM0_IPR2
.set I2C_master_SCB_IRQ__INTC_SET_EN_REG, CYREG_CM0_ISER
.set I2C_master_SCB_IRQ__INTC_SET_PD_REG, CYREG_CM0_ISPR

/* I2C_master_SCBCLK */
.set I2C_master_SCBCLK__CTRL_REGISTER, CYREG_PERI_PCLK_CTL2
.set I2C_master_SCBCLK__DIV_ID, 0x00000001
.set I2C_master_SCBCLK__DIV_REGISTER, CYREG_PERI_DIV_8_CTL1
.set I2C_master_SCBCLK__PA_DIV_ID, 0x000000FF

/* I2C_master_scl */
.set I2C_master_scl__0__DR, CYREG_GPIO_PRT3_DR
.set I2C_master_scl__0__DR_CLR, CYREG_GPIO_PRT3_DR_CLR
.set I2C_master_scl__0__DR_INV, CYREG_GPIO_PRT3_DR_INV
.set I2C_master_scl__0__DR_SET, CYREG_GPIO_PRT3_DR_SET
.set I2C_master_scl__0__HSIOM, CYREG_HSIOM_PORT_SEL3
.set I2C_master_scl__0__HSIOM_GPIO, 0
.set I2C_master_scl__0__HSIOM_I2C, 15
.set I2C_master_scl__0__HSIOM_I2C_SCL, 15
.set I2C_master_scl__0__HSIOM_MASK, 0x00F00000
.set I2C_master_scl__0__HSIOM_SHIFT, 20
.set I2C_master_scl__0__HSIOM_SPI, 14
.set I2C_master_scl__0__HSIOM_SPI_CLK, 14
.set I2C_master_scl__0__HSIOM_UART, 10
.set I2C_master_scl__0__HSIOM_UART_RTS, 10
.set I2C_master_scl__0__INTCFG, CYREG_GPIO_PRT3_INTR_CFG
.set I2C_master_scl__0__INTR, CYREG_GPIO_PRT3_INTR
.set I2C_master_scl__0__INTR_CFG, CYREG_GPIO_PRT3_INTR_CFG
.set I2C_master_scl__0__INTSTAT, CYREG_GPIO_PRT3_INTR
.set I2C_master_scl__0__MASK, 0x20
.set I2C_master_scl__0__PC, CYREG_GPIO_PRT3_PC
.set I2C_master_scl__0__PC2, CYREG_GPIO_PRT3_PC2
.set I2C_master_scl__0__PORT, 3
.set I2C_master_scl__0__PS, CYREG_GPIO_PRT3_PS
.set I2C_master_scl__0__SHIFT, 5
.set I2C_master_scl__DR, CYREG_GPIO_PRT3_DR
.set I2C_master_scl__DR_CLR, CYREG_GPIO_PRT3_DR_CLR
.set I2C_master_scl__DR_INV, CYREG_GPIO_PRT3_DR_INV
.set I2C_master_scl__DR_SET, CYREG_GPIO_PRT3_DR_SET
.set I2C_master_scl__INTCFG, CYREG_GPIO_PRT3_INTR_CFG
.set I2C_master_scl__INTR, CYREG_GPIO_PRT3_INTR
.set I2C_master_scl__INTR_CFG, CYREG_GPIO_PRT3_INTR_CFG
.set I2C_master_scl__INTSTAT, CYREG_GPIO_PRT3_INTR
.set I2C_master_scl__MASK, 0x20
.set I2C_master_scl__PC, CYREG_GPIO_PRT3_PC
.set I2C_master_scl__PC2, CYREG_GPIO_PRT3_PC2
.set I2C_master_scl__PORT, 3
.set I2C_master_scl__PS, CYREG_GPIO_PRT3_PS
.set I2C_master_scl__SHIFT, 5

/* I2C_master_sda */
.set I2C_master_sda__0__DR, CYREG_GPIO_PRT3_DR
.set I2C_master_sda__0__DR_CLR, CYREG_GPIO_PRT3_DR_CLR
.set I2C_master_sda__0__DR_INV, CYREG_GPIO_PRT3_DR_INV
.set I2C_master_sda__0__DR_SET, CYREG_GPIO_PRT3_DR_SET
.set I2C_master_sda__0__HSIOM, CYREG_HSIOM_PORT_SEL3
.set I2C_master_sda__0__HSIOM_GPIO, 0
.set I2C_master_sda__0__HSIOM_I2C, 15
.set I2C_master_sda__0__HSIOM_I2C_SDA, 15
.set I2C_master_sda__0__HSIOM_MASK, 0x000F0000
.set I2C_master_sda__0__HSIOM_SHIFT, 16
.set I2C_master_sda__0__HSIOM_SPI, 14
.set I2C_master_sda__0__HSIOM_SPI_MOSI, 14
.set I2C_master_sda__0__HSIOM_UART, 10
.set I2C_master_sda__0__HSIOM_UART_CTS, 10
.set I2C_master_sda__0__INTCFG, CYREG_GPIO_PRT3_INTR_CFG
.set I2C_master_sda__0__INTR, CYREG_GPIO_PRT3_INTR
.set I2C_master_sda__0__INTR_CFG, CYREG_GPIO_PRT3_INTR_CFG
.set I2C_master_sda__0__INTSTAT, CYREG_GPIO_PRT3_INTR
.set I2C_master_sda__0__MASK, 0x10
.set I2C_master_sda__0__PC, CYREG_GPIO_PRT3_PC
.set I2C_master_sda__0__PC2, CYREG_GPIO_PRT3_PC2
.set I2C_master_sda__0__PORT, 3
.set I2C_master_sda__0__PS, CYREG_GPIO_PRT3_PS
.set I2C_master_sda__0__SHIFT, 4
.set I2C_master_sda__DR, CYREG_GPIO_PRT3_DR
.set I2C_master_sda__DR_CLR, CYREG_GPIO_PRT3_DR_CLR
.set I2C_master_sda__DR_INV, CYREG_GPIO_PRT3_DR_INV
.set I2C_master_sda__DR_SET, CYREG_GPIO_PRT3_DR_SET
.set I2C_master_sda__INTCFG, CYREG_GPIO_PRT3_INTR_CFG
.set I2C_master_sda__INTR, CYREG_GPIO_PRT3_INTR
.set I2C_master_sda__INTR_CFG, CYREG_GPIO_PRT3_INTR_CFG
.set I2C_master_sda__INTSTAT, CYREG_GPIO_PRT3_INTR
.set I2C_master_sda__MASK, 0x10
.set I2C_master_sda__PC, CYREG_GPIO_PRT3_PC
.set I2C_master_sda__PC2, CYREG_GPIO_PRT3_PC2
.set I2C_master_sda__PORT, 3
.set I2C_master_sda__PS, CYREG_GPIO_PRT3_PS
.set I2C_master_sda__SHIFT, 4

/* PDSS_PORT0_RX_CLK */
.set PDSS_PORT0_RX_CLK__DIV_ID, 0x00000000
.set PDSS_PORT0_RX_CLK__DIV_REGISTER, CYREG_PERI_DIV_8_CTL0
.set PDSS_PORT0_RX_CLK__PA_DIV_ID, 0x000000FF

/* PDSS_PORT0_TX_CLK */
.set PDSS_PORT0_TX_CLK__DIV_ID, 0x00000041
.set PDSS_PORT0_TX_CLK__DIV_REGISTER, CYREG_PERI_DIV_16_CTL1
.set PDSS_PORT0_TX_CLK__PA_DIV_ID, 0x000000FF

/* PDSS_PORT0_SAR_CLK */
.set PDSS_PORT0_SAR_CLK__DIV_ID, 0x00000040
.set PDSS_PORT0_SAR_CLK__DIV_REGISTER, CYREG_PERI_DIV_16_CTL0
.set PDSS_PORT0_SAR_CLK__PA_DIV_ID, 0x000000FF

/* PDSS_PORT0_SWAP_CLK */
.set PDSS_PORT0_SWAP_CLK__DIV_ID, 0x00000002
.set PDSS_PORT0_SWAP_CLK__DIV_REGISTER, CYREG_PERI_DIV_8_CTL2
.set PDSS_PORT0_SWAP_CLK__PA_DIV_ID, 0x000000FF

/* Miscellaneous */
.set CYDEV_BCLK__HFCLK__HZ, 48000000
.set CYDEV_BCLK__HFCLK__KHZ, 48000
.set CYDEV_BCLK__HFCLK__MHZ, 48
.set CYDEV_BCLK__SYSCLK__HZ, 48000000
.set CYDEV_BCLK__SYSCLK__KHZ, 48000
.set CYDEV_BCLK__SYSCLK__MHZ, 48
.set CYDEV_CHIP_DIE_LEOPARD, 1
.set CYDEV_CHIP_DIE_PANTHER, 19
.set CYDEV_CHIP_DIE_PSOC4A, 11
.set CYDEV_CHIP_DIE_PSOC5LP, 18
.set CYDEV_CHIP_DIE_TMA4, 2
.set CYDEV_CHIP_DIE_UNKNOWN, 0
.set CYDEV_CHIP_FAMILY_PSOC3, 1
.set CYDEV_CHIP_FAMILY_PSOC4, 2
.set CYDEV_CHIP_FAMILY_PSOC5, 3
.set CYDEV_CHIP_FAMILY_UNKNOWN, 0
.set CYDEV_CHIP_FAMILY_USED, CYDEV_CHIP_FAMILY_PSOC4
.set CYDEV_CHIP_JTAG_ID, 0x1D0411AD
.set CYDEV_CHIP_MEMBER_3A, 1
.set CYDEV_CHIP_MEMBER_4A, 11
.set CYDEV_CHIP_MEMBER_4C, 16
.set CYDEV_CHIP_MEMBER_4D, 7
.set CYDEV_CHIP_MEMBER_4E, 4
.set CYDEV_CHIP_MEMBER_4F, 12
.set CYDEV_CHIP_MEMBER_4G, 2
.set CYDEV_CHIP_MEMBER_4H, 10
.set CYDEV_CHIP_MEMBER_4I, 15
.set CYDEV_CHIP_MEMBER_4J, 8
.set CYDEV_CHIP_MEMBER_4K, 9
.set CYDEV_CHIP_MEMBER_4L, 14
.set CYDEV_CHIP_MEMBER_4M, 13
.set CYDEV_CHIP_MEMBER_4N, 6
.set CYDEV_CHIP_MEMBER_4O, 5
.set CYDEV_CHIP_MEMBER_4U, 3
.set CYDEV_CHIP_MEMBER_5A, 18
.set CYDEV_CHIP_MEMBER_5B, 17
.set CYDEV_CHIP_MEMBER_UNKNOWN, 0
.set CYDEV_CHIP_MEMBER_USED, CYDEV_CHIP_MEMBER_4O
.set CYDEV_CHIP_DIE_EXPECT, CYDEV_CHIP_MEMBER_USED
.set CYDEV_CHIP_DIE_ACTUAL, CYDEV_CHIP_DIE_EXPECT
.set CYDEV_CHIP_REV_LEOPARD_ES1, 0
.set CYDEV_CHIP_REV_LEOPARD_ES2, 1
.set CYDEV_CHIP_REV_LEOPARD_ES3, 3
.set CYDEV_CHIP_REV_LEOPARD_PRODUCTION, 3
.set CYDEV_CHIP_REV_PANTHER_ES0, 0
.set CYDEV_CHIP_REV_PANTHER_ES1, 1
.set CYDEV_CHIP_REV_PANTHER_PRODUCTION, 1
.set CYDEV_CHIP_REV_PSOC4A_ES0, 17
.set CYDEV_CHIP_REV_PSOC4A_PRODUCTION, 17
.set CYDEV_CHIP_REV_PSOC5LP_ES0, 0
.set CYDEV_CHIP_REV_PSOC5LP_PRODUCTION, 0
.set CYDEV_CHIP_REV_TMA4_ES, 17
.set CYDEV_CHIP_REV_TMA4_ES2, 33
.set CYDEV_CHIP_REV_TMA4_PRODUCTION, 17
.set CYDEV_CHIP_REVISION_3A_ES1, 0
.set CYDEV_CHIP_REVISION_3A_ES2, 1
.set CYDEV_CHIP_REVISION_3A_ES3, 3
.set CYDEV_CHIP_REVISION_3A_PRODUCTION, 3
.set CYDEV_CHIP_REVISION_4A_ES0, 17
.set CYDEV_CHIP_REVISION_4A_PRODUCTION, 17
.set CYDEV_CHIP_REVISION_4C_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_4D_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_4E_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_4F_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_4F_PRODUCTION_256DMA, 0
.set CYDEV_CHIP_REVISION_4F_PRODUCTION_256K, 0
.set CYDEV_CHIP_REVISION_4G_ES, 17
.set CYDEV_CHIP_REVISION_4G_ES2, 33
.set CYDEV_CHIP_REVISION_4G_PRODUCTION, 17
.set CYDEV_CHIP_REVISION_4H_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_4I_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_4J_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_4K_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_4L_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_4M_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_4N_ES, 0
.set CYDEV_CHIP_REVISION_4N_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_4O_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_4U_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_5A_ES0, 0
.set CYDEV_CHIP_REVISION_5A_ES1, 1
.set CYDEV_CHIP_REVISION_5A_PRODUCTION, 1
.set CYDEV_CHIP_REVISION_5B_ES0, 0
.set CYDEV_CHIP_REVISION_5B_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_USED, CYDEV_CHIP_REVISION_4O_PRODUCTION
.set CYDEV_CHIP_REV_EXPECT, CYDEV_CHIP_REVISION_USED
.set CYDEV_CONFIG_READ_ACCELERATOR, 1
.set CYDEV_CONFIG_UNUSED_IO_AllowButWarn, 0
.set CYDEV_CONFIG_UNUSED_IO_AllowWithInfo, 1
.set CYDEV_CONFIG_UNUSED_IO_Disallowed, 2
.set CYDEV_CONFIGURATION_COMPRESSED, 1
.set CYDEV_CONFIGURATION_MODE_COMPRESSED, 0
.set CYDEV_CONFIGURATION_MODE, CYDEV_CONFIGURATION_MODE_COMPRESSED
.set CYDEV_CONFIGURATION_MODE_DMA, 2
.set CYDEV_CONFIGURATION_MODE_UNCOMPRESSED, 1
.set CYDEV_DEBUG_PROTECT_KILL, 4
.set CYDEV_DEBUG_PROTECT_OPEN, 1
.set CYDEV_DEBUG_PROTECT, CYDEV_DEBUG_PROTECT_OPEN
.set CYDEV_DEBUG_PROTECT_PROTECTED, 2
.set CYDEV_DEBUGGING_DPS_Disable, 3
.set CYDEV_DEBUGGING_DPS, CYDEV_DEBUGGING_DPS_Disable
.set CYDEV_DEBUGGING_DPS_SWD, 2
.set CYDEV_DEBUGGING_ENABLE, 0
.set CYDEV_DFT_SELECT_CLK0, 8
.set CYDEV_DFT_SELECT_CLK1, 9
.set CYDEV_HEAP_SIZE, 0x80
.set CYDEV_IMO_TRIMMED_BY_USB, 0
.set CYDEV_IMO_TRIMMED_BY_WCO, 0
.set CYDEV_IS_EXPORTING_CODE, 0
.set CYDEV_IS_IMPORTING_CODE, 0
.set CYDEV_PROJ_TYPE, 2
.set CYDEV_PROJ_TYPE_BOOTLOADER, 1
.set CYDEV_PROJ_TYPE_LAUNCHER, 5
.set CYDEV_PROJ_TYPE_LOADABLE, 2
.set CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER, 4
.set CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER, 3
.set CYDEV_PROJ_TYPE_STANDARD, 0
.set CYDEV_STACK_SIZE, 0x0800
.set CYDEV_USE_BUNDLED_CMSIS, 1
.set CYDEV_VARIABLE_VDDA, 1
.set CYDEV_VDDD_MV, 3300
.set CYDEV_VDDIO_MV, 3300
.set CYDEV_WDT_GENERATE_ISR, 0
.set CYIPBLOCK_m0s8cpussv3_VERSION, 1
.set CYIPBLOCK_m0s8crypto_VERSION, 2
.set CYIPBLOCK_m0s8ioss_VERSION, 1
.set CYIPBLOCK_m0s8peri_VERSION, 1
.set CYIPBLOCK_m0s8scb_VERSION, 2
.set CYIPBLOCK_m0s8tcpwm_VERSION, 2
.set CYIPBLOCK_m0s8usbdss_VERSION, 2
.set CYIPBLOCK_m0s8usbpd_VERSION, 2
.set CYIPBLOCK_s8srsslt_VERSION, 1
.set CYDEV_BOOTLOADER_ENABLE, 0
.endif
