/*******************************************************************************
* File Name: cydevice_trm.h
* 
* PSoC Creator  3.3 DP1
*
* Description:
* This file provides all of the address values for the entire PSoC device.
* This file is automatically generated by PSoC Creator.
*
********************************************************************************
* Copyright (c) 2007-2016 Cypress Semiconductor.  All rights reserved.
* You may use this file only in accordance with the license, terms, conditions, 
* disclaimers, and limitations in the end user license agreement accompanying 
* the software package with which this file was provided.
********************************************************************************/

#if !defined(CYDEVICE_TRM_H)
#define CYDEVICE_TRM_H
#define CYDEV_FLASH_BASE 0x00000000u
#define CYDEV_FLASH_SIZE 0x00020000u
#define CYREG_FLASH_DATA_MBASE 0x00000000u
#define CYREG_FLASH_DATA_MSIZE 0x00020000u
#define CYDEV_SFLASH_BASE 0x0ffff000u
#define CYDEV_SFLASH_SIZE 0x00000800u
#define CYREG_SFLASH_PROT_ROW0 0x0ffff000u
#define CYFLD_SFLASH_DATA8__OFFSET 0x00000000u
#define CYFLD_SFLASH_DATA8__SIZE 0x00000008u
#define CYREG_SFLASH_PROT_ROW1 0x0ffff001u
#define CYREG_SFLASH_PROT_ROW2 0x0ffff002u
#define CYREG_SFLASH_PROT_ROW3 0x0ffff003u
#define CYREG_SFLASH_PROT_ROW4 0x0ffff004u
#define CYREG_SFLASH_PROT_ROW5 0x0ffff005u
#define CYREG_SFLASH_PROT_ROW6 0x0ffff006u
#define CYREG_SFLASH_PROT_ROW7 0x0ffff007u
#define CYREG_SFLASH_PROT_ROW8 0x0ffff008u
#define CYREG_SFLASH_PROT_ROW9 0x0ffff009u
#define CYREG_SFLASH_PROT_ROW10 0x0ffff00au
#define CYREG_SFLASH_PROT_ROW11 0x0ffff00bu
#define CYREG_SFLASH_PROT_ROW12 0x0ffff00cu
#define CYREG_SFLASH_PROT_ROW13 0x0ffff00du
#define CYREG_SFLASH_PROT_ROW14 0x0ffff00eu
#define CYREG_SFLASH_PROT_ROW15 0x0ffff00fu
#define CYREG_SFLASH_PROT_ROW16 0x0ffff010u
#define CYREG_SFLASH_PROT_ROW17 0x0ffff011u
#define CYREG_SFLASH_PROT_ROW18 0x0ffff012u
#define CYREG_SFLASH_PROT_ROW19 0x0ffff013u
#define CYREG_SFLASH_PROT_ROW20 0x0ffff014u
#define CYREG_SFLASH_PROT_ROW21 0x0ffff015u
#define CYREG_SFLASH_PROT_ROW22 0x0ffff016u
#define CYREG_SFLASH_PROT_ROW23 0x0ffff017u
#define CYREG_SFLASH_PROT_ROW24 0x0ffff018u
#define CYREG_SFLASH_PROT_ROW25 0x0ffff019u
#define CYREG_SFLASH_PROT_ROW26 0x0ffff01au
#define CYREG_SFLASH_PROT_ROW27 0x0ffff01bu
#define CYREG_SFLASH_PROT_ROW28 0x0ffff01cu
#define CYREG_SFLASH_PROT_ROW29 0x0ffff01du
#define CYREG_SFLASH_PROT_ROW30 0x0ffff01eu
#define CYREG_SFLASH_PROT_ROW31 0x0ffff01fu
#define CYREG_SFLASH_PROT_ROW32 0x0ffff020u
#define CYREG_SFLASH_PROT_ROW33 0x0ffff021u
#define CYREG_SFLASH_PROT_ROW34 0x0ffff022u
#define CYREG_SFLASH_PROT_ROW35 0x0ffff023u
#define CYREG_SFLASH_PROT_ROW36 0x0ffff024u
#define CYREG_SFLASH_PROT_ROW37 0x0ffff025u
#define CYREG_SFLASH_PROT_ROW38 0x0ffff026u
#define CYREG_SFLASH_PROT_ROW39 0x0ffff027u
#define CYREG_SFLASH_PROT_ROW40 0x0ffff028u
#define CYREG_SFLASH_PROT_ROW41 0x0ffff029u
#define CYREG_SFLASH_PROT_ROW42 0x0ffff02au
#define CYREG_SFLASH_PROT_ROW43 0x0ffff02bu
#define CYREG_SFLASH_PROT_ROW44 0x0ffff02cu
#define CYREG_SFLASH_PROT_ROW45 0x0ffff02du
#define CYREG_SFLASH_PROT_ROW46 0x0ffff02eu
#define CYREG_SFLASH_PROT_ROW47 0x0ffff02fu
#define CYREG_SFLASH_PROT_ROW48 0x0ffff030u
#define CYREG_SFLASH_PROT_ROW49 0x0ffff031u
#define CYREG_SFLASH_PROT_ROW50 0x0ffff032u
#define CYREG_SFLASH_PROT_ROW51 0x0ffff033u
#define CYREG_SFLASH_PROT_ROW52 0x0ffff034u
#define CYREG_SFLASH_PROT_ROW53 0x0ffff035u
#define CYREG_SFLASH_PROT_ROW54 0x0ffff036u
#define CYREG_SFLASH_PROT_ROW55 0x0ffff037u
#define CYREG_SFLASH_PROT_ROW56 0x0ffff038u
#define CYREG_SFLASH_PROT_ROW57 0x0ffff039u
#define CYREG_SFLASH_PROT_ROW58 0x0ffff03au
#define CYREG_SFLASH_PROT_ROW59 0x0ffff03bu
#define CYREG_SFLASH_PROT_ROW60 0x0ffff03cu
#define CYREG_SFLASH_PROT_ROW61 0x0ffff03du
#define CYREG_SFLASH_PROT_ROW62 0x0ffff03eu
#define CYREG_SFLASH_PROT_ROW63 0x0ffff03fu
#define CYREG_SFLASH_PROT_PROTECTION 0x0ffff07fu
#define CYFLD_SFLASH_PROT_LEVEL__OFFSET 0x00000000u
#define CYFLD_SFLASH_PROT_LEVEL__SIZE 0x00000002u
#define CYVAL_SFLASH_PROT_LEVEL_VIRGIN 0x00000001u
#define CYVAL_SFLASH_PROT_LEVEL_OPEN 0x00000000u
#define CYVAL_SFLASH_PROT_LEVEL_PROTECTED 0x00000002u
#define CYVAL_SFLASH_PROT_LEVEL_KILL 0x00000003u
#define CYREG_SFLASH_AV_PAIRS_8B0 0x0ffff080u
#define CYREG_SFLASH_AV_PAIRS_8B1 0x0ffff081u
#define CYREG_SFLASH_AV_PAIRS_8B2 0x0ffff082u
#define CYREG_SFLASH_AV_PAIRS_8B3 0x0ffff083u
#define CYREG_SFLASH_AV_PAIRS_8B4 0x0ffff084u
#define CYREG_SFLASH_AV_PAIRS_8B5 0x0ffff085u
#define CYREG_SFLASH_AV_PAIRS_8B6 0x0ffff086u
#define CYREG_SFLASH_AV_PAIRS_8B7 0x0ffff087u
#define CYREG_SFLASH_AV_PAIRS_8B8 0x0ffff088u
#define CYREG_SFLASH_AV_PAIRS_8B9 0x0ffff089u
#define CYREG_SFLASH_AV_PAIRS_8B10 0x0ffff08au
#define CYREG_SFLASH_AV_PAIRS_8B11 0x0ffff08bu
#define CYREG_SFLASH_AV_PAIRS_8B12 0x0ffff08cu
#define CYREG_SFLASH_AV_PAIRS_8B13 0x0ffff08du
#define CYREG_SFLASH_AV_PAIRS_8B14 0x0ffff08eu
#define CYREG_SFLASH_AV_PAIRS_8B15 0x0ffff08fu
#define CYREG_SFLASH_AV_PAIRS_8B16 0x0ffff090u
#define CYREG_SFLASH_AV_PAIRS_8B17 0x0ffff091u
#define CYREG_SFLASH_AV_PAIRS_8B18 0x0ffff092u
#define CYREG_SFLASH_AV_PAIRS_8B19 0x0ffff093u
#define CYREG_SFLASH_AV_PAIRS_8B20 0x0ffff094u
#define CYREG_SFLASH_AV_PAIRS_8B21 0x0ffff095u
#define CYREG_SFLASH_AV_PAIRS_8B22 0x0ffff096u
#define CYREG_SFLASH_AV_PAIRS_8B23 0x0ffff097u
#define CYREG_SFLASH_AV_PAIRS_8B24 0x0ffff098u
#define CYREG_SFLASH_AV_PAIRS_8B25 0x0ffff099u
#define CYREG_SFLASH_AV_PAIRS_8B26 0x0ffff09au
#define CYREG_SFLASH_AV_PAIRS_8B27 0x0ffff09bu
#define CYREG_SFLASH_AV_PAIRS_8B28 0x0ffff09cu
#define CYREG_SFLASH_AV_PAIRS_8B29 0x0ffff09du
#define CYREG_SFLASH_AV_PAIRS_8B30 0x0ffff09eu
#define CYREG_SFLASH_AV_PAIRS_8B31 0x0ffff09fu
#define CYREG_SFLASH_AV_PAIRS_8B32 0x0ffff0a0u
#define CYREG_SFLASH_AV_PAIRS_8B33 0x0ffff0a1u
#define CYREG_SFLASH_AV_PAIRS_8B34 0x0ffff0a2u
#define CYREG_SFLASH_AV_PAIRS_8B35 0x0ffff0a3u
#define CYREG_SFLASH_AV_PAIRS_8B36 0x0ffff0a4u
#define CYREG_SFLASH_AV_PAIRS_8B37 0x0ffff0a5u
#define CYREG_SFLASH_AV_PAIRS_8B38 0x0ffff0a6u
#define CYREG_SFLASH_AV_PAIRS_8B39 0x0ffff0a7u
#define CYREG_SFLASH_AV_PAIRS_8B40 0x0ffff0a8u
#define CYREG_SFLASH_AV_PAIRS_8B41 0x0ffff0a9u
#define CYREG_SFLASH_AV_PAIRS_8B42 0x0ffff0aau
#define CYREG_SFLASH_AV_PAIRS_8B43 0x0ffff0abu
#define CYREG_SFLASH_AV_PAIRS_8B44 0x0ffff0acu
#define CYREG_SFLASH_AV_PAIRS_8B45 0x0ffff0adu
#define CYREG_SFLASH_AV_PAIRS_8B46 0x0ffff0aeu
#define CYREG_SFLASH_AV_PAIRS_8B47 0x0ffff0afu
#define CYREG_SFLASH_AV_PAIRS_8B48 0x0ffff0b0u
#define CYREG_SFLASH_AV_PAIRS_8B49 0x0ffff0b1u
#define CYREG_SFLASH_AV_PAIRS_8B50 0x0ffff0b2u
#define CYREG_SFLASH_AV_PAIRS_8B51 0x0ffff0b3u
#define CYREG_SFLASH_AV_PAIRS_8B52 0x0ffff0b4u
#define CYREG_SFLASH_AV_PAIRS_8B53 0x0ffff0b5u
#define CYREG_SFLASH_AV_PAIRS_8B54 0x0ffff0b6u
#define CYREG_SFLASH_AV_PAIRS_8B55 0x0ffff0b7u
#define CYREG_SFLASH_AV_PAIRS_8B56 0x0ffff0b8u
#define CYREG_SFLASH_AV_PAIRS_8B57 0x0ffff0b9u
#define CYREG_SFLASH_AV_PAIRS_8B58 0x0ffff0bau
#define CYREG_SFLASH_AV_PAIRS_8B59 0x0ffff0bbu
#define CYREG_SFLASH_AV_PAIRS_8B60 0x0ffff0bcu
#define CYREG_SFLASH_AV_PAIRS_8B61 0x0ffff0bdu
#define CYREG_SFLASH_AV_PAIRS_8B62 0x0ffff0beu
#define CYREG_SFLASH_AV_PAIRS_8B63 0x0ffff0bfu
#define CYREG_SFLASH_AV_PAIRS_8B64 0x0ffff0c0u
#define CYREG_SFLASH_AV_PAIRS_8B65 0x0ffff0c1u
#define CYREG_SFLASH_AV_PAIRS_8B66 0x0ffff0c2u
#define CYREG_SFLASH_AV_PAIRS_8B67 0x0ffff0c3u
#define CYREG_SFLASH_AV_PAIRS_8B68 0x0ffff0c4u
#define CYREG_SFLASH_AV_PAIRS_8B69 0x0ffff0c5u
#define CYREG_SFLASH_AV_PAIRS_8B70 0x0ffff0c6u
#define CYREG_SFLASH_AV_PAIRS_8B71 0x0ffff0c7u
#define CYREG_SFLASH_AV_PAIRS_8B72 0x0ffff0c8u
#define CYREG_SFLASH_AV_PAIRS_8B73 0x0ffff0c9u
#define CYREG_SFLASH_AV_PAIRS_8B74 0x0ffff0cau
#define CYREG_SFLASH_AV_PAIRS_8B75 0x0ffff0cbu
#define CYREG_SFLASH_AV_PAIRS_8B76 0x0ffff0ccu
#define CYREG_SFLASH_AV_PAIRS_8B77 0x0ffff0cdu
#define CYREG_SFLASH_AV_PAIRS_8B78 0x0ffff0ceu
#define CYREG_SFLASH_AV_PAIRS_8B79 0x0ffff0cfu
#define CYREG_SFLASH_AV_PAIRS_8B80 0x0ffff0d0u
#define CYREG_SFLASH_AV_PAIRS_8B81 0x0ffff0d1u
#define CYREG_SFLASH_AV_PAIRS_8B82 0x0ffff0d2u
#define CYREG_SFLASH_AV_PAIRS_8B83 0x0ffff0d3u
#define CYREG_SFLASH_AV_PAIRS_8B84 0x0ffff0d4u
#define CYREG_SFLASH_AV_PAIRS_8B85 0x0ffff0d5u
#define CYREG_SFLASH_AV_PAIRS_8B86 0x0ffff0d6u
#define CYREG_SFLASH_AV_PAIRS_8B87 0x0ffff0d7u
#define CYREG_SFLASH_AV_PAIRS_8B88 0x0ffff0d8u
#define CYREG_SFLASH_AV_PAIRS_8B89 0x0ffff0d9u
#define CYREG_SFLASH_AV_PAIRS_8B90 0x0ffff0dau
#define CYREG_SFLASH_AV_PAIRS_8B91 0x0ffff0dbu
#define CYREG_SFLASH_AV_PAIRS_8B92 0x0ffff0dcu
#define CYREG_SFLASH_AV_PAIRS_8B93 0x0ffff0ddu
#define CYREG_SFLASH_AV_PAIRS_8B94 0x0ffff0deu
#define CYREG_SFLASH_AV_PAIRS_8B95 0x0ffff0dfu
#define CYREG_SFLASH_AV_PAIRS_8B96 0x0ffff0e0u
#define CYREG_SFLASH_AV_PAIRS_8B97 0x0ffff0e1u
#define CYREG_SFLASH_AV_PAIRS_8B98 0x0ffff0e2u
#define CYREG_SFLASH_AV_PAIRS_8B99 0x0ffff0e3u
#define CYREG_SFLASH_AV_PAIRS_8B100 0x0ffff0e4u
#define CYREG_SFLASH_AV_PAIRS_8B101 0x0ffff0e5u
#define CYREG_SFLASH_AV_PAIRS_8B102 0x0ffff0e6u
#define CYREG_SFLASH_AV_PAIRS_8B103 0x0ffff0e7u
#define CYREG_SFLASH_AV_PAIRS_8B104 0x0ffff0e8u
#define CYREG_SFLASH_AV_PAIRS_8B105 0x0ffff0e9u
#define CYREG_SFLASH_AV_PAIRS_8B106 0x0ffff0eau
#define CYREG_SFLASH_AV_PAIRS_8B107 0x0ffff0ebu
#define CYREG_SFLASH_AV_PAIRS_8B108 0x0ffff0ecu
#define CYREG_SFLASH_AV_PAIRS_8B109 0x0ffff0edu
#define CYREG_SFLASH_AV_PAIRS_8B110 0x0ffff0eeu
#define CYREG_SFLASH_AV_PAIRS_8B111 0x0ffff0efu
#define CYREG_SFLASH_AV_PAIRS_8B112 0x0ffff0f0u
#define CYREG_SFLASH_AV_PAIRS_8B113 0x0ffff0f1u
#define CYREG_SFLASH_AV_PAIRS_8B114 0x0ffff0f2u
#define CYREG_SFLASH_AV_PAIRS_8B115 0x0ffff0f3u
#define CYREG_SFLASH_AV_PAIRS_8B116 0x0ffff0f4u
#define CYREG_SFLASH_AV_PAIRS_8B117 0x0ffff0f5u
#define CYREG_SFLASH_AV_PAIRS_8B118 0x0ffff0f6u
#define CYREG_SFLASH_AV_PAIRS_8B119 0x0ffff0f7u
#define CYREG_SFLASH_AV_PAIRS_8B120 0x0ffff0f8u
#define CYREG_SFLASH_AV_PAIRS_8B121 0x0ffff0f9u
#define CYREG_SFLASH_AV_PAIRS_8B122 0x0ffff0fau
#define CYREG_SFLASH_AV_PAIRS_8B123 0x0ffff0fbu
#define CYREG_SFLASH_AV_PAIRS_8B124 0x0ffff0fcu
#define CYREG_SFLASH_AV_PAIRS_8B125 0x0ffff0fdu
#define CYREG_SFLASH_AV_PAIRS_8B126 0x0ffff0feu
#define CYREG_SFLASH_AV_PAIRS_8B127 0x0ffff0ffu
#define CYREG_SFLASH_AV_PAIRS_32B0 0x0ffff100u
#define CYFLD_SFLASH_DATA32__OFFSET 0x00000000u
#define CYFLD_SFLASH_DATA32__SIZE 0x00000020u
#define CYREG_SFLASH_AV_PAIRS_32B1 0x0ffff104u
#define CYREG_SFLASH_AV_PAIRS_32B2 0x0ffff108u
#define CYREG_SFLASH_AV_PAIRS_32B3 0x0ffff10cu
#define CYREG_SFLASH_AV_PAIRS_32B4 0x0ffff110u
#define CYREG_SFLASH_AV_PAIRS_32B5 0x0ffff114u
#define CYREG_SFLASH_AV_PAIRS_32B6 0x0ffff118u
#define CYREG_SFLASH_AV_PAIRS_32B7 0x0ffff11cu
#define CYREG_SFLASH_AV_PAIRS_32B8 0x0ffff120u
#define CYREG_SFLASH_AV_PAIRS_32B9 0x0ffff124u
#define CYREG_SFLASH_AV_PAIRS_32B10 0x0ffff128u
#define CYREG_SFLASH_AV_PAIRS_32B11 0x0ffff12cu
#define CYREG_SFLASH_AV_PAIRS_32B12 0x0ffff130u
#define CYREG_SFLASH_AV_PAIRS_32B13 0x0ffff134u
#define CYREG_SFLASH_AV_PAIRS_32B14 0x0ffff138u
#define CYREG_SFLASH_AV_PAIRS_32B15 0x0ffff13cu
#define CYREG_SFLASH_CPUSS_WOUNDING 0x0ffff140u
#define CYREG_SFLASH_SILICON_ID 0x0ffff144u
#define CYFLD_SFLASH_ID__OFFSET 0x00000000u
#define CYFLD_SFLASH_ID__SIZE 0x00000010u
#define CYREG_SFLASH_CPUSS_PRIV_RAM 0x0ffff148u
#define CYFLD_SFLASH_RAM_PROT_LIMIT__OFFSET 0x00000000u
#define CYFLD_SFLASH_RAM_PROT_LIMIT__SIZE 0x00000009u
#define CYREG_SFLASH_CPUSS_PRIV_ROM_BROM 0x0ffff14au
#define CYFLD_SFLASH_BROM_PROT_LIMIT__OFFSET 0x00000000u
#define CYFLD_SFLASH_BROM_PROT_LIMIT__SIZE 0x00000008u
#define CYREG_SFLASH_CPUSS_PRIV_FLASH 0x0ffff14cu
#define CYFLD_SFLASH_FLASH_PROT_LIMIT__OFFSET 0x00000000u
#define CYFLD_SFLASH_FLASH_PROT_LIMIT__SIZE 0x0000000bu
#define CYREG_SFLASH_CPUSS_PRIV_ROM_SROM 0x0ffff14eu
#define CYFLD_SFLASH_SROM_PROT_LIMIT__OFFSET 0x00000000u
#define CYFLD_SFLASH_SROM_PROT_LIMIT__SIZE 0x0000000au
#define CYREG_SFLASH_HIB_KEY_DELAY 0x0ffff150u
#define CYFLD_SFLASH_WAKEUP_HOLDOFF__OFFSET 0x00000000u
#define CYFLD_SFLASH_WAKEUP_HOLDOFF__SIZE 0x0000000au
#define CYREG_SFLASH_DPSLP_KEY_DELAY 0x0ffff152u
#define CYREG_SFLASH_SWD_CONFIG 0x0ffff154u
#define CYFLD_SFLASH_SWD_SELECT__OFFSET 0x00000000u
#define CYFLD_SFLASH_SWD_SELECT__SIZE 0x00000001u
#define CYREG_SFLASH_INITIAL_SPCIF_TRIM_M1_DAC0 0x0ffff155u
#define CYFLD_SFLASH_IDAC__OFFSET 0x00000000u
#define CYFLD_SFLASH_IDAC__SIZE 0x00000005u
#define CYFLD_SFLASH_SLOPE__OFFSET 0x00000005u
#define CYFLD_SFLASH_SLOPE__SIZE 0x00000003u
#define CYREG_SFLASH_SWD_LISTEN 0x0ffff158u
#define CYFLD_SFLASH_CYCLES__OFFSET 0x00000000u
#define CYFLD_SFLASH_CYCLES__SIZE 0x00000020u
#define CYREG_SFLASH_FLASH_START 0x0ffff15cu
#define CYFLD_SFLASH_ADDRESS__OFFSET 0x00000000u
#define CYFLD_SFLASH_ADDRESS__SIZE 0x00000020u
#define CYREG_SFLASH_SKIP_CHECKSUM 0x0ffff169u
#define CYFLD_SFLASH_SKIP__OFFSET 0x00000000u
#define CYFLD_SFLASH_SKIP__SIZE 0x00000008u
#define CYREG_SFLASH_INITIAL_PWR_BG_TRIM1 0x0ffff16au
#define CYFLD_SFLASH_REF_ITRIM__OFFSET 0x00000000u
#define CYFLD_SFLASH_REF_ITRIM__SIZE 0x00000006u
#define CYREG_SFLASH_INITIAL_PWR_BG_TRIM1_INV 0x0ffff16bu
#define CYREG_SFLASH_INITIAL_PWR_BG_TRIM2 0x0ffff16cu
#define CYREG_SFLASH_INITIAL_PWR_BG_TRIM2_INV 0x0ffff16du
#define CYREG_SFLASH_INITIAL_SPCIF_TRIM_M0_DAC0 0x0ffff16eu
#define CYREG_SFLASH_INITIAL_SPCIF_TRIM_M0_DAC0_INV 0x0ffff16fu
#define CYREG_SFLASH_PROT_VIRGINKEY0 0x0ffff170u
#define CYFLD_SFLASH_KEY8__OFFSET 0x00000000u
#define CYFLD_SFLASH_KEY8__SIZE 0x00000008u
#define CYREG_SFLASH_PROT_VIRGINKEY1 0x0ffff171u
#define CYREG_SFLASH_PROT_VIRGINKEY2 0x0ffff172u
#define CYREG_SFLASH_PROT_VIRGINKEY3 0x0ffff173u
#define CYREG_SFLASH_PROT_VIRGINKEY4 0x0ffff174u
#define CYREG_SFLASH_PROT_VIRGINKEY5 0x0ffff175u
#define CYREG_SFLASH_PROT_VIRGINKEY6 0x0ffff176u
#define CYREG_SFLASH_PROT_VIRGINKEY7 0x0ffff177u
#define CYREG_SFLASH_DIE_LOT0 0x0ffff178u
#define CYFLD_SFLASH_LOT__OFFSET 0x00000000u
#define CYFLD_SFLASH_LOT__SIZE 0x00000008u
#define CYREG_SFLASH_DIE_LOT1 0x0ffff179u
#define CYREG_SFLASH_DIE_LOT2 0x0ffff17au
#define CYREG_SFLASH_DIE_WAFER 0x0ffff17bu
#define CYFLD_SFLASH_WAFER__OFFSET 0x00000000u
#define CYFLD_SFLASH_WAFER__SIZE 0x00000008u
#define CYREG_SFLASH_DIE_X 0x0ffff17cu
#define CYFLD_SFLASH_X__OFFSET 0x00000000u
#define CYFLD_SFLASH_X__SIZE 0x00000008u
#define CYREG_SFLASH_DIE_Y 0x0ffff17du
#define CYFLD_SFLASH_Y__OFFSET 0x00000000u
#define CYFLD_SFLASH_Y__SIZE 0x00000008u
#define CYREG_SFLASH_DIE_SORT 0x0ffff17eu
#define CYFLD_SFLASH_S1_PASS__OFFSET 0x00000000u
#define CYFLD_SFLASH_S1_PASS__SIZE 0x00000001u
#define CYFLD_SFLASH_S2_PASS__OFFSET 0x00000001u
#define CYFLD_SFLASH_S2_PASS__SIZE 0x00000001u
#define CYFLD_SFLASH_S3_PASS__OFFSET 0x00000002u
#define CYFLD_SFLASH_S3_PASS__SIZE 0x00000001u
#define CYFLD_SFLASH_CRI_PASS__OFFSET 0x00000003u
#define CYFLD_SFLASH_CRI_PASS__SIZE 0x00000001u
#define CYFLD_SFLASH_CHI_PASS__OFFSET 0x00000004u
#define CYFLD_SFLASH_CHI_PASS__SIZE 0x00000001u
#define CYFLD_SFLASH_ENG_PASS__OFFSET 0x00000005u
#define CYFLD_SFLASH_ENG_PASS__SIZE 0x00000001u
#define CYREG_SFLASH_DIE_MINOR 0x0ffff17fu
#define CYFLD_SFLASH_MINOR__OFFSET 0x00000000u
#define CYFLD_SFLASH_MINOR__SIZE 0x00000008u
#define CYREG_SFLASH_PE_TE_DATA0 0x0ffff180u
#define CYREG_SFLASH_PE_TE_DATA1 0x0ffff181u
#define CYREG_SFLASH_PE_TE_DATA2 0x0ffff182u
#define CYREG_SFLASH_PE_TE_DATA3 0x0ffff183u
#define CYREG_SFLASH_PE_TE_DATA4 0x0ffff184u
#define CYREG_SFLASH_PE_TE_DATA5 0x0ffff185u
#define CYREG_SFLASH_PE_TE_DATA6 0x0ffff186u
#define CYREG_SFLASH_PE_TE_DATA7 0x0ffff187u
#define CYREG_SFLASH_PE_TE_DATA8 0x0ffff188u
#define CYREG_SFLASH_PE_TE_DATA9 0x0ffff189u
#define CYREG_SFLASH_PE_TE_DATA10 0x0ffff18au
#define CYREG_SFLASH_PE_TE_DATA11 0x0ffff18bu
#define CYREG_SFLASH_PE_TE_DATA12 0x0ffff18cu
#define CYREG_SFLASH_PE_TE_DATA13 0x0ffff18du
#define CYREG_SFLASH_PE_TE_DATA14 0x0ffff18eu
#define CYREG_SFLASH_PE_TE_DATA15 0x0ffff18fu
#define CYREG_SFLASH_PE_TE_DATA16 0x0ffff190u
#define CYREG_SFLASH_PE_TE_DATA17 0x0ffff191u
#define CYREG_SFLASH_PE_TE_DATA18 0x0ffff192u
#define CYREG_SFLASH_PE_TE_DATA19 0x0ffff193u
#define CYREG_SFLASH_PE_TE_DATA20 0x0ffff194u
#define CYREG_SFLASH_PE_TE_DATA21 0x0ffff195u
#define CYREG_SFLASH_PE_TE_DATA22 0x0ffff196u
#define CYREG_SFLASH_PE_TE_DATA23 0x0ffff197u
#define CYREG_SFLASH_PE_TE_DATA24 0x0ffff198u
#define CYREG_SFLASH_PE_TE_DATA25 0x0ffff199u
#define CYREG_SFLASH_PE_TE_DATA26 0x0ffff19au
#define CYREG_SFLASH_PE_TE_DATA27 0x0ffff19bu
#define CYREG_SFLASH_PE_TE_DATA28 0x0ffff19cu
#define CYREG_SFLASH_PE_TE_DATA29 0x0ffff19du
#define CYREG_SFLASH_PE_TE_DATA30 0x0ffff19eu
#define CYREG_SFLASH_PE_TE_DATA31 0x0ffff19fu
#define CYREG_SFLASH_PP 0x0ffff1a0u
#define CYFLD_SFLASH_PERIOD__OFFSET 0x00000000u
#define CYFLD_SFLASH_PERIOD__SIZE 0x00000018u
#define CYFLD_SFLASH_PDAC__OFFSET 0x00000018u
#define CYFLD_SFLASH_PDAC__SIZE 0x00000004u
#define CYFLD_SFLASH_NDAC__OFFSET 0x0000001cu
#define CYFLD_SFLASH_NDAC__SIZE 0x00000004u
#define CYREG_SFLASH_E 0x0ffff1a4u
#define CYREG_SFLASH_P 0x0ffff1a8u
#define CYREG_SFLASH_EA_E 0x0ffff1acu
#define CYREG_SFLASH_EA_P 0x0ffff1b0u
#define CYREG_SFLASH_ES_E 0x0ffff1b4u
#define CYREG_SFLASH_ES_P_EO 0x0ffff1b8u
#define CYREG_SFLASH_IMO_TRIM_USBMODE_24 0x0ffff1beu
#define CYFLD_SFLASH_TRIM_24__OFFSET 0x00000000u
#define CYFLD_SFLASH_TRIM_24__SIZE 0x00000008u
#define CYREG_SFLASH_IMO_TRIM_USBMODE_48 0x0ffff1bfu
#define CYREG_SFLASH_IMO_TCTRIM_LT0 0x0ffff1ccu
#define CYFLD_SFLASH_STEPSIZE__OFFSET 0x00000000u
#define CYFLD_SFLASH_STEPSIZE__SIZE 0x00000005u
#define CYFLD_SFLASH_TCTRIM__OFFSET 0x00000005u
#define CYFLD_SFLASH_TCTRIM__SIZE 0x00000002u
#define CYREG_SFLASH_IMO_TCTRIM_LT1 0x0ffff1cdu
#define CYREG_SFLASH_IMO_TCTRIM_LT2 0x0ffff1ceu
#define CYREG_SFLASH_IMO_TCTRIM_LT3 0x0ffff1cfu
#define CYREG_SFLASH_IMO_TCTRIM_LT4 0x0ffff1d0u
#define CYREG_SFLASH_IMO_TCTRIM_LT5 0x0ffff1d1u
#define CYREG_SFLASH_IMO_TCTRIM_LT6 0x0ffff1d2u
#define CYREG_SFLASH_IMO_TCTRIM_LT7 0x0ffff1d3u
#define CYREG_SFLASH_IMO_TCTRIM_LT8 0x0ffff1d4u
#define CYREG_SFLASH_IMO_TCTRIM_LT9 0x0ffff1d5u
#define CYREG_SFLASH_IMO_TCTRIM_LT10 0x0ffff1d6u
#define CYREG_SFLASH_IMO_TCTRIM_LT11 0x0ffff1d7u
#define CYREG_SFLASH_IMO_TCTRIM_LT12 0x0ffff1d8u
#define CYREG_SFLASH_IMO_TCTRIM_LT13 0x0ffff1d9u
#define CYREG_SFLASH_IMO_TCTRIM_LT14 0x0ffff1dau
#define CYREG_SFLASH_IMO_TCTRIM_LT15 0x0ffff1dbu
#define CYREG_SFLASH_IMO_TCTRIM_LT16 0x0ffff1dcu
#define CYREG_SFLASH_IMO_TCTRIM_LT17 0x0ffff1ddu
#define CYREG_SFLASH_IMO_TCTRIM_LT18 0x0ffff1deu
#define CYREG_SFLASH_IMO_TCTRIM_LT19 0x0ffff1dfu
#define CYREG_SFLASH_IMO_TCTRIM_LT20 0x0ffff1e0u
#define CYREG_SFLASH_IMO_TCTRIM_LT21 0x0ffff1e1u
#define CYREG_SFLASH_IMO_TCTRIM_LT22 0x0ffff1e2u
#define CYREG_SFLASH_IMO_TCTRIM_LT23 0x0ffff1e3u
#define CYREG_SFLASH_IMO_TCTRIM_LT24 0x0ffff1e4u
#define CYREG_SFLASH_IMO_TRIM_LT0 0x0ffff1e5u
#define CYFLD_SFLASH_OFFSET__OFFSET 0x00000000u
#define CYFLD_SFLASH_OFFSET__SIZE 0x00000008u
#define CYREG_SFLASH_IMO_TRIM_LT1 0x0ffff1e6u
#define CYREG_SFLASH_IMO_TRIM_LT2 0x0ffff1e7u
#define CYREG_SFLASH_IMO_TRIM_LT3 0x0ffff1e8u
#define CYREG_SFLASH_IMO_TRIM_LT4 0x0ffff1e9u
#define CYREG_SFLASH_IMO_TRIM_LT5 0x0ffff1eau
#define CYREG_SFLASH_IMO_TRIM_LT6 0x0ffff1ebu
#define CYREG_SFLASH_IMO_TRIM_LT7 0x0ffff1ecu
#define CYREG_SFLASH_IMO_TRIM_LT8 0x0ffff1edu
#define CYREG_SFLASH_IMO_TRIM_LT9 0x0ffff1eeu
#define CYREG_SFLASH_IMO_TRIM_LT10 0x0ffff1efu
#define CYREG_SFLASH_IMO_TRIM_LT11 0x0ffff1f0u
#define CYREG_SFLASH_IMO_TRIM_LT12 0x0ffff1f1u
#define CYREG_SFLASH_IMO_TRIM_LT13 0x0ffff1f2u
#define CYREG_SFLASH_IMO_TRIM_LT14 0x0ffff1f3u
#define CYREG_SFLASH_IMO_TRIM_LT15 0x0ffff1f4u
#define CYREG_SFLASH_IMO_TRIM_LT16 0x0ffff1f5u
#define CYREG_SFLASH_IMO_TRIM_LT17 0x0ffff1f6u
#define CYREG_SFLASH_IMO_TRIM_LT18 0x0ffff1f7u
#define CYREG_SFLASH_IMO_TRIM_LT19 0x0ffff1f8u
#define CYREG_SFLASH_IMO_TRIM_LT20 0x0ffff1f9u
#define CYREG_SFLASH_IMO_TRIM_LT21 0x0ffff1fau
#define CYREG_SFLASH_IMO_TRIM_LT22 0x0ffff1fbu
#define CYREG_SFLASH_IMO_TRIM_LT23 0x0ffff1fcu
#define CYREG_SFLASH_IMO_TRIM_LT24 0x0ffff1fdu
#define CYREG_SFLASH_CHECKSUM 0x0ffff1feu
#define CYFLD_SFLASH_CHECKSUM__OFFSET 0x00000000u
#define CYFLD_SFLASH_CHECKSUM__SIZE 0x00000010u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH0 0x0ffff200u
#define CYFLD_SFLASH_BYTE_MEM__OFFSET 0x00000000u
#define CYFLD_SFLASH_BYTE_MEM__SIZE 0x00000008u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1 0x0ffff201u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH2 0x0ffff202u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH3 0x0ffff203u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH4 0x0ffff204u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH5 0x0ffff205u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH6 0x0ffff206u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH7 0x0ffff207u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH8 0x0ffff208u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH9 0x0ffff209u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH10 0x0ffff20au
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH11 0x0ffff20bu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH12 0x0ffff20cu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH13 0x0ffff20du
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH14 0x0ffff20eu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH15 0x0ffff20fu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH16 0x0ffff210u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH17 0x0ffff211u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH18 0x0ffff212u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH19 0x0ffff213u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH20 0x0ffff214u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH21 0x0ffff215u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH22 0x0ffff216u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH23 0x0ffff217u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH24 0x0ffff218u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH25 0x0ffff219u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH26 0x0ffff21au
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH27 0x0ffff21bu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH28 0x0ffff21cu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH29 0x0ffff21du
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH30 0x0ffff21eu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH31 0x0ffff21fu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH32 0x0ffff220u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH33 0x0ffff221u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH34 0x0ffff222u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH35 0x0ffff223u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH36 0x0ffff224u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH37 0x0ffff225u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH38 0x0ffff226u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH39 0x0ffff227u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH40 0x0ffff228u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH41 0x0ffff229u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH42 0x0ffff22au
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH43 0x0ffff22bu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH44 0x0ffff22cu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH45 0x0ffff22du
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH46 0x0ffff22eu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH47 0x0ffff22fu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH48 0x0ffff230u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH49 0x0ffff231u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH50 0x0ffff232u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH51 0x0ffff233u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH52 0x0ffff234u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH53 0x0ffff235u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH54 0x0ffff236u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH55 0x0ffff237u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH56 0x0ffff238u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH57 0x0ffff239u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH58 0x0ffff23au
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH59 0x0ffff23bu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH60 0x0ffff23cu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH61 0x0ffff23du
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH62 0x0ffff23eu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH63 0x0ffff23fu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH64 0x0ffff240u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH65 0x0ffff241u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH66 0x0ffff242u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH67 0x0ffff243u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH68 0x0ffff244u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH69 0x0ffff245u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH70 0x0ffff246u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH71 0x0ffff247u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH72 0x0ffff248u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH73 0x0ffff249u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH74 0x0ffff24au
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH75 0x0ffff24bu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH76 0x0ffff24cu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH77 0x0ffff24du
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH78 0x0ffff24eu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH79 0x0ffff24fu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH80 0x0ffff250u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH81 0x0ffff251u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH82 0x0ffff252u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH83 0x0ffff253u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH84 0x0ffff254u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH85 0x0ffff255u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH86 0x0ffff256u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH87 0x0ffff257u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH88 0x0ffff258u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH89 0x0ffff259u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH90 0x0ffff25au
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH91 0x0ffff25bu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH92 0x0ffff25cu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH93 0x0ffff25du
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH94 0x0ffff25eu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH95 0x0ffff25fu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH96 0x0ffff260u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH97 0x0ffff261u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH98 0x0ffff262u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH99 0x0ffff263u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH100 0x0ffff264u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH101 0x0ffff265u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH102 0x0ffff266u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH103 0x0ffff267u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH104 0x0ffff268u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH105 0x0ffff269u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH106 0x0ffff26au
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH107 0x0ffff26bu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH108 0x0ffff26cu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH109 0x0ffff26du
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH110 0x0ffff26eu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH111 0x0ffff26fu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH112 0x0ffff270u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH113 0x0ffff271u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH114 0x0ffff272u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH115 0x0ffff273u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH116 0x0ffff274u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH117 0x0ffff275u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH118 0x0ffff276u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH119 0x0ffff277u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH120 0x0ffff278u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH121 0x0ffff279u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH122 0x0ffff27au
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH123 0x0ffff27bu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH124 0x0ffff27cu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH125 0x0ffff27du
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH126 0x0ffff27eu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH127 0x0ffff27fu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH128 0x0ffff280u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH129 0x0ffff281u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH130 0x0ffff282u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH131 0x0ffff283u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH132 0x0ffff284u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH133 0x0ffff285u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH134 0x0ffff286u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH135 0x0ffff287u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH136 0x0ffff288u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH137 0x0ffff289u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH138 0x0ffff28au
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH139 0x0ffff28bu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH140 0x0ffff28cu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH141 0x0ffff28du
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH142 0x0ffff28eu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH143 0x0ffff28fu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH144 0x0ffff290u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH145 0x0ffff291u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH146 0x0ffff292u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH147 0x0ffff293u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH148 0x0ffff294u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH149 0x0ffff295u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH150 0x0ffff296u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH151 0x0ffff297u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH152 0x0ffff298u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH153 0x0ffff299u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH154 0x0ffff29au
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH155 0x0ffff29bu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH156 0x0ffff29cu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH157 0x0ffff29du
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH158 0x0ffff29eu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH159 0x0ffff29fu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH160 0x0ffff2a0u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH161 0x0ffff2a1u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH162 0x0ffff2a2u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH163 0x0ffff2a3u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH164 0x0ffff2a4u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH165 0x0ffff2a5u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH166 0x0ffff2a6u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH167 0x0ffff2a7u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH168 0x0ffff2a8u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH169 0x0ffff2a9u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH170 0x0ffff2aau
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH171 0x0ffff2abu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH172 0x0ffff2acu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH173 0x0ffff2adu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH174 0x0ffff2aeu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH175 0x0ffff2afu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH176 0x0ffff2b0u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH177 0x0ffff2b1u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH178 0x0ffff2b2u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH179 0x0ffff2b3u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH180 0x0ffff2b4u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH181 0x0ffff2b5u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH182 0x0ffff2b6u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH183 0x0ffff2b7u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH184 0x0ffff2b8u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH185 0x0ffff2b9u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH186 0x0ffff2bau
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH187 0x0ffff2bbu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH188 0x0ffff2bcu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH189 0x0ffff2bdu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH190 0x0ffff2beu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH191 0x0ffff2bfu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH192 0x0ffff2c0u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH193 0x0ffff2c1u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH194 0x0ffff2c2u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH195 0x0ffff2c3u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH196 0x0ffff2c4u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH197 0x0ffff2c5u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH198 0x0ffff2c6u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH199 0x0ffff2c7u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH200 0x0ffff2c8u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH201 0x0ffff2c9u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH202 0x0ffff2cau
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH203 0x0ffff2cbu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH204 0x0ffff2ccu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH205 0x0ffff2cdu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH206 0x0ffff2ceu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH207 0x0ffff2cfu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH208 0x0ffff2d0u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH209 0x0ffff2d1u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH210 0x0ffff2d2u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH211 0x0ffff2d3u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH212 0x0ffff2d4u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH213 0x0ffff2d5u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH214 0x0ffff2d6u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH215 0x0ffff2d7u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH216 0x0ffff2d8u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH217 0x0ffff2d9u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH218 0x0ffff2dau
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH219 0x0ffff2dbu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH220 0x0ffff2dcu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH221 0x0ffff2ddu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH222 0x0ffff2deu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH223 0x0ffff2dfu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH224 0x0ffff2e0u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH225 0x0ffff2e1u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH226 0x0ffff2e2u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH227 0x0ffff2e3u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH228 0x0ffff2e4u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH229 0x0ffff2e5u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH230 0x0ffff2e6u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH231 0x0ffff2e7u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH232 0x0ffff2e8u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH233 0x0ffff2e9u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH234 0x0ffff2eau
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH235 0x0ffff2ebu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH236 0x0ffff2ecu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH237 0x0ffff2edu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH238 0x0ffff2eeu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH239 0x0ffff2efu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH240 0x0ffff2f0u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH241 0x0ffff2f1u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH242 0x0ffff2f2u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH243 0x0ffff2f3u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH244 0x0ffff2f4u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH245 0x0ffff2f5u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH246 0x0ffff2f6u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH247 0x0ffff2f7u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH248 0x0ffff2f8u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH249 0x0ffff2f9u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH250 0x0ffff2fau
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH251 0x0ffff2fbu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH252 0x0ffff2fcu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH253 0x0ffff2fdu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH254 0x0ffff2feu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH255 0x0ffff2ffu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH256 0x0ffff300u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH257 0x0ffff301u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH258 0x0ffff302u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH259 0x0ffff303u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH260 0x0ffff304u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH261 0x0ffff305u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH262 0x0ffff306u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH263 0x0ffff307u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH264 0x0ffff308u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH265 0x0ffff309u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH266 0x0ffff30au
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH267 0x0ffff30bu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH268 0x0ffff30cu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH269 0x0ffff30du
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH270 0x0ffff30eu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH271 0x0ffff30fu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH272 0x0ffff310u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH273 0x0ffff311u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH274 0x0ffff312u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH275 0x0ffff313u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH276 0x0ffff314u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH277 0x0ffff315u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH278 0x0ffff316u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH279 0x0ffff317u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH280 0x0ffff318u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH281 0x0ffff319u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH282 0x0ffff31au
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH283 0x0ffff31bu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH284 0x0ffff31cu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH285 0x0ffff31du
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH286 0x0ffff31eu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH287 0x0ffff31fu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH288 0x0ffff320u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH289 0x0ffff321u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH290 0x0ffff322u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH291 0x0ffff323u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH292 0x0ffff324u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH293 0x0ffff325u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH294 0x0ffff326u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH295 0x0ffff327u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH296 0x0ffff328u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH297 0x0ffff329u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH298 0x0ffff32au
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH299 0x0ffff32bu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH300 0x0ffff32cu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH301 0x0ffff32du
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH302 0x0ffff32eu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH303 0x0ffff32fu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH304 0x0ffff330u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH305 0x0ffff331u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH306 0x0ffff332u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH307 0x0ffff333u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH308 0x0ffff334u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH309 0x0ffff335u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH310 0x0ffff336u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH311 0x0ffff337u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH312 0x0ffff338u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH313 0x0ffff339u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH314 0x0ffff33au
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH315 0x0ffff33bu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH316 0x0ffff33cu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH317 0x0ffff33du
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH318 0x0ffff33eu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH319 0x0ffff33fu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH320 0x0ffff340u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH321 0x0ffff341u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH322 0x0ffff342u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH323 0x0ffff343u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH324 0x0ffff344u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH325 0x0ffff345u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH326 0x0ffff346u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH327 0x0ffff347u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH328 0x0ffff348u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH329 0x0ffff349u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH330 0x0ffff34au
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH331 0x0ffff34bu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH332 0x0ffff34cu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH333 0x0ffff34du
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH334 0x0ffff34eu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH335 0x0ffff34fu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH336 0x0ffff350u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH337 0x0ffff351u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH338 0x0ffff352u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH339 0x0ffff353u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH340 0x0ffff354u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH341 0x0ffff355u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH342 0x0ffff356u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH343 0x0ffff357u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH344 0x0ffff358u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH345 0x0ffff359u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH346 0x0ffff35au
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH347 0x0ffff35bu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH348 0x0ffff35cu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH349 0x0ffff35du
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH350 0x0ffff35eu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH351 0x0ffff35fu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH352 0x0ffff360u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH353 0x0ffff361u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH354 0x0ffff362u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH355 0x0ffff363u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH356 0x0ffff364u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH357 0x0ffff365u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH358 0x0ffff366u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH359 0x0ffff367u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH360 0x0ffff368u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH361 0x0ffff369u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH362 0x0ffff36au
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH363 0x0ffff36bu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH364 0x0ffff36cu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH365 0x0ffff36du
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH366 0x0ffff36eu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH367 0x0ffff36fu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH368 0x0ffff370u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH369 0x0ffff371u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH370 0x0ffff372u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH371 0x0ffff373u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH372 0x0ffff374u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH373 0x0ffff375u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH374 0x0ffff376u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH375 0x0ffff377u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH376 0x0ffff378u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH377 0x0ffff379u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH378 0x0ffff37au
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH379 0x0ffff37bu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH380 0x0ffff37cu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH381 0x0ffff37du
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH382 0x0ffff37eu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH383 0x0ffff37fu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH384 0x0ffff380u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH385 0x0ffff381u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH386 0x0ffff382u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH387 0x0ffff383u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH388 0x0ffff384u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH389 0x0ffff385u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH390 0x0ffff386u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH391 0x0ffff387u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH392 0x0ffff388u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH393 0x0ffff389u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH394 0x0ffff38au
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH395 0x0ffff38bu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH396 0x0ffff38cu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH397 0x0ffff38du
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH398 0x0ffff38eu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH399 0x0ffff38fu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH400 0x0ffff390u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH401 0x0ffff391u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH402 0x0ffff392u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH403 0x0ffff393u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH404 0x0ffff394u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH405 0x0ffff395u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH406 0x0ffff396u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH407 0x0ffff397u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH408 0x0ffff398u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH409 0x0ffff399u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH410 0x0ffff39au
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH411 0x0ffff39bu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH412 0x0ffff39cu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH413 0x0ffff39du
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH414 0x0ffff39eu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH415 0x0ffff39fu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH416 0x0ffff3a0u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH417 0x0ffff3a1u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH418 0x0ffff3a2u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH419 0x0ffff3a3u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH420 0x0ffff3a4u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH421 0x0ffff3a5u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH422 0x0ffff3a6u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH423 0x0ffff3a7u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH424 0x0ffff3a8u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH425 0x0ffff3a9u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH426 0x0ffff3aau
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH427 0x0ffff3abu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH428 0x0ffff3acu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH429 0x0ffff3adu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH430 0x0ffff3aeu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH431 0x0ffff3afu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH432 0x0ffff3b0u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH433 0x0ffff3b1u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH434 0x0ffff3b2u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH435 0x0ffff3b3u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH436 0x0ffff3b4u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH437 0x0ffff3b5u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH438 0x0ffff3b6u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH439 0x0ffff3b7u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH440 0x0ffff3b8u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH441 0x0ffff3b9u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH442 0x0ffff3bau
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH443 0x0ffff3bbu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH444 0x0ffff3bcu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH445 0x0ffff3bdu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH446 0x0ffff3beu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH447 0x0ffff3bfu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH448 0x0ffff3c0u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH449 0x0ffff3c1u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH450 0x0ffff3c2u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH451 0x0ffff3c3u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH452 0x0ffff3c4u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH453 0x0ffff3c5u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH454 0x0ffff3c6u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH455 0x0ffff3c7u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH456 0x0ffff3c8u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH457 0x0ffff3c9u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH458 0x0ffff3cau
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH459 0x0ffff3cbu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH460 0x0ffff3ccu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH461 0x0ffff3cdu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH462 0x0ffff3ceu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH463 0x0ffff3cfu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH464 0x0ffff3d0u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH465 0x0ffff3d1u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH466 0x0ffff3d2u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH467 0x0ffff3d3u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH468 0x0ffff3d4u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH469 0x0ffff3d5u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH470 0x0ffff3d6u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH471 0x0ffff3d7u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH472 0x0ffff3d8u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH473 0x0ffff3d9u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH474 0x0ffff3dau
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH475 0x0ffff3dbu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH476 0x0ffff3dcu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH477 0x0ffff3ddu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH478 0x0ffff3deu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH479 0x0ffff3dfu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH480 0x0ffff3e0u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH481 0x0ffff3e1u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH482 0x0ffff3e2u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH483 0x0ffff3e3u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH484 0x0ffff3e4u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH485 0x0ffff3e5u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH486 0x0ffff3e6u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH487 0x0ffff3e7u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH488 0x0ffff3e8u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH489 0x0ffff3e9u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH490 0x0ffff3eau
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH491 0x0ffff3ebu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH492 0x0ffff3ecu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH493 0x0ffff3edu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH494 0x0ffff3eeu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH495 0x0ffff3efu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH496 0x0ffff3f0u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH497 0x0ffff3f1u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH498 0x0ffff3f2u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH499 0x0ffff3f3u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH500 0x0ffff3f4u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH501 0x0ffff3f5u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH502 0x0ffff3f6u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH503 0x0ffff3f7u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH504 0x0ffff3f8u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH505 0x0ffff3f9u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH506 0x0ffff3fau
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH507 0x0ffff3fbu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH508 0x0ffff3fcu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH509 0x0ffff3fdu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH510 0x0ffff3feu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH511 0x0ffff3ffu
#define CYREG_SFLASH_ALT_PROT_ROW0 0x0ffff400u
#define CYREG_SFLASH_ALT_PROT_ROW1 0x0ffff401u
#define CYREG_SFLASH_ALT_PROT_ROW2 0x0ffff402u
#define CYREG_SFLASH_ALT_PROT_ROW3 0x0ffff403u
#define CYREG_SFLASH_ALT_PROT_ROW4 0x0ffff404u
#define CYREG_SFLASH_ALT_PROT_ROW5 0x0ffff405u
#define CYREG_SFLASH_ALT_PROT_ROW6 0x0ffff406u
#define CYREG_SFLASH_ALT_PROT_ROW7 0x0ffff407u
#define CYREG_SFLASH_ALT_PROT_ROW8 0x0ffff408u
#define CYREG_SFLASH_ALT_PROT_ROW9 0x0ffff409u
#define CYREG_SFLASH_ALT_PROT_ROW10 0x0ffff40au
#define CYREG_SFLASH_ALT_PROT_ROW11 0x0ffff40bu
#define CYREG_SFLASH_ALT_PROT_ROW12 0x0ffff40cu
#define CYREG_SFLASH_ALT_PROT_ROW13 0x0ffff40du
#define CYREG_SFLASH_ALT_PROT_ROW14 0x0ffff40eu
#define CYREG_SFLASH_ALT_PROT_ROW15 0x0ffff40fu
#define CYREG_SFLASH_ALT_PROT_ROW16 0x0ffff410u
#define CYREG_SFLASH_ALT_PROT_ROW17 0x0ffff411u
#define CYREG_SFLASH_ALT_PROT_ROW18 0x0ffff412u
#define CYREG_SFLASH_ALT_PROT_ROW19 0x0ffff413u
#define CYREG_SFLASH_ALT_PROT_ROW20 0x0ffff414u
#define CYREG_SFLASH_ALT_PROT_ROW21 0x0ffff415u
#define CYREG_SFLASH_ALT_PROT_ROW22 0x0ffff416u
#define CYREG_SFLASH_ALT_PROT_ROW23 0x0ffff417u
#define CYREG_SFLASH_ALT_PROT_ROW24 0x0ffff418u
#define CYREG_SFLASH_ALT_PROT_ROW25 0x0ffff419u
#define CYREG_SFLASH_ALT_PROT_ROW26 0x0ffff41au
#define CYREG_SFLASH_ALT_PROT_ROW27 0x0ffff41bu
#define CYREG_SFLASH_ALT_PROT_ROW28 0x0ffff41cu
#define CYREG_SFLASH_ALT_PROT_ROW29 0x0ffff41du
#define CYREG_SFLASH_ALT_PROT_ROW30 0x0ffff41eu
#define CYREG_SFLASH_ALT_PROT_ROW31 0x0ffff41fu
#define CYREG_SFLASH_ALT_PROT_ROW32 0x0ffff420u
#define CYREG_SFLASH_ALT_PROT_ROW33 0x0ffff421u
#define CYREG_SFLASH_ALT_PROT_ROW34 0x0ffff422u
#define CYREG_SFLASH_ALT_PROT_ROW35 0x0ffff423u
#define CYREG_SFLASH_ALT_PROT_ROW36 0x0ffff424u
#define CYREG_SFLASH_ALT_PROT_ROW37 0x0ffff425u
#define CYREG_SFLASH_ALT_PROT_ROW38 0x0ffff426u
#define CYREG_SFLASH_ALT_PROT_ROW39 0x0ffff427u
#define CYREG_SFLASH_ALT_PROT_ROW40 0x0ffff428u
#define CYREG_SFLASH_ALT_PROT_ROW41 0x0ffff429u
#define CYREG_SFLASH_ALT_PROT_ROW42 0x0ffff42au
#define CYREG_SFLASH_ALT_PROT_ROW43 0x0ffff42bu
#define CYREG_SFLASH_ALT_PROT_ROW44 0x0ffff42cu
#define CYREG_SFLASH_ALT_PROT_ROW45 0x0ffff42du
#define CYREG_SFLASH_ALT_PROT_ROW46 0x0ffff42eu
#define CYREG_SFLASH_ALT_PROT_ROW47 0x0ffff42fu
#define CYREG_SFLASH_ALT_PROT_ROW48 0x0ffff430u
#define CYREG_SFLASH_ALT_PROT_ROW49 0x0ffff431u
#define CYREG_SFLASH_ALT_PROT_ROW50 0x0ffff432u
#define CYREG_SFLASH_ALT_PROT_ROW51 0x0ffff433u
#define CYREG_SFLASH_ALT_PROT_ROW52 0x0ffff434u
#define CYREG_SFLASH_ALT_PROT_ROW53 0x0ffff435u
#define CYREG_SFLASH_ALT_PROT_ROW54 0x0ffff436u
#define CYREG_SFLASH_ALT_PROT_ROW55 0x0ffff437u
#define CYREG_SFLASH_ALT_PROT_ROW56 0x0ffff438u
#define CYREG_SFLASH_ALT_PROT_ROW57 0x0ffff439u
#define CYREG_SFLASH_ALT_PROT_ROW58 0x0ffff43au
#define CYREG_SFLASH_ALT_PROT_ROW59 0x0ffff43bu
#define CYREG_SFLASH_ALT_PROT_ROW60 0x0ffff43cu
#define CYREG_SFLASH_ALT_PROT_ROW61 0x0ffff43du
#define CYREG_SFLASH_ALT_PROT_ROW62 0x0ffff43eu
#define CYREG_SFLASH_ALT_PROT_ROW63 0x0ffff43fu
#define CYREG_SFLASH_ALT_PROT_ROW64 0x0ffff440u
#define CYREG_SFLASH_ALT_PROT_ROW65 0x0ffff441u
#define CYREG_SFLASH_ALT_PROT_ROW66 0x0ffff442u
#define CYREG_SFLASH_ALT_PROT_ROW67 0x0ffff443u
#define CYREG_SFLASH_ALT_PROT_ROW68 0x0ffff444u
#define CYREG_SFLASH_ALT_PROT_ROW69 0x0ffff445u
#define CYREG_SFLASH_ALT_PROT_ROW70 0x0ffff446u
#define CYREG_SFLASH_ALT_PROT_ROW71 0x0ffff447u
#define CYREG_SFLASH_ALT_PROT_ROW72 0x0ffff448u
#define CYREG_SFLASH_ALT_PROT_ROW73 0x0ffff449u
#define CYREG_SFLASH_ALT_PROT_ROW74 0x0ffff44au
#define CYREG_SFLASH_ALT_PROT_ROW75 0x0ffff44bu
#define CYREG_SFLASH_ALT_PROT_ROW76 0x0ffff44cu
#define CYREG_SFLASH_ALT_PROT_ROW77 0x0ffff44du
#define CYREG_SFLASH_ALT_PROT_ROW78 0x0ffff44eu
#define CYREG_SFLASH_ALT_PROT_ROW79 0x0ffff44fu
#define CYREG_SFLASH_ALT_PROT_ROW80 0x0ffff450u
#define CYREG_SFLASH_ALT_PROT_ROW81 0x0ffff451u
#define CYREG_SFLASH_ALT_PROT_ROW82 0x0ffff452u
#define CYREG_SFLASH_ALT_PROT_ROW83 0x0ffff453u
#define CYREG_SFLASH_ALT_PROT_ROW84 0x0ffff454u
#define CYREG_SFLASH_ALT_PROT_ROW85 0x0ffff455u
#define CYREG_SFLASH_ALT_PROT_ROW86 0x0ffff456u
#define CYREG_SFLASH_ALT_PROT_ROW87 0x0ffff457u
#define CYREG_SFLASH_ALT_PROT_ROW88 0x0ffff458u
#define CYREG_SFLASH_ALT_PROT_ROW89 0x0ffff459u
#define CYREG_SFLASH_ALT_PROT_ROW90 0x0ffff45au
#define CYREG_SFLASH_ALT_PROT_ROW91 0x0ffff45bu
#define CYREG_SFLASH_ALT_PROT_ROW92 0x0ffff45cu
#define CYREG_SFLASH_ALT_PROT_ROW93 0x0ffff45du
#define CYREG_SFLASH_ALT_PROT_ROW94 0x0ffff45eu
#define CYREG_SFLASH_ALT_PROT_ROW95 0x0ffff45fu
#define CYREG_SFLASH_ALT_PROT_ROW96 0x0ffff460u
#define CYREG_SFLASH_ALT_PROT_ROW97 0x0ffff461u
#define CYREG_SFLASH_ALT_PROT_ROW98 0x0ffff462u
#define CYREG_SFLASH_ALT_PROT_ROW99 0x0ffff463u
#define CYREG_SFLASH_ALT_PROT_ROW100 0x0ffff464u
#define CYREG_SFLASH_ALT_PROT_ROW101 0x0ffff465u
#define CYREG_SFLASH_ALT_PROT_ROW102 0x0ffff466u
#define CYREG_SFLASH_ALT_PROT_ROW103 0x0ffff467u
#define CYREG_SFLASH_ALT_PROT_ROW104 0x0ffff468u
#define CYREG_SFLASH_ALT_PROT_ROW105 0x0ffff469u
#define CYREG_SFLASH_ALT_PROT_ROW106 0x0ffff46au
#define CYREG_SFLASH_ALT_PROT_ROW107 0x0ffff46bu
#define CYREG_SFLASH_ALT_PROT_ROW108 0x0ffff46cu
#define CYREG_SFLASH_ALT_PROT_ROW109 0x0ffff46du
#define CYREG_SFLASH_ALT_PROT_ROW110 0x0ffff46eu
#define CYREG_SFLASH_ALT_PROT_ROW111 0x0ffff46fu
#define CYREG_SFLASH_ALT_PROT_ROW112 0x0ffff470u
#define CYREG_SFLASH_ALT_PROT_ROW113 0x0ffff471u
#define CYREG_SFLASH_ALT_PROT_ROW114 0x0ffff472u
#define CYREG_SFLASH_ALT_PROT_ROW115 0x0ffff473u
#define CYREG_SFLASH_ALT_PROT_ROW116 0x0ffff474u
#define CYREG_SFLASH_ALT_PROT_ROW117 0x0ffff475u
#define CYREG_SFLASH_ALT_PROT_ROW118 0x0ffff476u
#define CYREG_SFLASH_ALT_PROT_ROW119 0x0ffff477u
#define CYREG_SFLASH_ALT_PROT_ROW120 0x0ffff478u
#define CYREG_SFLASH_ALT_PROT_ROW121 0x0ffff479u
#define CYREG_SFLASH_ALT_PROT_ROW122 0x0ffff47au
#define CYREG_SFLASH_ALT_PROT_ROW123 0x0ffff47bu
#define CYREG_SFLASH_ALT_PROT_ROW124 0x0ffff47cu
#define CYREG_SFLASH_ALT_PROT_ROW125 0x0ffff47du
#define CYREG_SFLASH_ALT_PROT_ROW126 0x0ffff47eu
#define CYREG_SFLASH_ALT_PROT_ROW127 0x0ffff47fu
#define CYREG_SFLASH_ALT_PROT_ROW128 0x0ffff480u
#define CYREG_SFLASH_ALT_PROT_ROW129 0x0ffff481u
#define CYREG_SFLASH_ALT_PROT_ROW130 0x0ffff482u
#define CYREG_SFLASH_ALT_PROT_ROW131 0x0ffff483u
#define CYREG_SFLASH_ALT_PROT_ROW132 0x0ffff484u
#define CYREG_SFLASH_ALT_PROT_ROW133 0x0ffff485u
#define CYREG_SFLASH_ALT_PROT_ROW134 0x0ffff486u
#define CYREG_SFLASH_ALT_PROT_ROW135 0x0ffff487u
#define CYREG_SFLASH_ALT_PROT_ROW136 0x0ffff488u
#define CYREG_SFLASH_ALT_PROT_ROW137 0x0ffff489u
#define CYREG_SFLASH_ALT_PROT_ROW138 0x0ffff48au
#define CYREG_SFLASH_ALT_PROT_ROW139 0x0ffff48bu
#define CYREG_SFLASH_ALT_PROT_ROW140 0x0ffff48cu
#define CYREG_SFLASH_ALT_PROT_ROW141 0x0ffff48du
#define CYREG_SFLASH_ALT_PROT_ROW142 0x0ffff48eu
#define CYREG_SFLASH_ALT_PROT_ROW143 0x0ffff48fu
#define CYREG_SFLASH_ALT_PROT_ROW144 0x0ffff490u
#define CYREG_SFLASH_ALT_PROT_ROW145 0x0ffff491u
#define CYREG_SFLASH_ALT_PROT_ROW146 0x0ffff492u
#define CYREG_SFLASH_ALT_PROT_ROW147 0x0ffff493u
#define CYREG_SFLASH_ALT_PROT_ROW148 0x0ffff494u
#define CYREG_SFLASH_ALT_PROT_ROW149 0x0ffff495u
#define CYREG_SFLASH_ALT_PROT_ROW150 0x0ffff496u
#define CYREG_SFLASH_ALT_PROT_ROW151 0x0ffff497u
#define CYREG_SFLASH_ALT_PROT_ROW152 0x0ffff498u
#define CYREG_SFLASH_ALT_PROT_ROW153 0x0ffff499u
#define CYREG_SFLASH_ALT_PROT_ROW154 0x0ffff49au
#define CYREG_SFLASH_ALT_PROT_ROW155 0x0ffff49bu
#define CYREG_SFLASH_ALT_PROT_ROW156 0x0ffff49cu
#define CYREG_SFLASH_ALT_PROT_ROW157 0x0ffff49du
#define CYREG_SFLASH_ALT_PROT_ROW158 0x0ffff49eu
#define CYREG_SFLASH_ALT_PROT_ROW159 0x0ffff49fu
#define CYREG_SFLASH_ALT_PROT_ROW160 0x0ffff4a0u
#define CYREG_SFLASH_ALT_PROT_ROW161 0x0ffff4a1u
#define CYREG_SFLASH_ALT_PROT_ROW162 0x0ffff4a2u
#define CYREG_SFLASH_ALT_PROT_ROW163 0x0ffff4a3u
#define CYREG_SFLASH_ALT_PROT_ROW164 0x0ffff4a4u
#define CYREG_SFLASH_ALT_PROT_ROW165 0x0ffff4a5u
#define CYREG_SFLASH_ALT_PROT_ROW166 0x0ffff4a6u
#define CYREG_SFLASH_ALT_PROT_ROW167 0x0ffff4a7u
#define CYREG_SFLASH_ALT_PROT_ROW168 0x0ffff4a8u
#define CYREG_SFLASH_ALT_PROT_ROW169 0x0ffff4a9u
#define CYREG_SFLASH_ALT_PROT_ROW170 0x0ffff4aau
#define CYREG_SFLASH_ALT_PROT_ROW171 0x0ffff4abu
#define CYREG_SFLASH_ALT_PROT_ROW172 0x0ffff4acu
#define CYREG_SFLASH_ALT_PROT_ROW173 0x0ffff4adu
#define CYREG_SFLASH_ALT_PROT_ROW174 0x0ffff4aeu
#define CYREG_SFLASH_ALT_PROT_ROW175 0x0ffff4afu
#define CYREG_SFLASH_ALT_PROT_ROW176 0x0ffff4b0u
#define CYREG_SFLASH_ALT_PROT_ROW177 0x0ffff4b1u
#define CYREG_SFLASH_ALT_PROT_ROW178 0x0ffff4b2u
#define CYREG_SFLASH_ALT_PROT_ROW179 0x0ffff4b3u
#define CYREG_SFLASH_ALT_PROT_ROW180 0x0ffff4b4u
#define CYREG_SFLASH_ALT_PROT_ROW181 0x0ffff4b5u
#define CYREG_SFLASH_ALT_PROT_ROW182 0x0ffff4b6u
#define CYREG_SFLASH_ALT_PROT_ROW183 0x0ffff4b7u
#define CYREG_SFLASH_ALT_PROT_ROW184 0x0ffff4b8u
#define CYREG_SFLASH_ALT_PROT_ROW185 0x0ffff4b9u
#define CYREG_SFLASH_ALT_PROT_ROW186 0x0ffff4bau
#define CYREG_SFLASH_ALT_PROT_ROW187 0x0ffff4bbu
#define CYREG_SFLASH_ALT_PROT_ROW188 0x0ffff4bcu
#define CYREG_SFLASH_ALT_PROT_ROW189 0x0ffff4bdu
#define CYREG_SFLASH_ALT_PROT_ROW190 0x0ffff4beu
#define CYREG_SFLASH_ALT_PROT_ROW191 0x0ffff4bfu
#define CYREG_SFLASH_ALT_PROT_ROW192 0x0ffff4c0u
#define CYREG_SFLASH_ALT_PROT_ROW193 0x0ffff4c1u
#define CYREG_SFLASH_ALT_PROT_ROW194 0x0ffff4c2u
#define CYREG_SFLASH_ALT_PROT_ROW195 0x0ffff4c3u
#define CYREG_SFLASH_ALT_PROT_ROW196 0x0ffff4c4u
#define CYREG_SFLASH_ALT_PROT_ROW197 0x0ffff4c5u
#define CYREG_SFLASH_ALT_PROT_ROW198 0x0ffff4c6u
#define CYREG_SFLASH_ALT_PROT_ROW199 0x0ffff4c7u
#define CYREG_SFLASH_ALT_PROT_ROW200 0x0ffff4c8u
#define CYREG_SFLASH_ALT_PROT_ROW201 0x0ffff4c9u
#define CYREG_SFLASH_ALT_PROT_ROW202 0x0ffff4cau
#define CYREG_SFLASH_ALT_PROT_ROW203 0x0ffff4cbu
#define CYREG_SFLASH_ALT_PROT_ROW204 0x0ffff4ccu
#define CYREG_SFLASH_ALT_PROT_ROW205 0x0ffff4cdu
#define CYREG_SFLASH_ALT_PROT_ROW206 0x0ffff4ceu
#define CYREG_SFLASH_ALT_PROT_ROW207 0x0ffff4cfu
#define CYREG_SFLASH_ALT_PROT_ROW208 0x0ffff4d0u
#define CYREG_SFLASH_ALT_PROT_ROW209 0x0ffff4d1u
#define CYREG_SFLASH_ALT_PROT_ROW210 0x0ffff4d2u
#define CYREG_SFLASH_ALT_PROT_ROW211 0x0ffff4d3u
#define CYREG_SFLASH_ALT_PROT_ROW212 0x0ffff4d4u
#define CYREG_SFLASH_ALT_PROT_ROW213 0x0ffff4d5u
#define CYREG_SFLASH_ALT_PROT_ROW214 0x0ffff4d6u
#define CYREG_SFLASH_ALT_PROT_ROW215 0x0ffff4d7u
#define CYREG_SFLASH_ALT_PROT_ROW216 0x0ffff4d8u
#define CYREG_SFLASH_ALT_PROT_ROW217 0x0ffff4d9u
#define CYREG_SFLASH_ALT_PROT_ROW218 0x0ffff4dau
#define CYREG_SFLASH_ALT_PROT_ROW219 0x0ffff4dbu
#define CYREG_SFLASH_ALT_PROT_ROW220 0x0ffff4dcu
#define CYREG_SFLASH_ALT_PROT_ROW221 0x0ffff4ddu
#define CYREG_SFLASH_ALT_PROT_ROW222 0x0ffff4deu
#define CYREG_SFLASH_ALT_PROT_ROW223 0x0ffff4dfu
#define CYREG_SFLASH_ALT_PROT_ROW224 0x0ffff4e0u
#define CYREG_SFLASH_ALT_PROT_ROW225 0x0ffff4e1u
#define CYREG_SFLASH_ALT_PROT_ROW226 0x0ffff4e2u
#define CYREG_SFLASH_ALT_PROT_ROW227 0x0ffff4e3u
#define CYREG_SFLASH_ALT_PROT_ROW228 0x0ffff4e4u
#define CYREG_SFLASH_ALT_PROT_ROW229 0x0ffff4e5u
#define CYREG_SFLASH_ALT_PROT_ROW230 0x0ffff4e6u
#define CYREG_SFLASH_ALT_PROT_ROW231 0x0ffff4e7u
#define CYREG_SFLASH_ALT_PROT_ROW232 0x0ffff4e8u
#define CYREG_SFLASH_ALT_PROT_ROW233 0x0ffff4e9u
#define CYREG_SFLASH_ALT_PROT_ROW234 0x0ffff4eau
#define CYREG_SFLASH_ALT_PROT_ROW235 0x0ffff4ebu
#define CYREG_SFLASH_ALT_PROT_ROW236 0x0ffff4ecu
#define CYREG_SFLASH_ALT_PROT_ROW237 0x0ffff4edu
#define CYREG_SFLASH_ALT_PROT_ROW238 0x0ffff4eeu
#define CYREG_SFLASH_ALT_PROT_ROW239 0x0ffff4efu
#define CYREG_SFLASH_ALT_PROT_ROW240 0x0ffff4f0u
#define CYREG_SFLASH_ALT_PROT_ROW241 0x0ffff4f1u
#define CYREG_SFLASH_ALT_PROT_ROW242 0x0ffff4f2u
#define CYREG_SFLASH_ALT_PROT_ROW243 0x0ffff4f3u
#define CYREG_SFLASH_ALT_PROT_ROW244 0x0ffff4f4u
#define CYREG_SFLASH_ALT_PROT_ROW245 0x0ffff4f5u
#define CYREG_SFLASH_ALT_PROT_ROW246 0x0ffff4f6u
#define CYREG_SFLASH_ALT_PROT_ROW247 0x0ffff4f7u
#define CYREG_SFLASH_ALT_PROT_ROW248 0x0ffff4f8u
#define CYREG_SFLASH_ALT_PROT_ROW249 0x0ffff4f9u
#define CYREG_SFLASH_ALT_PROT_ROW250 0x0ffff4fau
#define CYREG_SFLASH_ALT_PROT_ROW251 0x0ffff4fbu
#define CYREG_SFLASH_ALT_PROT_ROW252 0x0ffff4fcu
#define CYREG_SFLASH_ALT_PROT_ROW253 0x0ffff4fdu
#define CYREG_SFLASH_ALT_PROT_ROW254 0x0ffff4feu
#define CYREG_SFLASH_ALT_PROT_ROW255 0x0ffff4ffu
#define CYREG_SFLASH_ALT_PP 0x0ffff5a0u
#define CYREG_SFLASH_ALT_E 0x0ffff5a4u
#define CYREG_SFLASH_ALT_P 0x0ffff5a8u
#define CYREG_SFLASH_ALT_EA_E 0x0ffff5acu
#define CYREG_SFLASH_ALT_EA_P 0x0ffff5b0u
#define CYREG_SFLASH_ALT_ES_E 0x0ffff5b4u
#define CYREG_SFLASH_ALT_ES_P_EO 0x0ffff5b8u
#define CYREG_SFLASH_ALT_E_VCTAT 0x0ffff5bcu
#define CYFLD_SFLASH_VCTAT_SLOPE__OFFSET 0x00000000u
#define CYFLD_SFLASH_VCTAT_SLOPE__SIZE 0x00000004u
#define CYFLD_SFLASH_VCTAT_VOLTAGE__OFFSET 0x00000004u
#define CYFLD_SFLASH_VCTAT_VOLTAGE__SIZE 0x00000002u
#define CYFLD_SFLASH_VCTAT_ENABLE__OFFSET 0x00000006u
#define CYFLD_SFLASH_VCTAT_ENABLE__SIZE 0x00000001u
#define CYREG_SFLASH_ALT_P_VCTAT 0x0ffff5bdu
#define CYDEV_ROM_BASE 0x10000000u
#define CYDEV_ROM_SIZE 0x00002000u
#define CYREG_ROM_DATA_MBASE 0x10000000u
#define CYREG_ROM_DATA_MSIZE 0x00002000u
#define CYDEV_SRAM_BASE 0x20000000u
#define CYDEV_SRAM_SIZE 0x00002000u
#define CYREG_SRAM_DATA_MBASE 0x20000000u
#define CYREG_SRAM_DATA_MSIZE 0x00002000u
#define CYDEV_PERI_BASE 0x40010000u
#define CYDEV_PERI_SIZE 0x00010000u
#define CYREG_PERI_DIV_CMD 0x40010000u
#define CYFLD_PERI_SEL_DIV__OFFSET 0x00000000u
#define CYFLD_PERI_SEL_DIV__SIZE 0x00000006u
#define CYFLD_PERI_SEL_TYPE__OFFSET 0x00000006u
#define CYFLD_PERI_SEL_TYPE__SIZE 0x00000002u
#define CYFLD_PERI_PA_SEL_DIV__OFFSET 0x00000008u
#define CYFLD_PERI_PA_SEL_DIV__SIZE 0x00000006u
#define CYFLD_PERI_PA_SEL_TYPE__OFFSET 0x0000000eu
#define CYFLD_PERI_PA_SEL_TYPE__SIZE 0x00000002u
#define CYFLD_PERI_DISABLE__OFFSET 0x0000001eu
#define CYFLD_PERI_DISABLE__SIZE 0x00000001u
#define CYFLD_PERI_ENABLE__OFFSET 0x0000001fu
#define CYFLD_PERI_ENABLE__SIZE 0x00000001u
#define CYREG_PERI_PCLK_CTL0 0x40010100u
/* Duplicate field name in PERI: SEL_DIV [1:0] (previous: [5:0]) */
#define CYREG_PERI_PCLK_CTL1 0x40010104u
#define CYREG_PERI_PCLK_CTL2 0x40010108u
#define CYREG_PERI_PCLK_CTL3 0x4001010cu
#define CYREG_PERI_PCLK_CTL4 0x40010110u
#define CYREG_PERI_PCLK_CTL5 0x40010114u
#define CYREG_PERI_PCLK_CTL6 0x40010118u
#define CYREG_PERI_PCLK_CTL7 0x4001011cu
#define CYREG_PERI_PCLK_CTL8 0x40010120u
#define CYREG_PERI_PCLK_CTL9 0x40010124u
#define CYREG_PERI_PCLK_CTL10 0x40010128u
#define CYREG_PERI_PCLK_CTL11 0x4001012cu
#define CYREG_PERI_DIV_8_CTL0 0x40010200u
#define CYFLD_PERI_EN__OFFSET 0x00000000u
#define CYFLD_PERI_EN__SIZE 0x00000001u
#define CYFLD_PERI_INT8_DIV__OFFSET 0x00000008u
#define CYFLD_PERI_INT8_DIV__SIZE 0x00000008u
#define CYREG_PERI_DIV_8_CTL1 0x40010204u
#define CYREG_PERI_DIV_8_CTL2 0x40010208u
#define CYREG_PERI_DIV_8_CTL3 0x4001020cu
#define CYREG_PERI_DIV_16_CTL0 0x40010300u
#define CYFLD_PERI_INT16_DIV__OFFSET 0x00000008u
#define CYFLD_PERI_INT16_DIV__SIZE 0x00000010u
#define CYREG_PERI_DIV_16_CTL1 0x40010304u
#define CYREG_PERI_DIV_16_CTL2 0x40010308u
#define CYREG_PERI_DIV_16_CTL3 0x4001030cu
#define CYREG_PERI_DIV_16_5_CTL0 0x40010400u
#define CYFLD_PERI_FRAC5_DIV__OFFSET 0x00000003u
#define CYFLD_PERI_FRAC5_DIV__SIZE 0x00000005u
#define CYREG_PERI_DIV_16_5_CTL1 0x40010404u
#define CYDEV_HSIOM_BASE 0x40020000u
#define CYDEV_HSIOM_SIZE 0x00004000u
#define CYREG_HSIOM_PORT_SEL0 0x40020000u
#define CYFLD_HSIOM_IO0_SEL__OFFSET 0x00000000u
#define CYFLD_HSIOM_IO0_SEL__SIZE 0x00000004u
#define CYVAL_HSIOM_IO0_SEL_GPIO 0x00000000u
#define CYVAL_HSIOM_IO0_SEL_GPIO_DSI 0x00000001u
#define CYVAL_HSIOM_IO0_SEL_DSI_DSI 0x00000002u
#define CYVAL_HSIOM_IO0_SEL_DSI_GPIO 0x00000003u
#define CYVAL_HSIOM_IO0_SEL_CSD_SENSE 0x00000004u
#define CYVAL_HSIOM_IO0_SEL_CSD_SHIELD 0x00000005u
#define CYVAL_HSIOM_IO0_SEL_AMUXA 0x00000006u
#define CYVAL_HSIOM_IO0_SEL_AMUXB 0x00000007u
#define CYVAL_HSIOM_IO0_SEL_ACT_0 0x00000008u
#define CYVAL_HSIOM_IO0_SEL_ACT_1 0x00000009u
#define CYVAL_HSIOM_IO0_SEL_ACT_2 0x0000000au
#define CYVAL_HSIOM_IO0_SEL_ACT_3 0x0000000bu
#define CYVAL_HSIOM_IO0_SEL_LCD_COM 0x0000000cu
#define CYVAL_HSIOM_IO0_SEL_LCD_SEG 0x0000000du
#define CYVAL_HSIOM_IO0_SEL_DS_0 0x0000000cu
#define CYVAL_HSIOM_IO0_SEL_DS_1 0x0000000du
#define CYVAL_HSIOM_IO0_SEL_DS_2 0x0000000eu
#define CYVAL_HSIOM_IO0_SEL_DS_3 0x0000000fu
#define CYFLD_HSIOM_IO1_SEL__OFFSET 0x00000004u
#define CYFLD_HSIOM_IO1_SEL__SIZE 0x00000004u
#define CYREG_HSIOM_PORT_SEL1 0x40020100u
#define CYFLD_HSIOM_IO2_SEL__OFFSET 0x00000008u
#define CYFLD_HSIOM_IO2_SEL__SIZE 0x00000004u
#define CYFLD_HSIOM_IO3_SEL__OFFSET 0x0000000cu
#define CYFLD_HSIOM_IO3_SEL__SIZE 0x00000004u
#define CYFLD_HSIOM_IO4_SEL__OFFSET 0x00000010u
#define CYFLD_HSIOM_IO4_SEL__SIZE 0x00000004u
#define CYFLD_HSIOM_IO5_SEL__OFFSET 0x00000014u
#define CYFLD_HSIOM_IO5_SEL__SIZE 0x00000004u
#define CYFLD_HSIOM_IO6_SEL__OFFSET 0x00000018u
#define CYFLD_HSIOM_IO6_SEL__SIZE 0x00000004u
#define CYFLD_HSIOM_IO7_SEL__OFFSET 0x0000001cu
#define CYFLD_HSIOM_IO7_SEL__SIZE 0x00000004u
#define CYREG_HSIOM_PORT_SEL2 0x40020200u
#define CYREG_HSIOM_PORT_SEL3 0x40020300u
#define CYREG_HSIOM_PORT_SEL4 0x40020400u
#define CYREG_PWR_CONTROL 0x40030000u
#define CYFLD__POWER_MODE__OFFSET 0x00000000u
#define CYFLD__POWER_MODE__SIZE 0x00000004u
#define CYVAL__POWER_MODE_RESET 0x00000000u
#define CYVAL__POWER_MODE_ACTIVE 0x00000001u
#define CYVAL__POWER_MODE_SLEEP 0x00000002u
#define CYVAL__POWER_MODE_DEEP_SLEEP 0x00000003u
#define CYFLD__DEBUG_SESSION__OFFSET 0x00000004u
#define CYFLD__DEBUG_SESSION__SIZE 0x00000001u
#define CYVAL__DEBUG_SESSION_NO_SESSION 0x00000000u
#define CYVAL__DEBUG_SESSION_SESSION_ACTIVE 0x00000001u
#define CYFLD__LPM_READY__OFFSET 0x00000005u
#define CYFLD__LPM_READY__SIZE 0x00000001u
#define CYFLD__OVER_TEMP_EN__OFFSET 0x00000010u
#define CYFLD__OVER_TEMP_EN__SIZE 0x00000001u
#define CYFLD__OVER_TEMP_THRESH__OFFSET 0x00000011u
#define CYFLD__OVER_TEMP_THRESH__SIZE 0x00000001u
#define CYFLD__SPARE__OFFSET 0x00000012u
#define CYFLD__SPARE__SIZE 0x00000002u
#define CYFLD__EXT_VCCD__OFFSET 0x00000017u
#define CYFLD__EXT_VCCD__SIZE 0x00000001u
#define CYREG_PWR_KEY_DELAY 0x40030004u
#define CYFLD__WAKEUP_HOLDOFF__OFFSET 0x00000000u
#define CYFLD__WAKEUP_HOLDOFF__SIZE 0x0000000au
#define CYREG_PWR_DDFT_SELECT 0x4003000cu
#define CYFLD__DDFT0_SEL__OFFSET 0x00000000u
#define CYFLD__DDFT0_SEL__SIZE 0x00000004u
#define CYVAL__DDFT0_SEL_WAKEUP 0x00000000u
#define CYVAL__DDFT0_SEL_AWAKE 0x00000001u
#define CYVAL__DDFT0_SEL_ACT_POWER_EN 0x00000002u
#define CYVAL__DDFT0_SEL_ACT_POWER_UP 0x00000003u
#define CYVAL__DDFT0_SEL_ACT_POWER_GOOD 0x00000004u
#define CYVAL__DDFT0_SEL_ACT_REF_EN 0x00000005u
#define CYVAL__DDFT0_SEL_ACT_COMP_EN 0x00000006u
#define CYVAL__DDFT0_SEL_DPSLP_REF_EN 0x00000007u
#define CYVAL__DDFT0_SEL_DPSLP_REG_EN 0x00000008u
#define CYVAL__DDFT0_SEL_DPSLP_COMP_EN 0x00000009u
#define CYVAL__DDFT0_SEL_OVER_TEMP_EN 0x0000000au
#define CYVAL__DDFT0_SEL_SLEEPHOLDREQ_N 0x0000000bu
#define CYVAL__DDFT0_SEL_ADFT_BUF_EN 0x0000000cu
#define CYVAL__DDFT0_SEL_ATPG_OBSERVE 0x0000000du
#define CYVAL__DDFT0_SEL_GND 0x0000000eu
#define CYVAL__DDFT0_SEL_PWR 0x0000000fu
#define CYFLD__DDFT1_SEL__OFFSET 0x00000004u
#define CYFLD__DDFT1_SEL__SIZE 0x00000004u
#define CYVAL__DDFT1_SEL_WAKEUP 0x00000000u
#define CYVAL__DDFT1_SEL_AWAKE 0x00000001u
#define CYVAL__DDFT1_SEL_ACT_POWER_EN 0x00000002u
#define CYVAL__DDFT1_SEL_ACT_POWER_UP 0x00000003u
#define CYVAL__DDFT1_SEL_ACT_POWER_GOOD 0x00000004u
#define CYVAL__DDFT1_SEL_ACT_REF_VALID 0x00000005u
#define CYVAL__DDFT1_SEL_ACT_REG_VALID 0x00000006u
#define CYVAL__DDFT1_SEL_ACT_COMP_OUT 0x00000007u
#define CYVAL__DDFT1_SEL_ACT_TEMP_HIGH 0x00000008u
#define CYVAL__DDFT1_SEL_DPSLP_COMP_OUT 0x00000009u
#define CYVAL__DDFT1_SEL_DPSLP_POWER_UP 0x0000000au
#define CYVAL__DDFT1_SEL_AWAKE_DELAYED 0x0000000bu
#define CYVAL__DDFT1_SEL_LPM_READY 0x0000000cu
#define CYVAL__DDFT1_SEL_SLEEPHOLDACK_N 0x0000000du
#define CYVAL__DDFT1_SEL_GND 0x0000000eu
#define CYVAL__DDFT1_SEL_PWR 0x0000000fu
#define CYREG_TST_MODE 0x40030014u
#define CYFLD__SWD_CONNECTED__OFFSET 0x00000002u
#define CYFLD__SWD_CONNECTED__SIZE 0x00000001u
#define CYFLD__BLOCK_ALT_XRES__OFFSET 0x0000001cu
#define CYFLD__BLOCK_ALT_XRES__SIZE 0x00000001u
#define CYFLD__TEST_KEY_DFT_EN__OFFSET 0x0000001eu
#define CYFLD__TEST_KEY_DFT_EN__SIZE 0x00000001u
#define CYFLD__TEST_MODE__OFFSET 0x0000001fu
#define CYFLD__TEST_MODE__SIZE 0x00000001u
#define CYREG_TST_DDFT_CTRL 0x40030018u
#define CYFLD__DFT_SEL0__OFFSET 0x00000000u
#define CYFLD__DFT_SEL0__SIZE 0x00000004u
#define CYVAL__DFT_SEL0_SRC0 0x00000000u
#define CYVAL__DFT_SEL0_SRC1 0x00000001u
#define CYVAL__DFT_SEL0_SRC2 0x00000002u
#define CYVAL__DFT_SEL0_SRC3 0x00000003u
#define CYVAL__DFT_SEL0_SRC4 0x00000004u
#define CYVAL__DFT_SEL0_SRC5 0x00000005u
#define CYVAL__DFT_SEL0_SRC6 0x00000006u
#define CYVAL__DFT_SEL0_SRC7 0x00000007u
#define CYVAL__DFT_SEL0_CLK0 0x00000008u
#define CYVAL__DFT_SEL0_CLK1 0x00000009u
#define CYVAL__DFT_SEL0_PWR0 0x0000000au
#define CYVAL__DFT_SEL0_PWR1 0x0000000bu
#define CYVAL__DFT_SEL0_RES0 0x0000000cu
#define CYVAL__DFT_SEL0_RES1 0x0000000du
#define CYVAL__DFT_SEL0_ADFT_COMP 0x0000000eu
#define CYVAL__DFT_SEL0_VSS 0x0000000fu
#define CYFLD__DFT_SEL1__OFFSET 0x00000008u
#define CYFLD__DFT_SEL1__SIZE 0x00000004u
#define CYVAL__DFT_SEL1_SRC0 0x00000000u
#define CYVAL__DFT_SEL1_SRC1 0x00000001u
#define CYVAL__DFT_SEL1_SRC2 0x00000002u
#define CYVAL__DFT_SEL1_SRC3 0x00000003u
#define CYVAL__DFT_SEL1_SRC4 0x00000004u
#define CYVAL__DFT_SEL1_SRC5 0x00000005u
#define CYVAL__DFT_SEL1_SRC6 0x00000006u
#define CYVAL__DFT_SEL1_SRC7 0x00000007u
#define CYVAL__DFT_SEL1_CLK0 0x00000008u
#define CYVAL__DFT_SEL1_CLK1 0x00000009u
#define CYVAL__DFT_SEL1_PWR0 0x0000000au
#define CYVAL__DFT_SEL1_PWR1 0x0000000bu
#define CYVAL__DFT_SEL1_RES0 0x0000000cu
#define CYVAL__DFT_SEL1_RES1 0x0000000du
#define CYVAL__DFT_SEL1_ADFT_COMP 0x0000000eu
#define CYVAL__DFT_SEL1_VSS 0x0000000fu
#define CYFLD__ENABLE__OFFSET 0x0000001fu
#define CYFLD__ENABLE__SIZE 0x00000001u
#define CYREG_TST_TRIM_CNTR1 0x4003001cu
#define CYFLD__COUNTER__OFFSET 0x00000000u
#define CYFLD__COUNTER__SIZE 0x00000010u
#define CYFLD__COUNTER_DONE__OFFSET 0x0000001fu
#define CYFLD__COUNTER_DONE__SIZE 0x00000001u
#define CYREG_TST_TRIM_CNTR2 0x40030020u
#define CYREG_TST_ADFT_CTRL 0x40030024u
#define CYFLD__BUF_AUTO_ZERO__OFFSET 0x00000000u
#define CYFLD__BUF_AUTO_ZERO__SIZE 0x00000001u
#define CYFLD__BUF_MODE__OFFSET 0x00000008u
#define CYFLD__BUF_MODE__SIZE 0x00000002u
#define CYFLD__BUF_COMP_OUT__OFFSET 0x00000010u
#define CYFLD__BUF_COMP_OUT__SIZE 0x00000001u
#define CYFLD__BUF_EN__OFFSET 0x0000001fu
#define CYFLD__BUF_EN__SIZE 0x00000001u
#define CYREG_CLK_SELECT 0x40030028u
#define CYFLD__HFCLK_SEL__OFFSET 0x00000000u
#define CYFLD__HFCLK_SEL__SIZE 0x00000002u
#define CYVAL__HFCLK_SEL_IMO 0x00000000u
#define CYVAL__HFCLK_SEL_EXTCLK 0x00000001u
#define CYVAL__HFCLK_SEL_ECO 0x00000002u
#define CYFLD__HFCLK_DIV__OFFSET 0x00000002u
#define CYFLD__HFCLK_DIV__SIZE 0x00000002u
#define CYVAL__HFCLK_DIV_NO_DIV 0x00000000u
#define CYVAL__HFCLK_DIV_DIV_BY_2 0x00000001u
#define CYVAL__HFCLK_DIV_DIV_BY_4 0x00000002u
#define CYVAL__HFCLK_DIV_DIV_BY_8 0x00000003u
#define CYFLD__PUMP_SEL__OFFSET 0x00000004u
#define CYFLD__PUMP_SEL__SIZE 0x00000002u
#define CYVAL__PUMP_SEL_GND 0x00000000u
#define CYVAL__PUMP_SEL_IMO 0x00000001u
#define CYVAL__PUMP_SEL_HFCLK 0x00000002u
#define CYFLD__SYSCLK_DIV__OFFSET 0x00000006u
#define CYFLD__SYSCLK_DIV__SIZE 0x00000002u
#define CYVAL__SYSCLK_DIV_NO_DIV 0x00000000u
#define CYVAL__SYSCLK_DIV_DIV_BY_2 0x00000001u
#define CYVAL__SYSCLK_DIV_DIV_BY_4 0x00000002u
#define CYVAL__SYSCLK_DIV_DIV_BY_8 0x00000003u
#define CYREG_CLK_ILO_CONFIG 0x4003002cu
#define CYREG_CLK_IMO_CONFIG 0x40030030u
#define CYREG_CLK_DFT_SELECT 0x40030034u
#define CYFLD__DFT_DIV0__OFFSET 0x00000004u
#define CYFLD__DFT_DIV0__SIZE 0x00000002u
#define CYVAL__DFT_DIV0_NO_DIV 0x00000000u
#define CYVAL__DFT_DIV0_DIV_BY_2 0x00000001u
#define CYVAL__DFT_DIV0_DIV_BY_4 0x00000002u
#define CYVAL__DFT_DIV0_DIV_BY_8 0x00000003u
#define CYFLD__DFT_EDGE0__OFFSET 0x00000006u
#define CYFLD__DFT_EDGE0__SIZE 0x00000001u
#define CYVAL__DFT_EDGE0_POSEDGE 0x00000000u
#define CYVAL__DFT_EDGE0_NEGEDGE 0x00000001u
#define CYFLD__DFT_DIV1__OFFSET 0x0000000cu
#define CYFLD__DFT_DIV1__SIZE 0x00000002u
#define CYVAL__DFT_DIV1_NO_DIV 0x00000000u
#define CYVAL__DFT_DIV1_DIV_BY_2 0x00000001u
#define CYVAL__DFT_DIV1_DIV_BY_4 0x00000002u
#define CYVAL__DFT_DIV1_DIV_BY_8 0x00000003u
#define CYFLD__DFT_EDGE1__OFFSET 0x0000000eu
#define CYFLD__DFT_EDGE1__SIZE 0x00000001u
#define CYVAL__DFT_EDGE1_POSEDGE 0x00000000u
#define CYVAL__DFT_EDGE1_NEGEDGE 0x00000001u
#define CYREG_WDT_DISABLE_KEY 0x40030038u
#define CYFLD__KEY__OFFSET 0x00000000u
#define CYFLD__KEY__SIZE 0x00000020u
#define CYREG_WDT_COUNTER 0x4003003cu
#define CYREG_WDT_MATCH 0x40030040u
#define CYFLD__MATCH__OFFSET 0x00000000u
#define CYFLD__MATCH__SIZE 0x00000010u
#define CYFLD__IGNORE_BITS__OFFSET 0x00000010u
#define CYFLD__IGNORE_BITS__SIZE 0x00000004u
#define CYREG_SRSS_INTR 0x40030044u
#define CYFLD__WDT_MATCH__OFFSET 0x00000000u
#define CYFLD__WDT_MATCH__SIZE 0x00000001u
#define CYFLD__TEMP_HIGH__OFFSET 0x00000001u
#define CYFLD__TEMP_HIGH__SIZE 0x00000001u
#define CYREG_SRSS_INTR_SET 0x40030048u
#define CYREG_SRSS_INTR_MASK 0x4003004cu
#define CYREG_RES_CAUSE 0x40030054u
#define CYFLD__RESET_WDT__OFFSET 0x00000000u
#define CYFLD__RESET_WDT__SIZE 0x00000001u
#define CYFLD__RESET_PROT_FAULT__OFFSET 0x00000003u
#define CYFLD__RESET_PROT_FAULT__SIZE 0x00000001u
#define CYFLD__RESET_SOFT__OFFSET 0x00000004u
#define CYFLD__RESET_SOFT__SIZE 0x00000001u
#define CYREG_PWR_BG_TRIM1 0x40030f00u
#define CYFLD__REF_VTRIM__OFFSET 0x00000000u
#define CYFLD__REF_VTRIM__SIZE 0x00000006u
#define CYREG_PWR_BG_TRIM2 0x40030f04u
#define CYFLD__REF_ITRIM__OFFSET 0x00000000u
#define CYFLD__REF_ITRIM__SIZE 0x00000006u
#define CYREG_CLK_IMO_SELECT 0x40030f08u
#define CYFLD__FREQ__OFFSET 0x00000000u
#define CYFLD__FREQ__SIZE 0x00000003u
#define CYVAL__FREQ_24_MHZ 0x00000000u
#define CYVAL__FREQ_28_MHZ 0x00000001u
#define CYVAL__FREQ_32_MHZ 0x00000002u
#define CYVAL__FREQ_36_MHZ 0x00000003u
#define CYVAL__FREQ_40_MHZ 0x00000004u
#define CYVAL__FREQ_44_MHZ 0x00000005u
#define CYVAL__FREQ_48_MHZ 0x00000006u
#define CYREG_CLK_IMO_TRIM1 0x40030f0cu
#define CYFLD__OFFSET__OFFSET 0x00000000u
#define CYFLD__OFFSET__SIZE 0x00000008u
#define CYREG_CLK_IMO_TRIM2 0x40030f10u
#define CYFLD__FSOFFSET__OFFSET 0x00000000u
#define CYFLD__FSOFFSET__SIZE 0x00000003u
#define CYREG_PWR_PWRSYS_TRIM1 0x40030f14u
#define CYFLD__DPSLP_REF_TRIM__OFFSET 0x00000000u
#define CYFLD__DPSLP_REF_TRIM__SIZE 0x00000004u
#define CYFLD__SPARE_TRIM__OFFSET 0x00000004u
#define CYFLD__SPARE_TRIM__SIZE 0x00000004u
#define CYREG_CLK_IMO_TRIM3 0x40030f18u
#define CYFLD__STEPSIZE__OFFSET 0x00000000u
#define CYFLD__STEPSIZE__SIZE 0x00000005u
#define CYFLD__TCTRIM__OFFSET 0x00000005u
#define CYFLD__TCTRIM__SIZE 0x00000002u
#define CYDEV_GPIO_BASE 0x40040000u
#define CYDEV_GPIO_SIZE 0x00004000u
#define CYDEV_GPIO_PRT0_BASE 0x40040000u
#define CYDEV_GPIO_PRT0_SIZE 0x00000100u
#define CYREG_GPIO_PRT0_DR 0x40040000u
#define CYFLD_GPIO_PRT_DATA0__OFFSET 0x00000000u
#define CYFLD_GPIO_PRT_DATA0__SIZE 0x00000001u
#define CYFLD_GPIO_PRT_DATA1__OFFSET 0x00000001u
#define CYFLD_GPIO_PRT_DATA1__SIZE 0x00000001u
#define CYREG_GPIO_PRT0_PS 0x40040004u
#define CYFLD_GPIO_PRT_FLT_DATA__OFFSET 0x00000008u
#define CYFLD_GPIO_PRT_FLT_DATA__SIZE 0x00000001u
#define CYREG_GPIO_PRT0_PC 0x40040008u
#define CYFLD_GPIO_PRT_DM0__OFFSET 0x00000000u
#define CYFLD_GPIO_PRT_DM0__SIZE 0x00000003u
#define CYVAL_GPIO_PRT_DM0_OFF 0x00000000u
#define CYVAL_GPIO_PRT_DM0_INPUT 0x00000001u
#define CYVAL_GPIO_PRT_DM0_0_PU 0x00000002u
#define CYVAL_GPIO_PRT_DM0_PD_1 0x00000003u
#define CYVAL_GPIO_PRT_DM0_0_Z 0x00000004u
#define CYVAL_GPIO_PRT_DM0_Z_1 0x00000005u
#define CYVAL_GPIO_PRT_DM0_0_1 0x00000006u
#define CYVAL_GPIO_PRT_DM0_PD_PU 0x00000007u
#define CYFLD_GPIO_PRT_DM1__OFFSET 0x00000003u
#define CYFLD_GPIO_PRT_DM1__SIZE 0x00000003u
#define CYFLD_GPIO_PRT_PORT_VTRIP_SEL__OFFSET 0x00000018u
#define CYFLD_GPIO_PRT_PORT_VTRIP_SEL__SIZE 0x00000001u
#define CYFLD_GPIO_PRT_PORT_SLOW__OFFSET 0x00000019u
#define CYFLD_GPIO_PRT_PORT_SLOW__SIZE 0x00000001u
#define CYFLD_GPIO_PRT_PORT_HYST_TRIM__OFFSET 0x0000001bu
#define CYFLD_GPIO_PRT_PORT_HYST_TRIM__SIZE 0x00000001u
#define CYFLD_GPIO_PRT_PORT_SLEW_CTL__OFFSET 0x0000001cu
#define CYFLD_GPIO_PRT_PORT_SLEW_CTL__SIZE 0x00000002u
#define CYVAL_GPIO_PRT_PORT_SLEW_CTL_PORT_SLEW_CTL_0 0x00000000u
#define CYVAL_GPIO_PRT_PORT_SLEW_CTL_PORT_SLEW_CTL_1 0x00000001u
#define CYVAL_GPIO_PRT_PORT_SLEW_CTL_PORT_SLEW_CTL_2 0x00000002u
#define CYVAL_GPIO_PRT_PORT_SLEW_CTL_PORT_SLEW_CTL_3 0x00000003u
#define CYFLD_GPIO_PRT_PORT_IB_MODE_SEL__OFFSET 0x0000001eu
#define CYFLD_GPIO_PRT_PORT_IB_MODE_SEL__SIZE 0x00000002u
#define CYREG_GPIO_PRT0_INTR_CFG 0x4004000cu
#define CYFLD_GPIO_PRT_EDGE0_SEL__OFFSET 0x00000000u
#define CYFLD_GPIO_PRT_EDGE0_SEL__SIZE 0x00000002u
#define CYVAL_GPIO_PRT_EDGE0_SEL_DISABLE 0x00000000u
#define CYVAL_GPIO_PRT_EDGE0_SEL_RISING 0x00000001u
#define CYVAL_GPIO_PRT_EDGE0_SEL_FALLING 0x00000002u
#define CYVAL_GPIO_PRT_EDGE0_SEL_BOTH 0x00000003u
#define CYFLD_GPIO_PRT_EDGE1_SEL__OFFSET 0x00000002u
#define CYFLD_GPIO_PRT_EDGE1_SEL__SIZE 0x00000002u
#define CYFLD_GPIO_PRT_FLT_EDGE_SEL__OFFSET 0x00000010u
#define CYFLD_GPIO_PRT_FLT_EDGE_SEL__SIZE 0x00000002u
#define CYVAL_GPIO_PRT_FLT_EDGE_SEL_DISABLE 0x00000000u
#define CYVAL_GPIO_PRT_FLT_EDGE_SEL_RISING 0x00000001u
#define CYVAL_GPIO_PRT_FLT_EDGE_SEL_FALLING 0x00000002u
#define CYVAL_GPIO_PRT_FLT_EDGE_SEL_BOTH 0x00000003u
#define CYFLD_GPIO_PRT_FLT_SEL__OFFSET 0x00000012u
#define CYFLD_GPIO_PRT_FLT_SEL__SIZE 0x00000003u
#define CYREG_GPIO_PRT0_INTR 0x40040010u
#define CYFLD_GPIO_PRT_PS_DATA0__OFFSET 0x00000010u
#define CYFLD_GPIO_PRT_PS_DATA0__SIZE 0x00000001u
#define CYFLD_GPIO_PRT_PS_DATA1__OFFSET 0x00000011u
#define CYFLD_GPIO_PRT_PS_DATA1__SIZE 0x00000001u
#define CYFLD_GPIO_PRT_PS_FLT_DATA__OFFSET 0x00000018u
#define CYFLD_GPIO_PRT_PS_FLT_DATA__SIZE 0x00000001u
#define CYREG_GPIO_PRT0_PC2 0x40040018u
#define CYFLD_GPIO_PRT_INP_DIS0__OFFSET 0x00000000u
#define CYFLD_GPIO_PRT_INP_DIS0__SIZE 0x00000001u
#define CYFLD_GPIO_PRT_INP_DIS1__OFFSET 0x00000001u
#define CYFLD_GPIO_PRT_INP_DIS1__SIZE 0x00000001u
#define CYREG_GPIO_PRT0_DR_SET 0x40040040u
#define CYFLD_GPIO_PRT_DATA__OFFSET 0x00000000u
#define CYFLD_GPIO_PRT_DATA__SIZE 0x00000008u
#define CYREG_GPIO_PRT0_DR_CLR 0x40040044u
#define CYREG_GPIO_PRT0_DR_INV 0x40040048u
#define CYDEV_GPIO_PRT1_BASE 0x40040100u
#define CYDEV_GPIO_PRT1_SIZE 0x00000100u
#define CYREG_GPIO_PRT1_DR 0x40040100u
#define CYFLD_GPIO_PRT_DATA2__OFFSET 0x00000002u
#define CYFLD_GPIO_PRT_DATA2__SIZE 0x00000001u
#define CYFLD_GPIO_PRT_DATA3__OFFSET 0x00000003u
#define CYFLD_GPIO_PRT_DATA3__SIZE 0x00000001u
#define CYFLD_GPIO_PRT_DATA4__OFFSET 0x00000004u
#define CYFLD_GPIO_PRT_DATA4__SIZE 0x00000001u
#define CYFLD_GPIO_PRT_DATA5__OFFSET 0x00000005u
#define CYFLD_GPIO_PRT_DATA5__SIZE 0x00000001u
#define CYFLD_GPIO_PRT_DATA6__OFFSET 0x00000006u
#define CYFLD_GPIO_PRT_DATA6__SIZE 0x00000001u
#define CYFLD_GPIO_PRT_DATA7__OFFSET 0x00000007u
#define CYFLD_GPIO_PRT_DATA7__SIZE 0x00000001u
#define CYREG_GPIO_PRT1_PS 0x40040104u
#define CYREG_GPIO_PRT1_PC 0x40040108u
#define CYFLD_GPIO_PRT_DM2__OFFSET 0x00000006u
#define CYFLD_GPIO_PRT_DM2__SIZE 0x00000003u
#define CYFLD_GPIO_PRT_DM3__OFFSET 0x00000009u
#define CYFLD_GPIO_PRT_DM3__SIZE 0x00000003u
#define CYFLD_GPIO_PRT_DM4__OFFSET 0x0000000cu
#define CYFLD_GPIO_PRT_DM4__SIZE 0x00000003u
#define CYFLD_GPIO_PRT_DM5__OFFSET 0x0000000fu
#define CYFLD_GPIO_PRT_DM5__SIZE 0x00000003u
#define CYFLD_GPIO_PRT_DM6__OFFSET 0x00000012u
#define CYFLD_GPIO_PRT_DM6__SIZE 0x00000003u
#define CYFLD_GPIO_PRT_DM7__OFFSET 0x00000015u
#define CYFLD_GPIO_PRT_DM7__SIZE 0x00000003u
#define CYREG_GPIO_PRT1_INTR_CFG 0x4004010cu
#define CYFLD_GPIO_PRT_EDGE2_SEL__OFFSET 0x00000004u
#define CYFLD_GPIO_PRT_EDGE2_SEL__SIZE 0x00000002u
#define CYFLD_GPIO_PRT_EDGE3_SEL__OFFSET 0x00000006u
#define CYFLD_GPIO_PRT_EDGE3_SEL__SIZE 0x00000002u
#define CYFLD_GPIO_PRT_EDGE4_SEL__OFFSET 0x00000008u
#define CYFLD_GPIO_PRT_EDGE4_SEL__SIZE 0x00000002u
#define CYFLD_GPIO_PRT_EDGE5_SEL__OFFSET 0x0000000au
#define CYFLD_GPIO_PRT_EDGE5_SEL__SIZE 0x00000002u
#define CYFLD_GPIO_PRT_EDGE6_SEL__OFFSET 0x0000000cu
#define CYFLD_GPIO_PRT_EDGE6_SEL__SIZE 0x00000002u
#define CYFLD_GPIO_PRT_EDGE7_SEL__OFFSET 0x0000000eu
#define CYFLD_GPIO_PRT_EDGE7_SEL__SIZE 0x00000002u
#define CYREG_GPIO_PRT1_INTR 0x40040110u
#define CYFLD_GPIO_PRT_PS_DATA2__OFFSET 0x00000012u
#define CYFLD_GPIO_PRT_PS_DATA2__SIZE 0x00000001u
#define CYFLD_GPIO_PRT_PS_DATA3__OFFSET 0x00000013u
#define CYFLD_GPIO_PRT_PS_DATA3__SIZE 0x00000001u
#define CYFLD_GPIO_PRT_PS_DATA4__OFFSET 0x00000014u
#define CYFLD_GPIO_PRT_PS_DATA4__SIZE 0x00000001u
#define CYFLD_GPIO_PRT_PS_DATA5__OFFSET 0x00000015u
#define CYFLD_GPIO_PRT_PS_DATA5__SIZE 0x00000001u
#define CYFLD_GPIO_PRT_PS_DATA6__OFFSET 0x00000016u
#define CYFLD_GPIO_PRT_PS_DATA6__SIZE 0x00000001u
#define CYFLD_GPIO_PRT_PS_DATA7__OFFSET 0x00000017u
#define CYFLD_GPIO_PRT_PS_DATA7__SIZE 0x00000001u
#define CYREG_GPIO_PRT1_PC2 0x40040118u
#define CYFLD_GPIO_PRT_INP_DIS2__OFFSET 0x00000002u
#define CYFLD_GPIO_PRT_INP_DIS2__SIZE 0x00000001u
#define CYFLD_GPIO_PRT_INP_DIS3__OFFSET 0x00000003u
#define CYFLD_GPIO_PRT_INP_DIS3__SIZE 0x00000001u
#define CYFLD_GPIO_PRT_INP_DIS4__OFFSET 0x00000004u
#define CYFLD_GPIO_PRT_INP_DIS4__SIZE 0x00000001u
#define CYFLD_GPIO_PRT_INP_DIS5__OFFSET 0x00000005u
#define CYFLD_GPIO_PRT_INP_DIS5__SIZE 0x00000001u
#define CYFLD_GPIO_PRT_INP_DIS6__OFFSET 0x00000006u
#define CYFLD_GPIO_PRT_INP_DIS6__SIZE 0x00000001u
#define CYFLD_GPIO_PRT_INP_DIS7__OFFSET 0x00000007u
#define CYFLD_GPIO_PRT_INP_DIS7__SIZE 0x00000001u
#define CYREG_GPIO_PRT1_DR_SET 0x40040140u
#define CYREG_GPIO_PRT1_DR_CLR 0x40040144u
#define CYREG_GPIO_PRT1_DR_INV 0x40040148u
#define CYDEV_GPIO_PRT2_BASE 0x40040200u
#define CYDEV_GPIO_PRT2_SIZE 0x00000100u
#define CYREG_GPIO_PRT2_DR 0x40040200u
#define CYREG_GPIO_PRT2_PS 0x40040204u
#define CYREG_GPIO_PRT2_PC 0x40040208u
#define CYREG_GPIO_PRT2_INTR_CFG 0x4004020cu
#define CYREG_GPIO_PRT2_INTR 0x40040210u
#define CYREG_GPIO_PRT2_PC2 0x40040218u
#define CYREG_GPIO_PRT2_DR_SET 0x40040240u
#define CYREG_GPIO_PRT2_DR_CLR 0x40040244u
#define CYREG_GPIO_PRT2_DR_INV 0x40040248u
#define CYDEV_GPIO_PRT3_BASE 0x40040300u
#define CYDEV_GPIO_PRT3_SIZE 0x00000100u
#define CYREG_GPIO_PRT3_DR 0x40040300u
#define CYREG_GPIO_PRT3_PS 0x40040304u
#define CYREG_GPIO_PRT3_PC 0x40040308u
#define CYREG_GPIO_PRT3_INTR_CFG 0x4004030cu
#define CYREG_GPIO_PRT3_INTR 0x40040310u
#define CYREG_GPIO_PRT3_PC2 0x40040318u
#define CYREG_GPIO_PRT3_DR_SET 0x40040340u
#define CYREG_GPIO_PRT3_DR_CLR 0x40040344u
#define CYREG_GPIO_PRT3_DR_INV 0x40040348u
#define CYDEV_GPIO_PRT4_BASE 0x40040400u
#define CYDEV_GPIO_PRT4_SIZE 0x00000100u
#define CYREG_GPIO_PRT4_DR 0x40040400u
#define CYREG_GPIO_PRT4_PS 0x40040404u
#define CYREG_GPIO_PRT4_INTR_CFG 0x4004040cu
#define CYREG_GPIO_PRT4_INTR 0x40040410u
#define CYREG_GPIO_PRT4_DR_SET 0x40040440u
#define CYREG_GPIO_PRT4_DR_CLR 0x40040444u
#define CYREG_GPIO_PRT4_DR_INV 0x40040448u
#define CYREG_GPIO_INTR_CAUSE 0x40041000u
#define CYFLD_GPIO_PORT_INT__OFFSET 0x00000000u
#define CYFLD_GPIO_PORT_INT__SIZE 0x00000005u
#define CYDEV_SCB0_BASE 0x40050000u
#define CYDEV_SCB0_SIZE 0x00010000u
#define CYREG_SCB0_CTRL 0x40050000u
#define CYFLD_SCB_OVS__OFFSET 0x00000000u
#define CYFLD_SCB_OVS__SIZE 0x00000004u
#define CYFLD_SCB_EC_AM_MODE__OFFSET 0x00000008u
#define CYFLD_SCB_EC_AM_MODE__SIZE 0x00000001u
#define CYFLD_SCB_EC_OP_MODE__OFFSET 0x00000009u
#define CYFLD_SCB_EC_OP_MODE__SIZE 0x00000001u
#define CYFLD_SCB_EZ_MODE__OFFSET 0x0000000au
#define CYFLD_SCB_EZ_MODE__SIZE 0x00000001u
#define CYFLD_SCB_BYTE_MODE__OFFSET 0x0000000bu
#define CYFLD_SCB_BYTE_MODE__SIZE 0x00000001u
#define CYFLD_SCB_CMD_RESP_MODE__OFFSET 0x0000000cu
#define CYFLD_SCB_CMD_RESP_MODE__SIZE 0x00000001u
#define CYFLD_SCB_ADDR_ACCEPT__OFFSET 0x00000010u
#define CYFLD_SCB_ADDR_ACCEPT__SIZE 0x00000001u
#define CYFLD_SCB_BLOCK__OFFSET 0x00000011u
#define CYFLD_SCB_BLOCK__SIZE 0x00000001u
#define CYFLD_SCB_MODE__OFFSET 0x00000018u
#define CYFLD_SCB_MODE__SIZE 0x00000002u
#define CYVAL_SCB_MODE_I2C 0x00000000u
#define CYVAL_SCB_MODE_SPI 0x00000001u
#define CYVAL_SCB_MODE_UART 0x00000002u
#define CYFLD_SCB_ENABLED__OFFSET 0x0000001fu
#define CYFLD_SCB_ENABLED__SIZE 0x00000001u
#define CYREG_SCB0_STATUS 0x40050004u
#define CYFLD_SCB_EC_BUSY__OFFSET 0x00000000u
#define CYFLD_SCB_EC_BUSY__SIZE 0x00000001u
#define CYREG_SCB0_CMD_RESP_CTRL 0x40050008u
#define CYFLD_SCB_BASE_RD_ADDR__OFFSET 0x00000000u
#define CYFLD_SCB_BASE_RD_ADDR__SIZE 0x00000008u
#define CYFLD_SCB_BASE_WR_ADDR__OFFSET 0x00000010u
#define CYFLD_SCB_BASE_WR_ADDR__SIZE 0x00000008u
#define CYREG_SCB0_CMD_RESP_STATUS 0x4005000cu
#define CYFLD_SCB_CURR_RD_ADDR__OFFSET 0x00000000u
#define CYFLD_SCB_CURR_RD_ADDR__SIZE 0x00000008u
#define CYFLD_SCB_CURR_WR_ADDR__OFFSET 0x00000010u
#define CYFLD_SCB_CURR_WR_ADDR__SIZE 0x00000008u
#define CYFLD_SCB_CMD_RESP_EC_BUS_BUSY__OFFSET 0x0000001eu
#define CYFLD_SCB_CMD_RESP_EC_BUS_BUSY__SIZE 0x00000001u
#define CYFLD_SCB_CMD_RESP_EC_BUSY__OFFSET 0x0000001fu
#define CYFLD_SCB_CMD_RESP_EC_BUSY__SIZE 0x00000001u
#define CYREG_SCB0_SPI_CTRL 0x40050020u
#define CYFLD_SCB_CONTINUOUS__OFFSET 0x00000000u
#define CYFLD_SCB_CONTINUOUS__SIZE 0x00000001u
#define CYFLD_SCB_SELECT_PRECEDE__OFFSET 0x00000001u
#define CYFLD_SCB_SELECT_PRECEDE__SIZE 0x00000001u
#define CYFLD_SCB_CPHA__OFFSET 0x00000002u
#define CYFLD_SCB_CPHA__SIZE 0x00000001u
#define CYFLD_SCB_CPOL__OFFSET 0x00000003u
#define CYFLD_SCB_CPOL__SIZE 0x00000001u
#define CYFLD_SCB_LATE_MISO_SAMPLE__OFFSET 0x00000004u
#define CYFLD_SCB_LATE_MISO_SAMPLE__SIZE 0x00000001u
#define CYFLD_SCB_SCLK_CONTINUOUS__OFFSET 0x00000005u
#define CYFLD_SCB_SCLK_CONTINUOUS__SIZE 0x00000001u
#define CYFLD_SCB_SSEL_POLARITY0__OFFSET 0x00000008u
#define CYFLD_SCB_SSEL_POLARITY0__SIZE 0x00000001u
#define CYFLD_SCB_SSEL_POLARITY1__OFFSET 0x00000009u
#define CYFLD_SCB_SSEL_POLARITY1__SIZE 0x00000001u
#define CYFLD_SCB_SSEL_POLARITY2__OFFSET 0x0000000au
#define CYFLD_SCB_SSEL_POLARITY2__SIZE 0x00000001u
#define CYFLD_SCB_SSEL_POLARITY3__OFFSET 0x0000000bu
#define CYFLD_SCB_SSEL_POLARITY3__SIZE 0x00000001u
#define CYFLD_SCB_LOOPBACK__OFFSET 0x00000010u
#define CYFLD_SCB_LOOPBACK__SIZE 0x00000001u
#define CYFLD_SCB_SLAVE_SELECT__OFFSET 0x0000001au
#define CYFLD_SCB_SLAVE_SELECT__SIZE 0x00000002u
#define CYFLD_SCB_MASTER_MODE__OFFSET 0x0000001fu
#define CYFLD_SCB_MASTER_MODE__SIZE 0x00000001u
#define CYREG_SCB0_SPI_STATUS 0x40050024u
#define CYFLD_SCB_BUS_BUSY__OFFSET 0x00000000u
#define CYFLD_SCB_BUS_BUSY__SIZE 0x00000001u
#define CYFLD_SCB_SPI_EC_BUSY__OFFSET 0x00000001u
#define CYFLD_SCB_SPI_EC_BUSY__SIZE 0x00000001u
#define CYFLD_SCB_CURR_EZ_ADDR__OFFSET 0x00000008u
#define CYFLD_SCB_CURR_EZ_ADDR__SIZE 0x00000008u
#define CYFLD_SCB_BASE_EZ_ADDR__OFFSET 0x00000010u
#define CYFLD_SCB_BASE_EZ_ADDR__SIZE 0x00000008u
#define CYREG_SCB0_UART_CTRL 0x40050040u
#define CYREG_SCB0_UART_TX_CTRL 0x40050044u
#define CYFLD_SCB_STOP_BITS__OFFSET 0x00000000u
#define CYFLD_SCB_STOP_BITS__SIZE 0x00000003u
#define CYFLD_SCB_PARITY__OFFSET 0x00000004u
#define CYFLD_SCB_PARITY__SIZE 0x00000001u
#define CYFLD_SCB_PARITY_ENABLED__OFFSET 0x00000005u
#define CYFLD_SCB_PARITY_ENABLED__SIZE 0x00000001u
#define CYFLD_SCB_RETRY_ON_NACK__OFFSET 0x00000008u
#define CYFLD_SCB_RETRY_ON_NACK__SIZE 0x00000001u
#define CYREG_SCB0_UART_RX_CTRL 0x40050048u
#define CYFLD_SCB_POLARITY__OFFSET 0x00000006u
#define CYFLD_SCB_POLARITY__SIZE 0x00000001u
#define CYFLD_SCB_DROP_ON_PARITY_ERROR__OFFSET 0x00000008u
#define CYFLD_SCB_DROP_ON_PARITY_ERROR__SIZE 0x00000001u
#define CYFLD_SCB_DROP_ON_FRAME_ERROR__OFFSET 0x00000009u
#define CYFLD_SCB_DROP_ON_FRAME_ERROR__SIZE 0x00000001u
#define CYFLD_SCB_MP_MODE__OFFSET 0x0000000au
#define CYFLD_SCB_MP_MODE__SIZE 0x00000001u
#define CYFLD_SCB_LIN_MODE__OFFSET 0x0000000cu
#define CYFLD_SCB_LIN_MODE__SIZE 0x00000001u
#define CYFLD_SCB_SKIP_START__OFFSET 0x0000000du
#define CYFLD_SCB_SKIP_START__SIZE 0x00000001u
#define CYFLD_SCB_BREAK_WIDTH__OFFSET 0x00000010u
#define CYFLD_SCB_BREAK_WIDTH__SIZE 0x00000004u
#define CYREG_SCB0_UART_RX_STATUS 0x4005004cu
#define CYFLD_SCB_BR_COUNTER__OFFSET 0x00000000u
#define CYFLD_SCB_BR_COUNTER__SIZE 0x0000000cu
#define CYREG_SCB0_UART_FLOW_CTRL 0x40050050u
#define CYFLD_SCB_TRIGGER_LEVEL__OFFSET 0x00000000u
#define CYFLD_SCB_TRIGGER_LEVEL__SIZE 0x00000007u
#define CYFLD_SCB_RTS_POLARITY__OFFSET 0x00000010u
#define CYFLD_SCB_RTS_POLARITY__SIZE 0x00000001u
#define CYFLD_SCB_CTS_POLARITY__OFFSET 0x00000018u
#define CYFLD_SCB_CTS_POLARITY__SIZE 0x00000001u
#define CYFLD_SCB_CTS_ENABLED__OFFSET 0x00000019u
#define CYFLD_SCB_CTS_ENABLED__SIZE 0x00000001u
#define CYREG_SCB0_I2C_CTRL 0x40050060u
#define CYFLD_SCB_HIGH_PHASE_OVS__OFFSET 0x00000000u
#define CYFLD_SCB_HIGH_PHASE_OVS__SIZE 0x00000004u
#define CYFLD_SCB_LOW_PHASE_OVS__OFFSET 0x00000004u
#define CYFLD_SCB_LOW_PHASE_OVS__SIZE 0x00000004u
#define CYFLD_SCB_M_READY_DATA_ACK__OFFSET 0x00000008u
#define CYFLD_SCB_M_READY_DATA_ACK__SIZE 0x00000001u
#define CYFLD_SCB_M_NOT_READY_DATA_NACK__OFFSET 0x00000009u
#define CYFLD_SCB_M_NOT_READY_DATA_NACK__SIZE 0x00000001u
#define CYFLD_SCB_S_GENERAL_IGNORE__OFFSET 0x0000000bu
#define CYFLD_SCB_S_GENERAL_IGNORE__SIZE 0x00000001u
#define CYFLD_SCB_S_READY_ADDR_ACK__OFFSET 0x0000000cu
#define CYFLD_SCB_S_READY_ADDR_ACK__SIZE 0x00000001u
#define CYFLD_SCB_S_READY_DATA_ACK__OFFSET 0x0000000du
#define CYFLD_SCB_S_READY_DATA_ACK__SIZE 0x00000001u
#define CYFLD_SCB_S_NOT_READY_ADDR_NACK__OFFSET 0x0000000eu
#define CYFLD_SCB_S_NOT_READY_ADDR_NACK__SIZE 0x00000001u
#define CYFLD_SCB_S_NOT_READY_DATA_NACK__OFFSET 0x0000000fu
#define CYFLD_SCB_S_NOT_READY_DATA_NACK__SIZE 0x00000001u
#define CYFLD_SCB_SLAVE_MODE__OFFSET 0x0000001eu
#define CYFLD_SCB_SLAVE_MODE__SIZE 0x00000001u
#define CYREG_SCB0_I2C_STATUS 0x40050064u
#define CYFLD_SCB_I2C_EC_BUSY__OFFSET 0x00000001u
#define CYFLD_SCB_I2C_EC_BUSY__SIZE 0x00000001u
#define CYFLD_SCB_S_READ__OFFSET 0x00000004u
#define CYFLD_SCB_S_READ__SIZE 0x00000001u
#define CYFLD_SCB_M_READ__OFFSET 0x00000005u
#define CYFLD_SCB_M_READ__SIZE 0x00000001u
#define CYREG_SCB0_I2C_M_CMD 0x40050068u
#define CYFLD_SCB_M_START__OFFSET 0x00000000u
#define CYFLD_SCB_M_START__SIZE 0x00000001u
#define CYFLD_SCB_M_START_ON_IDLE__OFFSET 0x00000001u
#define CYFLD_SCB_M_START_ON_IDLE__SIZE 0x00000001u
#define CYFLD_SCB_M_ACK__OFFSET 0x00000002u
#define CYFLD_SCB_M_ACK__SIZE 0x00000001u
#define CYFLD_SCB_M_NACK__OFFSET 0x00000003u
#define CYFLD_SCB_M_NACK__SIZE 0x00000001u
#define CYFLD_SCB_M_STOP__OFFSET 0x00000004u
#define CYFLD_SCB_M_STOP__SIZE 0x00000001u
#define CYREG_SCB0_I2C_S_CMD 0x4005006cu
#define CYFLD_SCB_S_ACK__OFFSET 0x00000000u
#define CYFLD_SCB_S_ACK__SIZE 0x00000001u
#define CYFLD_SCB_S_NACK__OFFSET 0x00000001u
#define CYFLD_SCB_S_NACK__SIZE 0x00000001u
#define CYREG_SCB0_I2C_CFG 0x40050070u
#define CYFLD_SCB_SDA_IN_FILT_TRIM__OFFSET 0x00000000u
#define CYFLD_SCB_SDA_IN_FILT_TRIM__SIZE 0x00000002u
#define CYFLD_SCB_SDA_IN_FILT_SEL__OFFSET 0x00000004u
#define CYFLD_SCB_SDA_IN_FILT_SEL__SIZE 0x00000001u
#define CYFLD_SCB_SCL_IN_FILT_TRIM__OFFSET 0x00000008u
#define CYFLD_SCB_SCL_IN_FILT_TRIM__SIZE 0x00000002u
#define CYFLD_SCB_SCL_IN_FILT_SEL__OFFSET 0x0000000cu
#define CYFLD_SCB_SCL_IN_FILT_SEL__SIZE 0x00000001u
#define CYFLD_SCB_SDA_OUT_FILT0_TRIM__OFFSET 0x00000010u
#define CYFLD_SCB_SDA_OUT_FILT0_TRIM__SIZE 0x00000002u
#define CYFLD_SCB_SDA_OUT_FILT1_TRIM__OFFSET 0x00000012u
#define CYFLD_SCB_SDA_OUT_FILT1_TRIM__SIZE 0x00000002u
#define CYFLD_SCB_SDA_OUT_FILT2_TRIM__OFFSET 0x00000014u
#define CYFLD_SCB_SDA_OUT_FILT2_TRIM__SIZE 0x00000002u
#define CYFLD_SCB_SDA_OUT_FILT_SEL__OFFSET 0x0000001cu
#define CYFLD_SCB_SDA_OUT_FILT_SEL__SIZE 0x00000002u
#define CYREG_SCB0_TX_CTRL 0x40050200u
#define CYFLD_SCB_DATA_WIDTH__OFFSET 0x00000000u
#define CYFLD_SCB_DATA_WIDTH__SIZE 0x00000004u
#define CYFLD_SCB_MSB_FIRST__OFFSET 0x00000008u
#define CYFLD_SCB_MSB_FIRST__SIZE 0x00000001u
#define CYREG_SCB0_TX_FIFO_CTRL 0x40050204u
#define CYFLD_SCB_CLEAR__OFFSET 0x00000010u
#define CYFLD_SCB_CLEAR__SIZE 0x00000001u
#define CYFLD_SCB_FREEZE__OFFSET 0x00000011u
#define CYFLD_SCB_FREEZE__SIZE 0x00000001u
#define CYREG_SCB0_TX_FIFO_STATUS 0x40050208u
#define CYFLD_SCB_USED__OFFSET 0x00000000u
#define CYFLD_SCB_USED__SIZE 0x00000008u
#define CYFLD_SCB_SR_VALID__OFFSET 0x0000000fu
#define CYFLD_SCB_SR_VALID__SIZE 0x00000001u
#define CYFLD_SCB_RD_PTR__OFFSET 0x00000010u
#define CYFLD_SCB_RD_PTR__SIZE 0x00000007u
#define CYFLD_SCB_WR_PTR__OFFSET 0x00000018u
#define CYFLD_SCB_WR_PTR__SIZE 0x00000007u
#define CYREG_SCB0_TX_FIFO_WR 0x40050240u
#define CYFLD_SCB_DATA__OFFSET 0x00000000u
#define CYFLD_SCB_DATA__SIZE 0x00000010u
#define CYREG_SCB0_RX_CTRL 0x40050300u
#define CYFLD_SCB_MEDIAN__OFFSET 0x00000009u
#define CYFLD_SCB_MEDIAN__SIZE 0x00000001u
#define CYREG_SCB0_RX_FIFO_CTRL 0x40050304u
#define CYREG_SCB0_RX_FIFO_STATUS 0x40050308u
#define CYREG_SCB0_RX_MATCH 0x40050310u
#define CYFLD_SCB_ADDR__OFFSET 0x00000000u
#define CYFLD_SCB_ADDR__SIZE 0x00000008u
#define CYFLD_SCB_MASK__OFFSET 0x00000010u
#define CYFLD_SCB_MASK__SIZE 0x00000008u
#define CYREG_SCB0_RX_FIFO_RD 0x40050340u
#define CYREG_SCB0_RX_FIFO_RD_SILENT 0x40050344u
#define CYREG_SCB0_EZ_DATA0 0x40050400u
#define CYFLD_SCB_EZ_DATA__OFFSET 0x00000000u
#define CYFLD_SCB_EZ_DATA__SIZE 0x00000008u
#define CYREG_SCB0_EZ_DATA1 0x40050404u
#define CYREG_SCB0_EZ_DATA2 0x40050408u
#define CYREG_SCB0_EZ_DATA3 0x4005040cu
#define CYREG_SCB0_EZ_DATA4 0x40050410u
#define CYREG_SCB0_EZ_DATA5 0x40050414u
#define CYREG_SCB0_EZ_DATA6 0x40050418u
#define CYREG_SCB0_EZ_DATA7 0x4005041cu
#define CYREG_SCB0_EZ_DATA8 0x40050420u
#define CYREG_SCB0_EZ_DATA9 0x40050424u
#define CYREG_SCB0_EZ_DATA10 0x40050428u
#define CYREG_SCB0_EZ_DATA11 0x4005042cu
#define CYREG_SCB0_EZ_DATA12 0x40050430u
#define CYREG_SCB0_EZ_DATA13 0x40050434u
#define CYREG_SCB0_EZ_DATA14 0x40050438u
#define CYREG_SCB0_EZ_DATA15 0x4005043cu
#define CYREG_SCB0_EZ_DATA16 0x40050440u
#define CYREG_SCB0_EZ_DATA17 0x40050444u
#define CYREG_SCB0_EZ_DATA18 0x40050448u
#define CYREG_SCB0_EZ_DATA19 0x4005044cu
#define CYREG_SCB0_EZ_DATA20 0x40050450u
#define CYREG_SCB0_EZ_DATA21 0x40050454u
#define CYREG_SCB0_EZ_DATA22 0x40050458u
#define CYREG_SCB0_EZ_DATA23 0x4005045cu
#define CYREG_SCB0_EZ_DATA24 0x40050460u
#define CYREG_SCB0_EZ_DATA25 0x40050464u
#define CYREG_SCB0_EZ_DATA26 0x40050468u
#define CYREG_SCB0_EZ_DATA27 0x4005046cu
#define CYREG_SCB0_EZ_DATA28 0x40050470u
#define CYREG_SCB0_EZ_DATA29 0x40050474u
#define CYREG_SCB0_EZ_DATA30 0x40050478u
#define CYREG_SCB0_EZ_DATA31 0x4005047cu
#define CYREG_SCB0_EZ_DATA32 0x40050480u
#define CYREG_SCB0_EZ_DATA33 0x40050484u
#define CYREG_SCB0_EZ_DATA34 0x40050488u
#define CYREG_SCB0_EZ_DATA35 0x4005048cu
#define CYREG_SCB0_EZ_DATA36 0x40050490u
#define CYREG_SCB0_EZ_DATA37 0x40050494u
#define CYREG_SCB0_EZ_DATA38 0x40050498u
#define CYREG_SCB0_EZ_DATA39 0x4005049cu
#define CYREG_SCB0_EZ_DATA40 0x400504a0u
#define CYREG_SCB0_EZ_DATA41 0x400504a4u
#define CYREG_SCB0_EZ_DATA42 0x400504a8u
#define CYREG_SCB0_EZ_DATA43 0x400504acu
#define CYREG_SCB0_EZ_DATA44 0x400504b0u
#define CYREG_SCB0_EZ_DATA45 0x400504b4u
#define CYREG_SCB0_EZ_DATA46 0x400504b8u
#define CYREG_SCB0_EZ_DATA47 0x400504bcu
#define CYREG_SCB0_EZ_DATA48 0x400504c0u
#define CYREG_SCB0_EZ_DATA49 0x400504c4u
#define CYREG_SCB0_EZ_DATA50 0x400504c8u
#define CYREG_SCB0_EZ_DATA51 0x400504ccu
#define CYREG_SCB0_EZ_DATA52 0x400504d0u
#define CYREG_SCB0_EZ_DATA53 0x400504d4u
#define CYREG_SCB0_EZ_DATA54 0x400504d8u
#define CYREG_SCB0_EZ_DATA55 0x400504dcu
#define CYREG_SCB0_EZ_DATA56 0x400504e0u
#define CYREG_SCB0_EZ_DATA57 0x400504e4u
#define CYREG_SCB0_EZ_DATA58 0x400504e8u
#define CYREG_SCB0_EZ_DATA59 0x400504ecu
#define CYREG_SCB0_EZ_DATA60 0x400504f0u
#define CYREG_SCB0_EZ_DATA61 0x400504f4u
#define CYREG_SCB0_EZ_DATA62 0x400504f8u
#define CYREG_SCB0_EZ_DATA63 0x400504fcu
#define CYREG_SCB0_EZ_DATA64 0x40050500u
#define CYREG_SCB0_EZ_DATA65 0x40050504u
#define CYREG_SCB0_EZ_DATA66 0x40050508u
#define CYREG_SCB0_EZ_DATA67 0x4005050cu
#define CYREG_SCB0_EZ_DATA68 0x40050510u
#define CYREG_SCB0_EZ_DATA69 0x40050514u
#define CYREG_SCB0_EZ_DATA70 0x40050518u
#define CYREG_SCB0_EZ_DATA71 0x4005051cu
#define CYREG_SCB0_EZ_DATA72 0x40050520u
#define CYREG_SCB0_EZ_DATA73 0x40050524u
#define CYREG_SCB0_EZ_DATA74 0x40050528u
#define CYREG_SCB0_EZ_DATA75 0x4005052cu
#define CYREG_SCB0_EZ_DATA76 0x40050530u
#define CYREG_SCB0_EZ_DATA77 0x40050534u
#define CYREG_SCB0_EZ_DATA78 0x40050538u
#define CYREG_SCB0_EZ_DATA79 0x4005053cu
#define CYREG_SCB0_EZ_DATA80 0x40050540u
#define CYREG_SCB0_EZ_DATA81 0x40050544u
#define CYREG_SCB0_EZ_DATA82 0x40050548u
#define CYREG_SCB0_EZ_DATA83 0x4005054cu
#define CYREG_SCB0_EZ_DATA84 0x40050550u
#define CYREG_SCB0_EZ_DATA85 0x40050554u
#define CYREG_SCB0_EZ_DATA86 0x40050558u
#define CYREG_SCB0_EZ_DATA87 0x4005055cu
#define CYREG_SCB0_EZ_DATA88 0x40050560u
#define CYREG_SCB0_EZ_DATA89 0x40050564u
#define CYREG_SCB0_EZ_DATA90 0x40050568u
#define CYREG_SCB0_EZ_DATA91 0x4005056cu
#define CYREG_SCB0_EZ_DATA92 0x40050570u
#define CYREG_SCB0_EZ_DATA93 0x40050574u
#define CYREG_SCB0_EZ_DATA94 0x40050578u
#define CYREG_SCB0_EZ_DATA95 0x4005057cu
#define CYREG_SCB0_EZ_DATA96 0x40050580u
#define CYREG_SCB0_EZ_DATA97 0x40050584u
#define CYREG_SCB0_EZ_DATA98 0x40050588u
#define CYREG_SCB0_EZ_DATA99 0x4005058cu
#define CYREG_SCB0_EZ_DATA100 0x40050590u
#define CYREG_SCB0_EZ_DATA101 0x40050594u
#define CYREG_SCB0_EZ_DATA102 0x40050598u
#define CYREG_SCB0_EZ_DATA103 0x4005059cu
#define CYREG_SCB0_EZ_DATA104 0x400505a0u
#define CYREG_SCB0_EZ_DATA105 0x400505a4u
#define CYREG_SCB0_EZ_DATA106 0x400505a8u
#define CYREG_SCB0_EZ_DATA107 0x400505acu
#define CYREG_SCB0_EZ_DATA108 0x400505b0u
#define CYREG_SCB0_EZ_DATA109 0x400505b4u
#define CYREG_SCB0_EZ_DATA110 0x400505b8u
#define CYREG_SCB0_EZ_DATA111 0x400505bcu
#define CYREG_SCB0_EZ_DATA112 0x400505c0u
#define CYREG_SCB0_EZ_DATA113 0x400505c4u
#define CYREG_SCB0_EZ_DATA114 0x400505c8u
#define CYREG_SCB0_EZ_DATA115 0x400505ccu
#define CYREG_SCB0_EZ_DATA116 0x400505d0u
#define CYREG_SCB0_EZ_DATA117 0x400505d4u
#define CYREG_SCB0_EZ_DATA118 0x400505d8u
#define CYREG_SCB0_EZ_DATA119 0x400505dcu
#define CYREG_SCB0_EZ_DATA120 0x400505e0u
#define CYREG_SCB0_EZ_DATA121 0x400505e4u
#define CYREG_SCB0_EZ_DATA122 0x400505e8u
#define CYREG_SCB0_EZ_DATA123 0x400505ecu
#define CYREG_SCB0_EZ_DATA124 0x400505f0u
#define CYREG_SCB0_EZ_DATA125 0x400505f4u
#define CYREG_SCB0_EZ_DATA126 0x400505f8u
#define CYREG_SCB0_EZ_DATA127 0x400505fcu
#define CYREG_SCB0_EZ_DATA128 0x40050600u
#define CYREG_SCB0_EZ_DATA129 0x40050604u
#define CYREG_SCB0_EZ_DATA130 0x40050608u
#define CYREG_SCB0_EZ_DATA131 0x4005060cu
#define CYREG_SCB0_EZ_DATA132 0x40050610u
#define CYREG_SCB0_EZ_DATA133 0x40050614u
#define CYREG_SCB0_EZ_DATA134 0x40050618u
#define CYREG_SCB0_EZ_DATA135 0x4005061cu
#define CYREG_SCB0_EZ_DATA136 0x40050620u
#define CYREG_SCB0_EZ_DATA137 0x40050624u
#define CYREG_SCB0_EZ_DATA138 0x40050628u
#define CYREG_SCB0_EZ_DATA139 0x4005062cu
#define CYREG_SCB0_EZ_DATA140 0x40050630u
#define CYREG_SCB0_EZ_DATA141 0x40050634u
#define CYREG_SCB0_EZ_DATA142 0x40050638u
#define CYREG_SCB0_EZ_DATA143 0x4005063cu
#define CYREG_SCB0_EZ_DATA144 0x40050640u
#define CYREG_SCB0_EZ_DATA145 0x40050644u
#define CYREG_SCB0_EZ_DATA146 0x40050648u
#define CYREG_SCB0_EZ_DATA147 0x4005064cu
#define CYREG_SCB0_EZ_DATA148 0x40050650u
#define CYREG_SCB0_EZ_DATA149 0x40050654u
#define CYREG_SCB0_EZ_DATA150 0x40050658u
#define CYREG_SCB0_EZ_DATA151 0x4005065cu
#define CYREG_SCB0_EZ_DATA152 0x40050660u
#define CYREG_SCB0_EZ_DATA153 0x40050664u
#define CYREG_SCB0_EZ_DATA154 0x40050668u
#define CYREG_SCB0_EZ_DATA155 0x4005066cu
#define CYREG_SCB0_EZ_DATA156 0x40050670u
#define CYREG_SCB0_EZ_DATA157 0x40050674u
#define CYREG_SCB0_EZ_DATA158 0x40050678u
#define CYREG_SCB0_EZ_DATA159 0x4005067cu
#define CYREG_SCB0_EZ_DATA160 0x40050680u
#define CYREG_SCB0_EZ_DATA161 0x40050684u
#define CYREG_SCB0_EZ_DATA162 0x40050688u
#define CYREG_SCB0_EZ_DATA163 0x4005068cu
#define CYREG_SCB0_EZ_DATA164 0x40050690u
#define CYREG_SCB0_EZ_DATA165 0x40050694u
#define CYREG_SCB0_EZ_DATA166 0x40050698u
#define CYREG_SCB0_EZ_DATA167 0x4005069cu
#define CYREG_SCB0_EZ_DATA168 0x400506a0u
#define CYREG_SCB0_EZ_DATA169 0x400506a4u
#define CYREG_SCB0_EZ_DATA170 0x400506a8u
#define CYREG_SCB0_EZ_DATA171 0x400506acu
#define CYREG_SCB0_EZ_DATA172 0x400506b0u
#define CYREG_SCB0_EZ_DATA173 0x400506b4u
#define CYREG_SCB0_EZ_DATA174 0x400506b8u
#define CYREG_SCB0_EZ_DATA175 0x400506bcu
#define CYREG_SCB0_EZ_DATA176 0x400506c0u
#define CYREG_SCB0_EZ_DATA177 0x400506c4u
#define CYREG_SCB0_EZ_DATA178 0x400506c8u
#define CYREG_SCB0_EZ_DATA179 0x400506ccu
#define CYREG_SCB0_EZ_DATA180 0x400506d0u
#define CYREG_SCB0_EZ_DATA181 0x400506d4u
#define CYREG_SCB0_EZ_DATA182 0x400506d8u
#define CYREG_SCB0_EZ_DATA183 0x400506dcu
#define CYREG_SCB0_EZ_DATA184 0x400506e0u
#define CYREG_SCB0_EZ_DATA185 0x400506e4u
#define CYREG_SCB0_EZ_DATA186 0x400506e8u
#define CYREG_SCB0_EZ_DATA187 0x400506ecu
#define CYREG_SCB0_EZ_DATA188 0x400506f0u
#define CYREG_SCB0_EZ_DATA189 0x400506f4u
#define CYREG_SCB0_EZ_DATA190 0x400506f8u
#define CYREG_SCB0_EZ_DATA191 0x400506fcu
#define CYREG_SCB0_EZ_DATA192 0x40050700u
#define CYREG_SCB0_EZ_DATA193 0x40050704u
#define CYREG_SCB0_EZ_DATA194 0x40050708u
#define CYREG_SCB0_EZ_DATA195 0x4005070cu
#define CYREG_SCB0_EZ_DATA196 0x40050710u
#define CYREG_SCB0_EZ_DATA197 0x40050714u
#define CYREG_SCB0_EZ_DATA198 0x40050718u
#define CYREG_SCB0_EZ_DATA199 0x4005071cu
#define CYREG_SCB0_EZ_DATA200 0x40050720u
#define CYREG_SCB0_EZ_DATA201 0x40050724u
#define CYREG_SCB0_EZ_DATA202 0x40050728u
#define CYREG_SCB0_EZ_DATA203 0x4005072cu
#define CYREG_SCB0_EZ_DATA204 0x40050730u
#define CYREG_SCB0_EZ_DATA205 0x40050734u
#define CYREG_SCB0_EZ_DATA206 0x40050738u
#define CYREG_SCB0_EZ_DATA207 0x4005073cu
#define CYREG_SCB0_EZ_DATA208 0x40050740u
#define CYREG_SCB0_EZ_DATA209 0x40050744u
#define CYREG_SCB0_EZ_DATA210 0x40050748u
#define CYREG_SCB0_EZ_DATA211 0x4005074cu
#define CYREG_SCB0_EZ_DATA212 0x40050750u
#define CYREG_SCB0_EZ_DATA213 0x40050754u
#define CYREG_SCB0_EZ_DATA214 0x40050758u
#define CYREG_SCB0_EZ_DATA215 0x4005075cu
#define CYREG_SCB0_EZ_DATA216 0x40050760u
#define CYREG_SCB0_EZ_DATA217 0x40050764u
#define CYREG_SCB0_EZ_DATA218 0x40050768u
#define CYREG_SCB0_EZ_DATA219 0x4005076cu
#define CYREG_SCB0_EZ_DATA220 0x40050770u
#define CYREG_SCB0_EZ_DATA221 0x40050774u
#define CYREG_SCB0_EZ_DATA222 0x40050778u
#define CYREG_SCB0_EZ_DATA223 0x4005077cu
#define CYREG_SCB0_EZ_DATA224 0x40050780u
#define CYREG_SCB0_EZ_DATA225 0x40050784u
#define CYREG_SCB0_EZ_DATA226 0x40050788u
#define CYREG_SCB0_EZ_DATA227 0x4005078cu
#define CYREG_SCB0_EZ_DATA228 0x40050790u
#define CYREG_SCB0_EZ_DATA229 0x40050794u
#define CYREG_SCB0_EZ_DATA230 0x40050798u
#define CYREG_SCB0_EZ_DATA231 0x4005079cu
#define CYREG_SCB0_EZ_DATA232 0x400507a0u
#define CYREG_SCB0_EZ_DATA233 0x400507a4u
#define CYREG_SCB0_EZ_DATA234 0x400507a8u
#define CYREG_SCB0_EZ_DATA235 0x400507acu
#define CYREG_SCB0_EZ_DATA236 0x400507b0u
#define CYREG_SCB0_EZ_DATA237 0x400507b4u
#define CYREG_SCB0_EZ_DATA238 0x400507b8u
#define CYREG_SCB0_EZ_DATA239 0x400507bcu
#define CYREG_SCB0_EZ_DATA240 0x400507c0u
#define CYREG_SCB0_EZ_DATA241 0x400507c4u
#define CYREG_SCB0_EZ_DATA242 0x400507c8u
#define CYREG_SCB0_EZ_DATA243 0x400507ccu
#define CYREG_SCB0_EZ_DATA244 0x400507d0u
#define CYREG_SCB0_EZ_DATA245 0x400507d4u
#define CYREG_SCB0_EZ_DATA246 0x400507d8u
#define CYREG_SCB0_EZ_DATA247 0x400507dcu
#define CYREG_SCB0_EZ_DATA248 0x400507e0u
#define CYREG_SCB0_EZ_DATA249 0x400507e4u
#define CYREG_SCB0_EZ_DATA250 0x400507e8u
#define CYREG_SCB0_EZ_DATA251 0x400507ecu
#define CYREG_SCB0_EZ_DATA252 0x400507f0u
#define CYREG_SCB0_EZ_DATA253 0x400507f4u
#define CYREG_SCB0_EZ_DATA254 0x400507f8u
#define CYREG_SCB0_EZ_DATA255 0x400507fcu
#define CYREG_SCB0_INTR_CAUSE 0x40050e00u
#define CYFLD_SCB_M__OFFSET 0x00000000u
#define CYFLD_SCB_M__SIZE 0x00000001u
#define CYFLD_SCB_S__OFFSET 0x00000001u
#define CYFLD_SCB_S__SIZE 0x00000001u
#define CYFLD_SCB_TX__OFFSET 0x00000002u
#define CYFLD_SCB_TX__SIZE 0x00000001u
#define CYFLD_SCB_RX__OFFSET 0x00000003u
#define CYFLD_SCB_RX__SIZE 0x00000001u
#define CYFLD_SCB_I2C_EC__OFFSET 0x00000004u
#define CYFLD_SCB_I2C_EC__SIZE 0x00000001u
#define CYFLD_SCB_SPI_EC__OFFSET 0x00000005u
#define CYFLD_SCB_SPI_EC__SIZE 0x00000001u
#define CYREG_SCB0_INTR_I2C_EC 0x40050e80u
#define CYFLD_SCB_WAKE_UP__OFFSET 0x00000000u
#define CYFLD_SCB_WAKE_UP__SIZE 0x00000001u
#define CYFLD_SCB_EZ_STOP__OFFSET 0x00000001u
#define CYFLD_SCB_EZ_STOP__SIZE 0x00000001u
#define CYFLD_SCB_EZ_WRITE_STOP__OFFSET 0x00000002u
#define CYFLD_SCB_EZ_WRITE_STOP__SIZE 0x00000001u
#define CYFLD_SCB_EZ_READ_STOP__OFFSET 0x00000003u
#define CYFLD_SCB_EZ_READ_STOP__SIZE 0x00000001u
#define CYREG_SCB0_INTR_I2C_EC_MASK 0x40050e88u
#define CYREG_SCB0_INTR_I2C_EC_MASKED 0x40050e8cu
#define CYREG_SCB0_INTR_SPI_EC 0x40050ec0u
#define CYREG_SCB0_INTR_SPI_EC_MASK 0x40050ec8u
#define CYREG_SCB0_INTR_SPI_EC_MASKED 0x40050eccu
#define CYREG_SCB0_INTR_M 0x40050f00u
#define CYFLD_SCB_I2C_ARB_LOST__OFFSET 0x00000000u
#define CYFLD_SCB_I2C_ARB_LOST__SIZE 0x00000001u
#define CYFLD_SCB_I2C_NACK__OFFSET 0x00000001u
#define CYFLD_SCB_I2C_NACK__SIZE 0x00000001u
#define CYFLD_SCB_I2C_ACK__OFFSET 0x00000002u
#define CYFLD_SCB_I2C_ACK__SIZE 0x00000001u
#define CYFLD_SCB_I2C_STOP__OFFSET 0x00000004u
#define CYFLD_SCB_I2C_STOP__SIZE 0x00000001u
#define CYFLD_SCB_I2C_BUS_ERROR__OFFSET 0x00000008u
#define CYFLD_SCB_I2C_BUS_ERROR__SIZE 0x00000001u
#define CYFLD_SCB_SPI_DONE__OFFSET 0x00000009u
#define CYFLD_SCB_SPI_DONE__SIZE 0x00000001u
#define CYREG_SCB0_INTR_M_SET 0x40050f04u
#define CYREG_SCB0_INTR_M_MASK 0x40050f08u
#define CYREG_SCB0_INTR_M_MASKED 0x40050f0cu
#define CYREG_SCB0_INTR_S 0x40050f40u
#define CYFLD_SCB_I2C_WRITE_STOP__OFFSET 0x00000003u
#define CYFLD_SCB_I2C_WRITE_STOP__SIZE 0x00000001u
#define CYFLD_SCB_I2C_START__OFFSET 0x00000005u
#define CYFLD_SCB_I2C_START__SIZE 0x00000001u
#define CYFLD_SCB_I2C_ADDR_MATCH__OFFSET 0x00000006u
#define CYFLD_SCB_I2C_ADDR_MATCH__SIZE 0x00000001u
#define CYFLD_SCB_I2C_GENERAL__OFFSET 0x00000007u
#define CYFLD_SCB_I2C_GENERAL__SIZE 0x00000001u
#define CYFLD_SCB_SPI_EZ_WRITE_STOP__OFFSET 0x00000009u
#define CYFLD_SCB_SPI_EZ_WRITE_STOP__SIZE 0x00000001u
#define CYFLD_SCB_SPI_EZ_STOP__OFFSET 0x0000000au
#define CYFLD_SCB_SPI_EZ_STOP__SIZE 0x00000001u
#define CYFLD_SCB_SPI_BUS_ERROR__OFFSET 0x0000000bu
#define CYFLD_SCB_SPI_BUS_ERROR__SIZE 0x00000001u
#define CYREG_SCB0_INTR_S_SET 0x40050f44u
#define CYREG_SCB0_INTR_S_MASK 0x40050f48u
#define CYREG_SCB0_INTR_S_MASKED 0x40050f4cu
#define CYREG_SCB0_INTR_TX 0x40050f80u
#define CYFLD_SCB_TRIGGER__OFFSET 0x00000000u
#define CYFLD_SCB_TRIGGER__SIZE 0x00000001u
#define CYFLD_SCB_NOT_FULL__OFFSET 0x00000001u
#define CYFLD_SCB_NOT_FULL__SIZE 0x00000001u
#define CYFLD_SCB_EMPTY__OFFSET 0x00000004u
#define CYFLD_SCB_EMPTY__SIZE 0x00000001u
#define CYFLD_SCB_OVERFLOW__OFFSET 0x00000005u
#define CYFLD_SCB_OVERFLOW__SIZE 0x00000001u
#define CYFLD_SCB_UNDERFLOW__OFFSET 0x00000006u
#define CYFLD_SCB_UNDERFLOW__SIZE 0x00000001u
#define CYFLD_SCB_BLOCKED__OFFSET 0x00000007u
#define CYFLD_SCB_BLOCKED__SIZE 0x00000001u
#define CYFLD_SCB_UART_NACK__OFFSET 0x00000008u
#define CYFLD_SCB_UART_NACK__SIZE 0x00000001u
#define CYFLD_SCB_UART_DONE__OFFSET 0x00000009u
#define CYFLD_SCB_UART_DONE__SIZE 0x00000001u
#define CYFLD_SCB_UART_ARB_LOST__OFFSET 0x0000000au
#define CYFLD_SCB_UART_ARB_LOST__SIZE 0x00000001u
#define CYREG_SCB0_INTR_TX_SET 0x40050f84u
#define CYREG_SCB0_INTR_TX_MASK 0x40050f88u
#define CYREG_SCB0_INTR_TX_MASKED 0x40050f8cu
#define CYREG_SCB0_INTR_RX 0x40050fc0u
#define CYFLD_SCB_NOT_EMPTY__OFFSET 0x00000002u
#define CYFLD_SCB_NOT_EMPTY__SIZE 0x00000001u
#define CYFLD_SCB_FULL__OFFSET 0x00000003u
#define CYFLD_SCB_FULL__SIZE 0x00000001u
#define CYFLD_SCB_FRAME_ERROR__OFFSET 0x00000008u
#define CYFLD_SCB_FRAME_ERROR__SIZE 0x00000001u
#define CYFLD_SCB_PARITY_ERROR__OFFSET 0x00000009u
#define CYFLD_SCB_PARITY_ERROR__SIZE 0x00000001u
#define CYFLD_SCB_BAUD_DETECT__OFFSET 0x0000000au
#define CYFLD_SCB_BAUD_DETECT__SIZE 0x00000001u
#define CYFLD_SCB_BREAK_DETECT__OFFSET 0x0000000bu
#define CYFLD_SCB_BREAK_DETECT__SIZE 0x00000001u
#define CYREG_SCB0_INTR_RX_SET 0x40050fc4u
#define CYREG_SCB0_INTR_RX_MASK 0x40050fc8u
#define CYREG_SCB0_INTR_RX_MASKED 0x40050fccu
#define CYDEV_SCB1_BASE 0x40060000u
#define CYDEV_SCB1_SIZE 0x00010000u
#define CYREG_SCB1_CTRL 0x40060000u
#define CYREG_SCB1_STATUS 0x40060004u
#define CYREG_SCB1_CMD_RESP_CTRL 0x40060008u
#define CYREG_SCB1_CMD_RESP_STATUS 0x4006000cu
#define CYREG_SCB1_SPI_CTRL 0x40060020u
#define CYREG_SCB1_SPI_STATUS 0x40060024u
#define CYREG_SCB1_UART_CTRL 0x40060040u
#define CYREG_SCB1_UART_TX_CTRL 0x40060044u
#define CYREG_SCB1_UART_RX_CTRL 0x40060048u
#define CYREG_SCB1_UART_RX_STATUS 0x4006004cu
#define CYREG_SCB1_UART_FLOW_CTRL 0x40060050u
#define CYREG_SCB1_I2C_CTRL 0x40060060u
#define CYREG_SCB1_I2C_STATUS 0x40060064u
#define CYREG_SCB1_I2C_M_CMD 0x40060068u
#define CYREG_SCB1_I2C_S_CMD 0x4006006cu
#define CYREG_SCB1_I2C_CFG 0x40060070u
#define CYREG_SCB1_TX_CTRL 0x40060200u
#define CYREG_SCB1_TX_FIFO_CTRL 0x40060204u
#define CYREG_SCB1_TX_FIFO_STATUS 0x40060208u
#define CYREG_SCB1_TX_FIFO_WR 0x40060240u
#define CYREG_SCB1_RX_CTRL 0x40060300u
#define CYREG_SCB1_RX_FIFO_CTRL 0x40060304u
#define CYREG_SCB1_RX_FIFO_STATUS 0x40060308u
#define CYREG_SCB1_RX_MATCH 0x40060310u
#define CYREG_SCB1_RX_FIFO_RD 0x40060340u
#define CYREG_SCB1_RX_FIFO_RD_SILENT 0x40060344u
#define CYREG_SCB1_EZ_DATA0 0x40060400u
#define CYREG_SCB1_EZ_DATA1 0x40060404u
#define CYREG_SCB1_EZ_DATA2 0x40060408u
#define CYREG_SCB1_EZ_DATA3 0x4006040cu
#define CYREG_SCB1_EZ_DATA4 0x40060410u
#define CYREG_SCB1_EZ_DATA5 0x40060414u
#define CYREG_SCB1_EZ_DATA6 0x40060418u
#define CYREG_SCB1_EZ_DATA7 0x4006041cu
#define CYREG_SCB1_EZ_DATA8 0x40060420u
#define CYREG_SCB1_EZ_DATA9 0x40060424u
#define CYREG_SCB1_EZ_DATA10 0x40060428u
#define CYREG_SCB1_EZ_DATA11 0x4006042cu
#define CYREG_SCB1_EZ_DATA12 0x40060430u
#define CYREG_SCB1_EZ_DATA13 0x40060434u
#define CYREG_SCB1_EZ_DATA14 0x40060438u
#define CYREG_SCB1_EZ_DATA15 0x4006043cu
#define CYREG_SCB1_EZ_DATA16 0x40060440u
#define CYREG_SCB1_EZ_DATA17 0x40060444u
#define CYREG_SCB1_EZ_DATA18 0x40060448u
#define CYREG_SCB1_EZ_DATA19 0x4006044cu
#define CYREG_SCB1_EZ_DATA20 0x40060450u
#define CYREG_SCB1_EZ_DATA21 0x40060454u
#define CYREG_SCB1_EZ_DATA22 0x40060458u
#define CYREG_SCB1_EZ_DATA23 0x4006045cu
#define CYREG_SCB1_EZ_DATA24 0x40060460u
#define CYREG_SCB1_EZ_DATA25 0x40060464u
#define CYREG_SCB1_EZ_DATA26 0x40060468u
#define CYREG_SCB1_EZ_DATA27 0x4006046cu
#define CYREG_SCB1_EZ_DATA28 0x40060470u
#define CYREG_SCB1_EZ_DATA29 0x40060474u
#define CYREG_SCB1_EZ_DATA30 0x40060478u
#define CYREG_SCB1_EZ_DATA31 0x4006047cu
#define CYREG_SCB1_EZ_DATA32 0x40060480u
#define CYREG_SCB1_EZ_DATA33 0x40060484u
#define CYREG_SCB1_EZ_DATA34 0x40060488u
#define CYREG_SCB1_EZ_DATA35 0x4006048cu
#define CYREG_SCB1_EZ_DATA36 0x40060490u
#define CYREG_SCB1_EZ_DATA37 0x40060494u
#define CYREG_SCB1_EZ_DATA38 0x40060498u
#define CYREG_SCB1_EZ_DATA39 0x4006049cu
#define CYREG_SCB1_EZ_DATA40 0x400604a0u
#define CYREG_SCB1_EZ_DATA41 0x400604a4u
#define CYREG_SCB1_EZ_DATA42 0x400604a8u
#define CYREG_SCB1_EZ_DATA43 0x400604acu
#define CYREG_SCB1_EZ_DATA44 0x400604b0u
#define CYREG_SCB1_EZ_DATA45 0x400604b4u
#define CYREG_SCB1_EZ_DATA46 0x400604b8u
#define CYREG_SCB1_EZ_DATA47 0x400604bcu
#define CYREG_SCB1_EZ_DATA48 0x400604c0u
#define CYREG_SCB1_EZ_DATA49 0x400604c4u
#define CYREG_SCB1_EZ_DATA50 0x400604c8u
#define CYREG_SCB1_EZ_DATA51 0x400604ccu
#define CYREG_SCB1_EZ_DATA52 0x400604d0u
#define CYREG_SCB1_EZ_DATA53 0x400604d4u
#define CYREG_SCB1_EZ_DATA54 0x400604d8u
#define CYREG_SCB1_EZ_DATA55 0x400604dcu
#define CYREG_SCB1_EZ_DATA56 0x400604e0u
#define CYREG_SCB1_EZ_DATA57 0x400604e4u
#define CYREG_SCB1_EZ_DATA58 0x400604e8u
#define CYREG_SCB1_EZ_DATA59 0x400604ecu
#define CYREG_SCB1_EZ_DATA60 0x400604f0u
#define CYREG_SCB1_EZ_DATA61 0x400604f4u
#define CYREG_SCB1_EZ_DATA62 0x400604f8u
#define CYREG_SCB1_EZ_DATA63 0x400604fcu
#define CYREG_SCB1_EZ_DATA64 0x40060500u
#define CYREG_SCB1_EZ_DATA65 0x40060504u
#define CYREG_SCB1_EZ_DATA66 0x40060508u
#define CYREG_SCB1_EZ_DATA67 0x4006050cu
#define CYREG_SCB1_EZ_DATA68 0x40060510u
#define CYREG_SCB1_EZ_DATA69 0x40060514u
#define CYREG_SCB1_EZ_DATA70 0x40060518u
#define CYREG_SCB1_EZ_DATA71 0x4006051cu
#define CYREG_SCB1_EZ_DATA72 0x40060520u
#define CYREG_SCB1_EZ_DATA73 0x40060524u
#define CYREG_SCB1_EZ_DATA74 0x40060528u
#define CYREG_SCB1_EZ_DATA75 0x4006052cu
#define CYREG_SCB1_EZ_DATA76 0x40060530u
#define CYREG_SCB1_EZ_DATA77 0x40060534u
#define CYREG_SCB1_EZ_DATA78 0x40060538u
#define CYREG_SCB1_EZ_DATA79 0x4006053cu
#define CYREG_SCB1_EZ_DATA80 0x40060540u
#define CYREG_SCB1_EZ_DATA81 0x40060544u
#define CYREG_SCB1_EZ_DATA82 0x40060548u
#define CYREG_SCB1_EZ_DATA83 0x4006054cu
#define CYREG_SCB1_EZ_DATA84 0x40060550u
#define CYREG_SCB1_EZ_DATA85 0x40060554u
#define CYREG_SCB1_EZ_DATA86 0x40060558u
#define CYREG_SCB1_EZ_DATA87 0x4006055cu
#define CYREG_SCB1_EZ_DATA88 0x40060560u
#define CYREG_SCB1_EZ_DATA89 0x40060564u
#define CYREG_SCB1_EZ_DATA90 0x40060568u
#define CYREG_SCB1_EZ_DATA91 0x4006056cu
#define CYREG_SCB1_EZ_DATA92 0x40060570u
#define CYREG_SCB1_EZ_DATA93 0x40060574u
#define CYREG_SCB1_EZ_DATA94 0x40060578u
#define CYREG_SCB1_EZ_DATA95 0x4006057cu
#define CYREG_SCB1_EZ_DATA96 0x40060580u
#define CYREG_SCB1_EZ_DATA97 0x40060584u
#define CYREG_SCB1_EZ_DATA98 0x40060588u
#define CYREG_SCB1_EZ_DATA99 0x4006058cu
#define CYREG_SCB1_EZ_DATA100 0x40060590u
#define CYREG_SCB1_EZ_DATA101 0x40060594u
#define CYREG_SCB1_EZ_DATA102 0x40060598u
#define CYREG_SCB1_EZ_DATA103 0x4006059cu
#define CYREG_SCB1_EZ_DATA104 0x400605a0u
#define CYREG_SCB1_EZ_DATA105 0x400605a4u
#define CYREG_SCB1_EZ_DATA106 0x400605a8u
#define CYREG_SCB1_EZ_DATA107 0x400605acu
#define CYREG_SCB1_EZ_DATA108 0x400605b0u
#define CYREG_SCB1_EZ_DATA109 0x400605b4u
#define CYREG_SCB1_EZ_DATA110 0x400605b8u
#define CYREG_SCB1_EZ_DATA111 0x400605bcu
#define CYREG_SCB1_EZ_DATA112 0x400605c0u
#define CYREG_SCB1_EZ_DATA113 0x400605c4u
#define CYREG_SCB1_EZ_DATA114 0x400605c8u
#define CYREG_SCB1_EZ_DATA115 0x400605ccu
#define CYREG_SCB1_EZ_DATA116 0x400605d0u
#define CYREG_SCB1_EZ_DATA117 0x400605d4u
#define CYREG_SCB1_EZ_DATA118 0x400605d8u
#define CYREG_SCB1_EZ_DATA119 0x400605dcu
#define CYREG_SCB1_EZ_DATA120 0x400605e0u
#define CYREG_SCB1_EZ_DATA121 0x400605e4u
#define CYREG_SCB1_EZ_DATA122 0x400605e8u
#define CYREG_SCB1_EZ_DATA123 0x400605ecu
#define CYREG_SCB1_EZ_DATA124 0x400605f0u
#define CYREG_SCB1_EZ_DATA125 0x400605f4u
#define CYREG_SCB1_EZ_DATA126 0x400605f8u
#define CYREG_SCB1_EZ_DATA127 0x400605fcu
#define CYREG_SCB1_EZ_DATA128 0x40060600u
#define CYREG_SCB1_EZ_DATA129 0x40060604u
#define CYREG_SCB1_EZ_DATA130 0x40060608u
#define CYREG_SCB1_EZ_DATA131 0x4006060cu
#define CYREG_SCB1_EZ_DATA132 0x40060610u
#define CYREG_SCB1_EZ_DATA133 0x40060614u
#define CYREG_SCB1_EZ_DATA134 0x40060618u
#define CYREG_SCB1_EZ_DATA135 0x4006061cu
#define CYREG_SCB1_EZ_DATA136 0x40060620u
#define CYREG_SCB1_EZ_DATA137 0x40060624u
#define CYREG_SCB1_EZ_DATA138 0x40060628u
#define CYREG_SCB1_EZ_DATA139 0x4006062cu
#define CYREG_SCB1_EZ_DATA140 0x40060630u
#define CYREG_SCB1_EZ_DATA141 0x40060634u
#define CYREG_SCB1_EZ_DATA142 0x40060638u
#define CYREG_SCB1_EZ_DATA143 0x4006063cu
#define CYREG_SCB1_EZ_DATA144 0x40060640u
#define CYREG_SCB1_EZ_DATA145 0x40060644u
#define CYREG_SCB1_EZ_DATA146 0x40060648u
#define CYREG_SCB1_EZ_DATA147 0x4006064cu
#define CYREG_SCB1_EZ_DATA148 0x40060650u
#define CYREG_SCB1_EZ_DATA149 0x40060654u
#define CYREG_SCB1_EZ_DATA150 0x40060658u
#define CYREG_SCB1_EZ_DATA151 0x4006065cu
#define CYREG_SCB1_EZ_DATA152 0x40060660u
#define CYREG_SCB1_EZ_DATA153 0x40060664u
#define CYREG_SCB1_EZ_DATA154 0x40060668u
#define CYREG_SCB1_EZ_DATA155 0x4006066cu
#define CYREG_SCB1_EZ_DATA156 0x40060670u
#define CYREG_SCB1_EZ_DATA157 0x40060674u
#define CYREG_SCB1_EZ_DATA158 0x40060678u
#define CYREG_SCB1_EZ_DATA159 0x4006067cu
#define CYREG_SCB1_EZ_DATA160 0x40060680u
#define CYREG_SCB1_EZ_DATA161 0x40060684u
#define CYREG_SCB1_EZ_DATA162 0x40060688u
#define CYREG_SCB1_EZ_DATA163 0x4006068cu
#define CYREG_SCB1_EZ_DATA164 0x40060690u
#define CYREG_SCB1_EZ_DATA165 0x40060694u
#define CYREG_SCB1_EZ_DATA166 0x40060698u
#define CYREG_SCB1_EZ_DATA167 0x4006069cu
#define CYREG_SCB1_EZ_DATA168 0x400606a0u
#define CYREG_SCB1_EZ_DATA169 0x400606a4u
#define CYREG_SCB1_EZ_DATA170 0x400606a8u
#define CYREG_SCB1_EZ_DATA171 0x400606acu
#define CYREG_SCB1_EZ_DATA172 0x400606b0u
#define CYREG_SCB1_EZ_DATA173 0x400606b4u
#define CYREG_SCB1_EZ_DATA174 0x400606b8u
#define CYREG_SCB1_EZ_DATA175 0x400606bcu
#define CYREG_SCB1_EZ_DATA176 0x400606c0u
#define CYREG_SCB1_EZ_DATA177 0x400606c4u
#define CYREG_SCB1_EZ_DATA178 0x400606c8u
#define CYREG_SCB1_EZ_DATA179 0x400606ccu
#define CYREG_SCB1_EZ_DATA180 0x400606d0u
#define CYREG_SCB1_EZ_DATA181 0x400606d4u
#define CYREG_SCB1_EZ_DATA182 0x400606d8u
#define CYREG_SCB1_EZ_DATA183 0x400606dcu
#define CYREG_SCB1_EZ_DATA184 0x400606e0u
#define CYREG_SCB1_EZ_DATA185 0x400606e4u
#define CYREG_SCB1_EZ_DATA186 0x400606e8u
#define CYREG_SCB1_EZ_DATA187 0x400606ecu
#define CYREG_SCB1_EZ_DATA188 0x400606f0u
#define CYREG_SCB1_EZ_DATA189 0x400606f4u
#define CYREG_SCB1_EZ_DATA190 0x400606f8u
#define CYREG_SCB1_EZ_DATA191 0x400606fcu
#define CYREG_SCB1_EZ_DATA192 0x40060700u
#define CYREG_SCB1_EZ_DATA193 0x40060704u
#define CYREG_SCB1_EZ_DATA194 0x40060708u
#define CYREG_SCB1_EZ_DATA195 0x4006070cu
#define CYREG_SCB1_EZ_DATA196 0x40060710u
#define CYREG_SCB1_EZ_DATA197 0x40060714u
#define CYREG_SCB1_EZ_DATA198 0x40060718u
#define CYREG_SCB1_EZ_DATA199 0x4006071cu
#define CYREG_SCB1_EZ_DATA200 0x40060720u
#define CYREG_SCB1_EZ_DATA201 0x40060724u
#define CYREG_SCB1_EZ_DATA202 0x40060728u
#define CYREG_SCB1_EZ_DATA203 0x4006072cu
#define CYREG_SCB1_EZ_DATA204 0x40060730u
#define CYREG_SCB1_EZ_DATA205 0x40060734u
#define CYREG_SCB1_EZ_DATA206 0x40060738u
#define CYREG_SCB1_EZ_DATA207 0x4006073cu
#define CYREG_SCB1_EZ_DATA208 0x40060740u
#define CYREG_SCB1_EZ_DATA209 0x40060744u
#define CYREG_SCB1_EZ_DATA210 0x40060748u
#define CYREG_SCB1_EZ_DATA211 0x4006074cu
#define CYREG_SCB1_EZ_DATA212 0x40060750u
#define CYREG_SCB1_EZ_DATA213 0x40060754u
#define CYREG_SCB1_EZ_DATA214 0x40060758u
#define CYREG_SCB1_EZ_DATA215 0x4006075cu
#define CYREG_SCB1_EZ_DATA216 0x40060760u
#define CYREG_SCB1_EZ_DATA217 0x40060764u
#define CYREG_SCB1_EZ_DATA218 0x40060768u
#define CYREG_SCB1_EZ_DATA219 0x4006076cu
#define CYREG_SCB1_EZ_DATA220 0x40060770u
#define CYREG_SCB1_EZ_DATA221 0x40060774u
#define CYREG_SCB1_EZ_DATA222 0x40060778u
#define CYREG_SCB1_EZ_DATA223 0x4006077cu
#define CYREG_SCB1_EZ_DATA224 0x40060780u
#define CYREG_SCB1_EZ_DATA225 0x40060784u
#define CYREG_SCB1_EZ_DATA226 0x40060788u
#define CYREG_SCB1_EZ_DATA227 0x4006078cu
#define CYREG_SCB1_EZ_DATA228 0x40060790u
#define CYREG_SCB1_EZ_DATA229 0x40060794u
#define CYREG_SCB1_EZ_DATA230 0x40060798u
#define CYREG_SCB1_EZ_DATA231 0x4006079cu
#define CYREG_SCB1_EZ_DATA232 0x400607a0u
#define CYREG_SCB1_EZ_DATA233 0x400607a4u
#define CYREG_SCB1_EZ_DATA234 0x400607a8u
#define CYREG_SCB1_EZ_DATA235 0x400607acu
#define CYREG_SCB1_EZ_DATA236 0x400607b0u
#define CYREG_SCB1_EZ_DATA237 0x400607b4u
#define CYREG_SCB1_EZ_DATA238 0x400607b8u
#define CYREG_SCB1_EZ_DATA239 0x400607bcu
#define CYREG_SCB1_EZ_DATA240 0x400607c0u
#define CYREG_SCB1_EZ_DATA241 0x400607c4u
#define CYREG_SCB1_EZ_DATA242 0x400607c8u
#define CYREG_SCB1_EZ_DATA243 0x400607ccu
#define CYREG_SCB1_EZ_DATA244 0x400607d0u
#define CYREG_SCB1_EZ_DATA245 0x400607d4u
#define CYREG_SCB1_EZ_DATA246 0x400607d8u
#define CYREG_SCB1_EZ_DATA247 0x400607dcu
#define CYREG_SCB1_EZ_DATA248 0x400607e0u
#define CYREG_SCB1_EZ_DATA249 0x400607e4u
#define CYREG_SCB1_EZ_DATA250 0x400607e8u
#define CYREG_SCB1_EZ_DATA251 0x400607ecu
#define CYREG_SCB1_EZ_DATA252 0x400607f0u
#define CYREG_SCB1_EZ_DATA253 0x400607f4u
#define CYREG_SCB1_EZ_DATA254 0x400607f8u
#define CYREG_SCB1_EZ_DATA255 0x400607fcu
#define CYREG_SCB1_INTR_CAUSE 0x40060e00u
#define CYREG_SCB1_INTR_I2C_EC 0x40060e80u
#define CYREG_SCB1_INTR_I2C_EC_MASK 0x40060e88u
#define CYREG_SCB1_INTR_I2C_EC_MASKED 0x40060e8cu
#define CYREG_SCB1_INTR_SPI_EC 0x40060ec0u
#define CYREG_SCB1_INTR_SPI_EC_MASK 0x40060ec8u
#define CYREG_SCB1_INTR_SPI_EC_MASKED 0x40060eccu
#define CYREG_SCB1_INTR_M 0x40060f00u
#define CYREG_SCB1_INTR_M_SET 0x40060f04u
#define CYREG_SCB1_INTR_M_MASK 0x40060f08u
#define CYREG_SCB1_INTR_M_MASKED 0x40060f0cu
#define CYREG_SCB1_INTR_S 0x40060f40u
#define CYREG_SCB1_INTR_S_SET 0x40060f44u
#define CYREG_SCB1_INTR_S_MASK 0x40060f48u
#define CYREG_SCB1_INTR_S_MASKED 0x40060f4cu
#define CYREG_SCB1_INTR_TX 0x40060f80u
#define CYREG_SCB1_INTR_TX_SET 0x40060f84u
#define CYREG_SCB1_INTR_TX_MASK 0x40060f88u
#define CYREG_SCB1_INTR_TX_MASKED 0x40060f8cu
#define CYREG_SCB1_INTR_RX 0x40060fc0u
#define CYREG_SCB1_INTR_RX_SET 0x40060fc4u
#define CYREG_SCB1_INTR_RX_MASK 0x40060fc8u
#define CYREG_SCB1_INTR_RX_MASKED 0x40060fccu
#define CYDEV_SCB2_BASE 0x40070000u
#define CYDEV_SCB2_SIZE 0x00010000u
#define CYREG_SCB2_CTRL 0x40070000u
#define CYREG_SCB2_STATUS 0x40070004u
#define CYREG_SCB2_CMD_RESP_CTRL 0x40070008u
#define CYREG_SCB2_CMD_RESP_STATUS 0x4007000cu
#define CYREG_SCB2_SPI_CTRL 0x40070020u
#define CYREG_SCB2_SPI_STATUS 0x40070024u
#define CYREG_SCB2_UART_CTRL 0x40070040u
#define CYREG_SCB2_UART_TX_CTRL 0x40070044u
#define CYREG_SCB2_UART_RX_CTRL 0x40070048u
#define CYREG_SCB2_UART_RX_STATUS 0x4007004cu
#define CYREG_SCB2_UART_FLOW_CTRL 0x40070050u
#define CYREG_SCB2_I2C_CTRL 0x40070060u
#define CYREG_SCB2_I2C_STATUS 0x40070064u
#define CYREG_SCB2_I2C_M_CMD 0x40070068u
#define CYREG_SCB2_I2C_S_CMD 0x4007006cu
#define CYREG_SCB2_I2C_CFG 0x40070070u
#define CYREG_SCB2_TX_CTRL 0x40070200u
#define CYREG_SCB2_TX_FIFO_CTRL 0x40070204u
#define CYREG_SCB2_TX_FIFO_STATUS 0x40070208u
#define CYREG_SCB2_TX_FIFO_WR 0x40070240u
#define CYREG_SCB2_RX_CTRL 0x40070300u
#define CYREG_SCB2_RX_FIFO_CTRL 0x40070304u
#define CYREG_SCB2_RX_FIFO_STATUS 0x40070308u
#define CYREG_SCB2_RX_MATCH 0x40070310u
#define CYREG_SCB2_RX_FIFO_RD 0x40070340u
#define CYREG_SCB2_RX_FIFO_RD_SILENT 0x40070344u
#define CYREG_SCB2_EZ_DATA0 0x40070400u
#define CYREG_SCB2_EZ_DATA1 0x40070404u
#define CYREG_SCB2_EZ_DATA2 0x40070408u
#define CYREG_SCB2_EZ_DATA3 0x4007040cu
#define CYREG_SCB2_EZ_DATA4 0x40070410u
#define CYREG_SCB2_EZ_DATA5 0x40070414u
#define CYREG_SCB2_EZ_DATA6 0x40070418u
#define CYREG_SCB2_EZ_DATA7 0x4007041cu
#define CYREG_SCB2_EZ_DATA8 0x40070420u
#define CYREG_SCB2_EZ_DATA9 0x40070424u
#define CYREG_SCB2_EZ_DATA10 0x40070428u
#define CYREG_SCB2_EZ_DATA11 0x4007042cu
#define CYREG_SCB2_EZ_DATA12 0x40070430u
#define CYREG_SCB2_EZ_DATA13 0x40070434u
#define CYREG_SCB2_EZ_DATA14 0x40070438u
#define CYREG_SCB2_EZ_DATA15 0x4007043cu
#define CYREG_SCB2_EZ_DATA16 0x40070440u
#define CYREG_SCB2_EZ_DATA17 0x40070444u
#define CYREG_SCB2_EZ_DATA18 0x40070448u
#define CYREG_SCB2_EZ_DATA19 0x4007044cu
#define CYREG_SCB2_EZ_DATA20 0x40070450u
#define CYREG_SCB2_EZ_DATA21 0x40070454u
#define CYREG_SCB2_EZ_DATA22 0x40070458u
#define CYREG_SCB2_EZ_DATA23 0x4007045cu
#define CYREG_SCB2_EZ_DATA24 0x40070460u
#define CYREG_SCB2_EZ_DATA25 0x40070464u
#define CYREG_SCB2_EZ_DATA26 0x40070468u
#define CYREG_SCB2_EZ_DATA27 0x4007046cu
#define CYREG_SCB2_EZ_DATA28 0x40070470u
#define CYREG_SCB2_EZ_DATA29 0x40070474u
#define CYREG_SCB2_EZ_DATA30 0x40070478u
#define CYREG_SCB2_EZ_DATA31 0x4007047cu
#define CYREG_SCB2_EZ_DATA32 0x40070480u
#define CYREG_SCB2_EZ_DATA33 0x40070484u
#define CYREG_SCB2_EZ_DATA34 0x40070488u
#define CYREG_SCB2_EZ_DATA35 0x4007048cu
#define CYREG_SCB2_EZ_DATA36 0x40070490u
#define CYREG_SCB2_EZ_DATA37 0x40070494u
#define CYREG_SCB2_EZ_DATA38 0x40070498u
#define CYREG_SCB2_EZ_DATA39 0x4007049cu
#define CYREG_SCB2_EZ_DATA40 0x400704a0u
#define CYREG_SCB2_EZ_DATA41 0x400704a4u
#define CYREG_SCB2_EZ_DATA42 0x400704a8u
#define CYREG_SCB2_EZ_DATA43 0x400704acu
#define CYREG_SCB2_EZ_DATA44 0x400704b0u
#define CYREG_SCB2_EZ_DATA45 0x400704b4u
#define CYREG_SCB2_EZ_DATA46 0x400704b8u
#define CYREG_SCB2_EZ_DATA47 0x400704bcu
#define CYREG_SCB2_EZ_DATA48 0x400704c0u
#define CYREG_SCB2_EZ_DATA49 0x400704c4u
#define CYREG_SCB2_EZ_DATA50 0x400704c8u
#define CYREG_SCB2_EZ_DATA51 0x400704ccu
#define CYREG_SCB2_EZ_DATA52 0x400704d0u
#define CYREG_SCB2_EZ_DATA53 0x400704d4u
#define CYREG_SCB2_EZ_DATA54 0x400704d8u
#define CYREG_SCB2_EZ_DATA55 0x400704dcu
#define CYREG_SCB2_EZ_DATA56 0x400704e0u
#define CYREG_SCB2_EZ_DATA57 0x400704e4u
#define CYREG_SCB2_EZ_DATA58 0x400704e8u
#define CYREG_SCB2_EZ_DATA59 0x400704ecu
#define CYREG_SCB2_EZ_DATA60 0x400704f0u
#define CYREG_SCB2_EZ_DATA61 0x400704f4u
#define CYREG_SCB2_EZ_DATA62 0x400704f8u
#define CYREG_SCB2_EZ_DATA63 0x400704fcu
#define CYREG_SCB2_EZ_DATA64 0x40070500u
#define CYREG_SCB2_EZ_DATA65 0x40070504u
#define CYREG_SCB2_EZ_DATA66 0x40070508u
#define CYREG_SCB2_EZ_DATA67 0x4007050cu
#define CYREG_SCB2_EZ_DATA68 0x40070510u
#define CYREG_SCB2_EZ_DATA69 0x40070514u
#define CYREG_SCB2_EZ_DATA70 0x40070518u
#define CYREG_SCB2_EZ_DATA71 0x4007051cu
#define CYREG_SCB2_EZ_DATA72 0x40070520u
#define CYREG_SCB2_EZ_DATA73 0x40070524u
#define CYREG_SCB2_EZ_DATA74 0x40070528u
#define CYREG_SCB2_EZ_DATA75 0x4007052cu
#define CYREG_SCB2_EZ_DATA76 0x40070530u
#define CYREG_SCB2_EZ_DATA77 0x40070534u
#define CYREG_SCB2_EZ_DATA78 0x40070538u
#define CYREG_SCB2_EZ_DATA79 0x4007053cu
#define CYREG_SCB2_EZ_DATA80 0x40070540u
#define CYREG_SCB2_EZ_DATA81 0x40070544u
#define CYREG_SCB2_EZ_DATA82 0x40070548u
#define CYREG_SCB2_EZ_DATA83 0x4007054cu
#define CYREG_SCB2_EZ_DATA84 0x40070550u
#define CYREG_SCB2_EZ_DATA85 0x40070554u
#define CYREG_SCB2_EZ_DATA86 0x40070558u
#define CYREG_SCB2_EZ_DATA87 0x4007055cu
#define CYREG_SCB2_EZ_DATA88 0x40070560u
#define CYREG_SCB2_EZ_DATA89 0x40070564u
#define CYREG_SCB2_EZ_DATA90 0x40070568u
#define CYREG_SCB2_EZ_DATA91 0x4007056cu
#define CYREG_SCB2_EZ_DATA92 0x40070570u
#define CYREG_SCB2_EZ_DATA93 0x40070574u
#define CYREG_SCB2_EZ_DATA94 0x40070578u
#define CYREG_SCB2_EZ_DATA95 0x4007057cu
#define CYREG_SCB2_EZ_DATA96 0x40070580u
#define CYREG_SCB2_EZ_DATA97 0x40070584u
#define CYREG_SCB2_EZ_DATA98 0x40070588u
#define CYREG_SCB2_EZ_DATA99 0x4007058cu
#define CYREG_SCB2_EZ_DATA100 0x40070590u
#define CYREG_SCB2_EZ_DATA101 0x40070594u
#define CYREG_SCB2_EZ_DATA102 0x40070598u
#define CYREG_SCB2_EZ_DATA103 0x4007059cu
#define CYREG_SCB2_EZ_DATA104 0x400705a0u
#define CYREG_SCB2_EZ_DATA105 0x400705a4u
#define CYREG_SCB2_EZ_DATA106 0x400705a8u
#define CYREG_SCB2_EZ_DATA107 0x400705acu
#define CYREG_SCB2_EZ_DATA108 0x400705b0u
#define CYREG_SCB2_EZ_DATA109 0x400705b4u
#define CYREG_SCB2_EZ_DATA110 0x400705b8u
#define CYREG_SCB2_EZ_DATA111 0x400705bcu
#define CYREG_SCB2_EZ_DATA112 0x400705c0u
#define CYREG_SCB2_EZ_DATA113 0x400705c4u
#define CYREG_SCB2_EZ_DATA114 0x400705c8u
#define CYREG_SCB2_EZ_DATA115 0x400705ccu
#define CYREG_SCB2_EZ_DATA116 0x400705d0u
#define CYREG_SCB2_EZ_DATA117 0x400705d4u
#define CYREG_SCB2_EZ_DATA118 0x400705d8u
#define CYREG_SCB2_EZ_DATA119 0x400705dcu
#define CYREG_SCB2_EZ_DATA120 0x400705e0u
#define CYREG_SCB2_EZ_DATA121 0x400705e4u
#define CYREG_SCB2_EZ_DATA122 0x400705e8u
#define CYREG_SCB2_EZ_DATA123 0x400705ecu
#define CYREG_SCB2_EZ_DATA124 0x400705f0u
#define CYREG_SCB2_EZ_DATA125 0x400705f4u
#define CYREG_SCB2_EZ_DATA126 0x400705f8u
#define CYREG_SCB2_EZ_DATA127 0x400705fcu
#define CYREG_SCB2_EZ_DATA128 0x40070600u
#define CYREG_SCB2_EZ_DATA129 0x40070604u
#define CYREG_SCB2_EZ_DATA130 0x40070608u
#define CYREG_SCB2_EZ_DATA131 0x4007060cu
#define CYREG_SCB2_EZ_DATA132 0x40070610u
#define CYREG_SCB2_EZ_DATA133 0x40070614u
#define CYREG_SCB2_EZ_DATA134 0x40070618u
#define CYREG_SCB2_EZ_DATA135 0x4007061cu
#define CYREG_SCB2_EZ_DATA136 0x40070620u
#define CYREG_SCB2_EZ_DATA137 0x40070624u
#define CYREG_SCB2_EZ_DATA138 0x40070628u
#define CYREG_SCB2_EZ_DATA139 0x4007062cu
#define CYREG_SCB2_EZ_DATA140 0x40070630u
#define CYREG_SCB2_EZ_DATA141 0x40070634u
#define CYREG_SCB2_EZ_DATA142 0x40070638u
#define CYREG_SCB2_EZ_DATA143 0x4007063cu
#define CYREG_SCB2_EZ_DATA144 0x40070640u
#define CYREG_SCB2_EZ_DATA145 0x40070644u
#define CYREG_SCB2_EZ_DATA146 0x40070648u
#define CYREG_SCB2_EZ_DATA147 0x4007064cu
#define CYREG_SCB2_EZ_DATA148 0x40070650u
#define CYREG_SCB2_EZ_DATA149 0x40070654u
#define CYREG_SCB2_EZ_DATA150 0x40070658u
#define CYREG_SCB2_EZ_DATA151 0x4007065cu
#define CYREG_SCB2_EZ_DATA152 0x40070660u
#define CYREG_SCB2_EZ_DATA153 0x40070664u
#define CYREG_SCB2_EZ_DATA154 0x40070668u
#define CYREG_SCB2_EZ_DATA155 0x4007066cu
#define CYREG_SCB2_EZ_DATA156 0x40070670u
#define CYREG_SCB2_EZ_DATA157 0x40070674u
#define CYREG_SCB2_EZ_DATA158 0x40070678u
#define CYREG_SCB2_EZ_DATA159 0x4007067cu
#define CYREG_SCB2_EZ_DATA160 0x40070680u
#define CYREG_SCB2_EZ_DATA161 0x40070684u
#define CYREG_SCB2_EZ_DATA162 0x40070688u
#define CYREG_SCB2_EZ_DATA163 0x4007068cu
#define CYREG_SCB2_EZ_DATA164 0x40070690u
#define CYREG_SCB2_EZ_DATA165 0x40070694u
#define CYREG_SCB2_EZ_DATA166 0x40070698u
#define CYREG_SCB2_EZ_DATA167 0x4007069cu
#define CYREG_SCB2_EZ_DATA168 0x400706a0u
#define CYREG_SCB2_EZ_DATA169 0x400706a4u
#define CYREG_SCB2_EZ_DATA170 0x400706a8u
#define CYREG_SCB2_EZ_DATA171 0x400706acu
#define CYREG_SCB2_EZ_DATA172 0x400706b0u
#define CYREG_SCB2_EZ_DATA173 0x400706b4u
#define CYREG_SCB2_EZ_DATA174 0x400706b8u
#define CYREG_SCB2_EZ_DATA175 0x400706bcu
#define CYREG_SCB2_EZ_DATA176 0x400706c0u
#define CYREG_SCB2_EZ_DATA177 0x400706c4u
#define CYREG_SCB2_EZ_DATA178 0x400706c8u
#define CYREG_SCB2_EZ_DATA179 0x400706ccu
#define CYREG_SCB2_EZ_DATA180 0x400706d0u
#define CYREG_SCB2_EZ_DATA181 0x400706d4u
#define CYREG_SCB2_EZ_DATA182 0x400706d8u
#define CYREG_SCB2_EZ_DATA183 0x400706dcu
#define CYREG_SCB2_EZ_DATA184 0x400706e0u
#define CYREG_SCB2_EZ_DATA185 0x400706e4u
#define CYREG_SCB2_EZ_DATA186 0x400706e8u
#define CYREG_SCB2_EZ_DATA187 0x400706ecu
#define CYREG_SCB2_EZ_DATA188 0x400706f0u
#define CYREG_SCB2_EZ_DATA189 0x400706f4u
#define CYREG_SCB2_EZ_DATA190 0x400706f8u
#define CYREG_SCB2_EZ_DATA191 0x400706fcu
#define CYREG_SCB2_EZ_DATA192 0x40070700u
#define CYREG_SCB2_EZ_DATA193 0x40070704u
#define CYREG_SCB2_EZ_DATA194 0x40070708u
#define CYREG_SCB2_EZ_DATA195 0x4007070cu
#define CYREG_SCB2_EZ_DATA196 0x40070710u
#define CYREG_SCB2_EZ_DATA197 0x40070714u
#define CYREG_SCB2_EZ_DATA198 0x40070718u
#define CYREG_SCB2_EZ_DATA199 0x4007071cu
#define CYREG_SCB2_EZ_DATA200 0x40070720u
#define CYREG_SCB2_EZ_DATA201 0x40070724u
#define CYREG_SCB2_EZ_DATA202 0x40070728u
#define CYREG_SCB2_EZ_DATA203 0x4007072cu
#define CYREG_SCB2_EZ_DATA204 0x40070730u
#define CYREG_SCB2_EZ_DATA205 0x40070734u
#define CYREG_SCB2_EZ_DATA206 0x40070738u
#define CYREG_SCB2_EZ_DATA207 0x4007073cu
#define CYREG_SCB2_EZ_DATA208 0x40070740u
#define CYREG_SCB2_EZ_DATA209 0x40070744u
#define CYREG_SCB2_EZ_DATA210 0x40070748u
#define CYREG_SCB2_EZ_DATA211 0x4007074cu
#define CYREG_SCB2_EZ_DATA212 0x40070750u
#define CYREG_SCB2_EZ_DATA213 0x40070754u
#define CYREG_SCB2_EZ_DATA214 0x40070758u
#define CYREG_SCB2_EZ_DATA215 0x4007075cu
#define CYREG_SCB2_EZ_DATA216 0x40070760u
#define CYREG_SCB2_EZ_DATA217 0x40070764u
#define CYREG_SCB2_EZ_DATA218 0x40070768u
#define CYREG_SCB2_EZ_DATA219 0x4007076cu
#define CYREG_SCB2_EZ_DATA220 0x40070770u
#define CYREG_SCB2_EZ_DATA221 0x40070774u
#define CYREG_SCB2_EZ_DATA222 0x40070778u
#define CYREG_SCB2_EZ_DATA223 0x4007077cu
#define CYREG_SCB2_EZ_DATA224 0x40070780u
#define CYREG_SCB2_EZ_DATA225 0x40070784u
#define CYREG_SCB2_EZ_DATA226 0x40070788u
#define CYREG_SCB2_EZ_DATA227 0x4007078cu
#define CYREG_SCB2_EZ_DATA228 0x40070790u
#define CYREG_SCB2_EZ_DATA229 0x40070794u
#define CYREG_SCB2_EZ_DATA230 0x40070798u
#define CYREG_SCB2_EZ_DATA231 0x4007079cu
#define CYREG_SCB2_EZ_DATA232 0x400707a0u
#define CYREG_SCB2_EZ_DATA233 0x400707a4u
#define CYREG_SCB2_EZ_DATA234 0x400707a8u
#define CYREG_SCB2_EZ_DATA235 0x400707acu
#define CYREG_SCB2_EZ_DATA236 0x400707b0u
#define CYREG_SCB2_EZ_DATA237 0x400707b4u
#define CYREG_SCB2_EZ_DATA238 0x400707b8u
#define CYREG_SCB2_EZ_DATA239 0x400707bcu
#define CYREG_SCB2_EZ_DATA240 0x400707c0u
#define CYREG_SCB2_EZ_DATA241 0x400707c4u
#define CYREG_SCB2_EZ_DATA242 0x400707c8u
#define CYREG_SCB2_EZ_DATA243 0x400707ccu
#define CYREG_SCB2_EZ_DATA244 0x400707d0u
#define CYREG_SCB2_EZ_DATA245 0x400707d4u
#define CYREG_SCB2_EZ_DATA246 0x400707d8u
#define CYREG_SCB2_EZ_DATA247 0x400707dcu
#define CYREG_SCB2_EZ_DATA248 0x400707e0u
#define CYREG_SCB2_EZ_DATA249 0x400707e4u
#define CYREG_SCB2_EZ_DATA250 0x400707e8u
#define CYREG_SCB2_EZ_DATA251 0x400707ecu
#define CYREG_SCB2_EZ_DATA252 0x400707f0u
#define CYREG_SCB2_EZ_DATA253 0x400707f4u
#define CYREG_SCB2_EZ_DATA254 0x400707f8u
#define CYREG_SCB2_EZ_DATA255 0x400707fcu
#define CYREG_SCB2_INTR_CAUSE 0x40070e00u
#define CYREG_SCB2_INTR_I2C_EC 0x40070e80u
#define CYREG_SCB2_INTR_I2C_EC_MASK 0x40070e88u
#define CYREG_SCB2_INTR_I2C_EC_MASKED 0x40070e8cu
#define CYREG_SCB2_INTR_SPI_EC 0x40070ec0u
#define CYREG_SCB2_INTR_SPI_EC_MASK 0x40070ec8u
#define CYREG_SCB2_INTR_SPI_EC_MASKED 0x40070eccu
#define CYREG_SCB2_INTR_M 0x40070f00u
#define CYREG_SCB2_INTR_M_SET 0x40070f04u
#define CYREG_SCB2_INTR_M_MASK 0x40070f08u
#define CYREG_SCB2_INTR_M_MASKED 0x40070f0cu
#define CYREG_SCB2_INTR_S 0x40070f40u
#define CYREG_SCB2_INTR_S_SET 0x40070f44u
#define CYREG_SCB2_INTR_S_MASK 0x40070f48u
#define CYREG_SCB2_INTR_S_MASKED 0x40070f4cu
#define CYREG_SCB2_INTR_TX 0x40070f80u
#define CYREG_SCB2_INTR_TX_SET 0x40070f84u
#define CYREG_SCB2_INTR_TX_MASK 0x40070f88u
#define CYREG_SCB2_INTR_TX_MASKED 0x40070f8cu
#define CYREG_SCB2_INTR_RX 0x40070fc0u
#define CYREG_SCB2_INTR_RX_SET 0x40070fc4u
#define CYREG_SCB2_INTR_RX_MASK 0x40070fc8u
#define CYREG_SCB2_INTR_RX_MASKED 0x40070fccu
#define CYDEV_SCB3_BASE 0x40080000u
#define CYDEV_SCB3_SIZE 0x00010000u
#define CYREG_SCB3_CTRL 0x40080000u
#define CYREG_SCB3_STATUS 0x40080004u
#define CYREG_SCB3_CMD_RESP_CTRL 0x40080008u
#define CYREG_SCB3_CMD_RESP_STATUS 0x4008000cu
#define CYREG_SCB3_SPI_CTRL 0x40080020u
#define CYREG_SCB3_SPI_STATUS 0x40080024u
#define CYREG_SCB3_UART_CTRL 0x40080040u
#define CYREG_SCB3_UART_TX_CTRL 0x40080044u
#define CYREG_SCB3_UART_RX_CTRL 0x40080048u
#define CYREG_SCB3_UART_RX_STATUS 0x4008004cu
#define CYREG_SCB3_UART_FLOW_CTRL 0x40080050u
#define CYREG_SCB3_I2C_CTRL 0x40080060u
#define CYREG_SCB3_I2C_STATUS 0x40080064u
#define CYREG_SCB3_I2C_M_CMD 0x40080068u
#define CYREG_SCB3_I2C_S_CMD 0x4008006cu
#define CYREG_SCB3_I2C_CFG 0x40080070u
#define CYREG_SCB3_TX_CTRL 0x40080200u
#define CYREG_SCB3_TX_FIFO_CTRL 0x40080204u
#define CYREG_SCB3_TX_FIFO_STATUS 0x40080208u
#define CYREG_SCB3_TX_FIFO_WR 0x40080240u
#define CYREG_SCB3_RX_CTRL 0x40080300u
#define CYREG_SCB3_RX_FIFO_CTRL 0x40080304u
#define CYREG_SCB3_RX_FIFO_STATUS 0x40080308u
#define CYREG_SCB3_RX_MATCH 0x40080310u
#define CYREG_SCB3_RX_FIFO_RD 0x40080340u
#define CYREG_SCB3_RX_FIFO_RD_SILENT 0x40080344u
#define CYREG_SCB3_EZ_DATA0 0x40080400u
#define CYREG_SCB3_EZ_DATA1 0x40080404u
#define CYREG_SCB3_EZ_DATA2 0x40080408u
#define CYREG_SCB3_EZ_DATA3 0x4008040cu
#define CYREG_SCB3_EZ_DATA4 0x40080410u
#define CYREG_SCB3_EZ_DATA5 0x40080414u
#define CYREG_SCB3_EZ_DATA6 0x40080418u
#define CYREG_SCB3_EZ_DATA7 0x4008041cu
#define CYREG_SCB3_EZ_DATA8 0x40080420u
#define CYREG_SCB3_EZ_DATA9 0x40080424u
#define CYREG_SCB3_EZ_DATA10 0x40080428u
#define CYREG_SCB3_EZ_DATA11 0x4008042cu
#define CYREG_SCB3_EZ_DATA12 0x40080430u
#define CYREG_SCB3_EZ_DATA13 0x40080434u
#define CYREG_SCB3_EZ_DATA14 0x40080438u
#define CYREG_SCB3_EZ_DATA15 0x4008043cu
#define CYREG_SCB3_EZ_DATA16 0x40080440u
#define CYREG_SCB3_EZ_DATA17 0x40080444u
#define CYREG_SCB3_EZ_DATA18 0x40080448u
#define CYREG_SCB3_EZ_DATA19 0x4008044cu
#define CYREG_SCB3_EZ_DATA20 0x40080450u
#define CYREG_SCB3_EZ_DATA21 0x40080454u
#define CYREG_SCB3_EZ_DATA22 0x40080458u
#define CYREG_SCB3_EZ_DATA23 0x4008045cu
#define CYREG_SCB3_EZ_DATA24 0x40080460u
#define CYREG_SCB3_EZ_DATA25 0x40080464u
#define CYREG_SCB3_EZ_DATA26 0x40080468u
#define CYREG_SCB3_EZ_DATA27 0x4008046cu
#define CYREG_SCB3_EZ_DATA28 0x40080470u
#define CYREG_SCB3_EZ_DATA29 0x40080474u
#define CYREG_SCB3_EZ_DATA30 0x40080478u
#define CYREG_SCB3_EZ_DATA31 0x4008047cu
#define CYREG_SCB3_EZ_DATA32 0x40080480u
#define CYREG_SCB3_EZ_DATA33 0x40080484u
#define CYREG_SCB3_EZ_DATA34 0x40080488u
#define CYREG_SCB3_EZ_DATA35 0x4008048cu
#define CYREG_SCB3_EZ_DATA36 0x40080490u
#define CYREG_SCB3_EZ_DATA37 0x40080494u
#define CYREG_SCB3_EZ_DATA38 0x40080498u
#define CYREG_SCB3_EZ_DATA39 0x4008049cu
#define CYREG_SCB3_EZ_DATA40 0x400804a0u
#define CYREG_SCB3_EZ_DATA41 0x400804a4u
#define CYREG_SCB3_EZ_DATA42 0x400804a8u
#define CYREG_SCB3_EZ_DATA43 0x400804acu
#define CYREG_SCB3_EZ_DATA44 0x400804b0u
#define CYREG_SCB3_EZ_DATA45 0x400804b4u
#define CYREG_SCB3_EZ_DATA46 0x400804b8u
#define CYREG_SCB3_EZ_DATA47 0x400804bcu
#define CYREG_SCB3_EZ_DATA48 0x400804c0u
#define CYREG_SCB3_EZ_DATA49 0x400804c4u
#define CYREG_SCB3_EZ_DATA50 0x400804c8u
#define CYREG_SCB3_EZ_DATA51 0x400804ccu
#define CYREG_SCB3_EZ_DATA52 0x400804d0u
#define CYREG_SCB3_EZ_DATA53 0x400804d4u
#define CYREG_SCB3_EZ_DATA54 0x400804d8u
#define CYREG_SCB3_EZ_DATA55 0x400804dcu
#define CYREG_SCB3_EZ_DATA56 0x400804e0u
#define CYREG_SCB3_EZ_DATA57 0x400804e4u
#define CYREG_SCB3_EZ_DATA58 0x400804e8u
#define CYREG_SCB3_EZ_DATA59 0x400804ecu
#define CYREG_SCB3_EZ_DATA60 0x400804f0u
#define CYREG_SCB3_EZ_DATA61 0x400804f4u
#define CYREG_SCB3_EZ_DATA62 0x400804f8u
#define CYREG_SCB3_EZ_DATA63 0x400804fcu
#define CYREG_SCB3_EZ_DATA64 0x40080500u
#define CYREG_SCB3_EZ_DATA65 0x40080504u
#define CYREG_SCB3_EZ_DATA66 0x40080508u
#define CYREG_SCB3_EZ_DATA67 0x4008050cu
#define CYREG_SCB3_EZ_DATA68 0x40080510u
#define CYREG_SCB3_EZ_DATA69 0x40080514u
#define CYREG_SCB3_EZ_DATA70 0x40080518u
#define CYREG_SCB3_EZ_DATA71 0x4008051cu
#define CYREG_SCB3_EZ_DATA72 0x40080520u
#define CYREG_SCB3_EZ_DATA73 0x40080524u
#define CYREG_SCB3_EZ_DATA74 0x40080528u
#define CYREG_SCB3_EZ_DATA75 0x4008052cu
#define CYREG_SCB3_EZ_DATA76 0x40080530u
#define CYREG_SCB3_EZ_DATA77 0x40080534u
#define CYREG_SCB3_EZ_DATA78 0x40080538u
#define CYREG_SCB3_EZ_DATA79 0x4008053cu
#define CYREG_SCB3_EZ_DATA80 0x40080540u
#define CYREG_SCB3_EZ_DATA81 0x40080544u
#define CYREG_SCB3_EZ_DATA82 0x40080548u
#define CYREG_SCB3_EZ_DATA83 0x4008054cu
#define CYREG_SCB3_EZ_DATA84 0x40080550u
#define CYREG_SCB3_EZ_DATA85 0x40080554u
#define CYREG_SCB3_EZ_DATA86 0x40080558u
#define CYREG_SCB3_EZ_DATA87 0x4008055cu
#define CYREG_SCB3_EZ_DATA88 0x40080560u
#define CYREG_SCB3_EZ_DATA89 0x40080564u
#define CYREG_SCB3_EZ_DATA90 0x40080568u
#define CYREG_SCB3_EZ_DATA91 0x4008056cu
#define CYREG_SCB3_EZ_DATA92 0x40080570u
#define CYREG_SCB3_EZ_DATA93 0x40080574u
#define CYREG_SCB3_EZ_DATA94 0x40080578u
#define CYREG_SCB3_EZ_DATA95 0x4008057cu
#define CYREG_SCB3_EZ_DATA96 0x40080580u
#define CYREG_SCB3_EZ_DATA97 0x40080584u
#define CYREG_SCB3_EZ_DATA98 0x40080588u
#define CYREG_SCB3_EZ_DATA99 0x4008058cu
#define CYREG_SCB3_EZ_DATA100 0x40080590u
#define CYREG_SCB3_EZ_DATA101 0x40080594u
#define CYREG_SCB3_EZ_DATA102 0x40080598u
#define CYREG_SCB3_EZ_DATA103 0x4008059cu
#define CYREG_SCB3_EZ_DATA104 0x400805a0u
#define CYREG_SCB3_EZ_DATA105 0x400805a4u
#define CYREG_SCB3_EZ_DATA106 0x400805a8u
#define CYREG_SCB3_EZ_DATA107 0x400805acu
#define CYREG_SCB3_EZ_DATA108 0x400805b0u
#define CYREG_SCB3_EZ_DATA109 0x400805b4u
#define CYREG_SCB3_EZ_DATA110 0x400805b8u
#define CYREG_SCB3_EZ_DATA111 0x400805bcu
#define CYREG_SCB3_EZ_DATA112 0x400805c0u
#define CYREG_SCB3_EZ_DATA113 0x400805c4u
#define CYREG_SCB3_EZ_DATA114 0x400805c8u
#define CYREG_SCB3_EZ_DATA115 0x400805ccu
#define CYREG_SCB3_EZ_DATA116 0x400805d0u
#define CYREG_SCB3_EZ_DATA117 0x400805d4u
#define CYREG_SCB3_EZ_DATA118 0x400805d8u
#define CYREG_SCB3_EZ_DATA119 0x400805dcu
#define CYREG_SCB3_EZ_DATA120 0x400805e0u
#define CYREG_SCB3_EZ_DATA121 0x400805e4u
#define CYREG_SCB3_EZ_DATA122 0x400805e8u
#define CYREG_SCB3_EZ_DATA123 0x400805ecu
#define CYREG_SCB3_EZ_DATA124 0x400805f0u
#define CYREG_SCB3_EZ_DATA125 0x400805f4u
#define CYREG_SCB3_EZ_DATA126 0x400805f8u
#define CYREG_SCB3_EZ_DATA127 0x400805fcu
#define CYREG_SCB3_EZ_DATA128 0x40080600u
#define CYREG_SCB3_EZ_DATA129 0x40080604u
#define CYREG_SCB3_EZ_DATA130 0x40080608u
#define CYREG_SCB3_EZ_DATA131 0x4008060cu
#define CYREG_SCB3_EZ_DATA132 0x40080610u
#define CYREG_SCB3_EZ_DATA133 0x40080614u
#define CYREG_SCB3_EZ_DATA134 0x40080618u
#define CYREG_SCB3_EZ_DATA135 0x4008061cu
#define CYREG_SCB3_EZ_DATA136 0x40080620u
#define CYREG_SCB3_EZ_DATA137 0x40080624u
#define CYREG_SCB3_EZ_DATA138 0x40080628u
#define CYREG_SCB3_EZ_DATA139 0x4008062cu
#define CYREG_SCB3_EZ_DATA140 0x40080630u
#define CYREG_SCB3_EZ_DATA141 0x40080634u
#define CYREG_SCB3_EZ_DATA142 0x40080638u
#define CYREG_SCB3_EZ_DATA143 0x4008063cu
#define CYREG_SCB3_EZ_DATA144 0x40080640u
#define CYREG_SCB3_EZ_DATA145 0x40080644u
#define CYREG_SCB3_EZ_DATA146 0x40080648u
#define CYREG_SCB3_EZ_DATA147 0x4008064cu
#define CYREG_SCB3_EZ_DATA148 0x40080650u
#define CYREG_SCB3_EZ_DATA149 0x40080654u
#define CYREG_SCB3_EZ_DATA150 0x40080658u
#define CYREG_SCB3_EZ_DATA151 0x4008065cu
#define CYREG_SCB3_EZ_DATA152 0x40080660u
#define CYREG_SCB3_EZ_DATA153 0x40080664u
#define CYREG_SCB3_EZ_DATA154 0x40080668u
#define CYREG_SCB3_EZ_DATA155 0x4008066cu
#define CYREG_SCB3_EZ_DATA156 0x40080670u
#define CYREG_SCB3_EZ_DATA157 0x40080674u
#define CYREG_SCB3_EZ_DATA158 0x40080678u
#define CYREG_SCB3_EZ_DATA159 0x4008067cu
#define CYREG_SCB3_EZ_DATA160 0x40080680u
#define CYREG_SCB3_EZ_DATA161 0x40080684u
#define CYREG_SCB3_EZ_DATA162 0x40080688u
#define CYREG_SCB3_EZ_DATA163 0x4008068cu
#define CYREG_SCB3_EZ_DATA164 0x40080690u
#define CYREG_SCB3_EZ_DATA165 0x40080694u
#define CYREG_SCB3_EZ_DATA166 0x40080698u
#define CYREG_SCB3_EZ_DATA167 0x4008069cu
#define CYREG_SCB3_EZ_DATA168 0x400806a0u
#define CYREG_SCB3_EZ_DATA169 0x400806a4u
#define CYREG_SCB3_EZ_DATA170 0x400806a8u
#define CYREG_SCB3_EZ_DATA171 0x400806acu
#define CYREG_SCB3_EZ_DATA172 0x400806b0u
#define CYREG_SCB3_EZ_DATA173 0x400806b4u
#define CYREG_SCB3_EZ_DATA174 0x400806b8u
#define CYREG_SCB3_EZ_DATA175 0x400806bcu
#define CYREG_SCB3_EZ_DATA176 0x400806c0u
#define CYREG_SCB3_EZ_DATA177 0x400806c4u
#define CYREG_SCB3_EZ_DATA178 0x400806c8u
#define CYREG_SCB3_EZ_DATA179 0x400806ccu
#define CYREG_SCB3_EZ_DATA180 0x400806d0u
#define CYREG_SCB3_EZ_DATA181 0x400806d4u
#define CYREG_SCB3_EZ_DATA182 0x400806d8u
#define CYREG_SCB3_EZ_DATA183 0x400806dcu
#define CYREG_SCB3_EZ_DATA184 0x400806e0u
#define CYREG_SCB3_EZ_DATA185 0x400806e4u
#define CYREG_SCB3_EZ_DATA186 0x400806e8u
#define CYREG_SCB3_EZ_DATA187 0x400806ecu
#define CYREG_SCB3_EZ_DATA188 0x400806f0u
#define CYREG_SCB3_EZ_DATA189 0x400806f4u
#define CYREG_SCB3_EZ_DATA190 0x400806f8u
#define CYREG_SCB3_EZ_DATA191 0x400806fcu
#define CYREG_SCB3_EZ_DATA192 0x40080700u
#define CYREG_SCB3_EZ_DATA193 0x40080704u
#define CYREG_SCB3_EZ_DATA194 0x40080708u
#define CYREG_SCB3_EZ_DATA195 0x4008070cu
#define CYREG_SCB3_EZ_DATA196 0x40080710u
#define CYREG_SCB3_EZ_DATA197 0x40080714u
#define CYREG_SCB3_EZ_DATA198 0x40080718u
#define CYREG_SCB3_EZ_DATA199 0x4008071cu
#define CYREG_SCB3_EZ_DATA200 0x40080720u
#define CYREG_SCB3_EZ_DATA201 0x40080724u
#define CYREG_SCB3_EZ_DATA202 0x40080728u
#define CYREG_SCB3_EZ_DATA203 0x4008072cu
#define CYREG_SCB3_EZ_DATA204 0x40080730u
#define CYREG_SCB3_EZ_DATA205 0x40080734u
#define CYREG_SCB3_EZ_DATA206 0x40080738u
#define CYREG_SCB3_EZ_DATA207 0x4008073cu
#define CYREG_SCB3_EZ_DATA208 0x40080740u
#define CYREG_SCB3_EZ_DATA209 0x40080744u
#define CYREG_SCB3_EZ_DATA210 0x40080748u
#define CYREG_SCB3_EZ_DATA211 0x4008074cu
#define CYREG_SCB3_EZ_DATA212 0x40080750u
#define CYREG_SCB3_EZ_DATA213 0x40080754u
#define CYREG_SCB3_EZ_DATA214 0x40080758u
#define CYREG_SCB3_EZ_DATA215 0x4008075cu
#define CYREG_SCB3_EZ_DATA216 0x40080760u
#define CYREG_SCB3_EZ_DATA217 0x40080764u
#define CYREG_SCB3_EZ_DATA218 0x40080768u
#define CYREG_SCB3_EZ_DATA219 0x4008076cu
#define CYREG_SCB3_EZ_DATA220 0x40080770u
#define CYREG_SCB3_EZ_DATA221 0x40080774u
#define CYREG_SCB3_EZ_DATA222 0x40080778u
#define CYREG_SCB3_EZ_DATA223 0x4008077cu
#define CYREG_SCB3_EZ_DATA224 0x40080780u
#define CYREG_SCB3_EZ_DATA225 0x40080784u
#define CYREG_SCB3_EZ_DATA226 0x40080788u
#define CYREG_SCB3_EZ_DATA227 0x4008078cu
#define CYREG_SCB3_EZ_DATA228 0x40080790u
#define CYREG_SCB3_EZ_DATA229 0x40080794u
#define CYREG_SCB3_EZ_DATA230 0x40080798u
#define CYREG_SCB3_EZ_DATA231 0x4008079cu
#define CYREG_SCB3_EZ_DATA232 0x400807a0u
#define CYREG_SCB3_EZ_DATA233 0x400807a4u
#define CYREG_SCB3_EZ_DATA234 0x400807a8u
#define CYREG_SCB3_EZ_DATA235 0x400807acu
#define CYREG_SCB3_EZ_DATA236 0x400807b0u
#define CYREG_SCB3_EZ_DATA237 0x400807b4u
#define CYREG_SCB3_EZ_DATA238 0x400807b8u
#define CYREG_SCB3_EZ_DATA239 0x400807bcu
#define CYREG_SCB3_EZ_DATA240 0x400807c0u
#define CYREG_SCB3_EZ_DATA241 0x400807c4u
#define CYREG_SCB3_EZ_DATA242 0x400807c8u
#define CYREG_SCB3_EZ_DATA243 0x400807ccu
#define CYREG_SCB3_EZ_DATA244 0x400807d0u
#define CYREG_SCB3_EZ_DATA245 0x400807d4u
#define CYREG_SCB3_EZ_DATA246 0x400807d8u
#define CYREG_SCB3_EZ_DATA247 0x400807dcu
#define CYREG_SCB3_EZ_DATA248 0x400807e0u
#define CYREG_SCB3_EZ_DATA249 0x400807e4u
#define CYREG_SCB3_EZ_DATA250 0x400807e8u
#define CYREG_SCB3_EZ_DATA251 0x400807ecu
#define CYREG_SCB3_EZ_DATA252 0x400807f0u
#define CYREG_SCB3_EZ_DATA253 0x400807f4u
#define CYREG_SCB3_EZ_DATA254 0x400807f8u
#define CYREG_SCB3_EZ_DATA255 0x400807fcu
#define CYREG_SCB3_INTR_CAUSE 0x40080e00u
#define CYREG_SCB3_INTR_I2C_EC 0x40080e80u
#define CYREG_SCB3_INTR_I2C_EC_MASK 0x40080e88u
#define CYREG_SCB3_INTR_I2C_EC_MASKED 0x40080e8cu
#define CYREG_SCB3_INTR_SPI_EC 0x40080ec0u
#define CYREG_SCB3_INTR_SPI_EC_MASK 0x40080ec8u
#define CYREG_SCB3_INTR_SPI_EC_MASKED 0x40080eccu
#define CYREG_SCB3_INTR_M 0x40080f00u
#define CYREG_SCB3_INTR_M_SET 0x40080f04u
#define CYREG_SCB3_INTR_M_MASK 0x40080f08u
#define CYREG_SCB3_INTR_M_MASKED 0x40080f0cu
#define CYREG_SCB3_INTR_S 0x40080f40u
#define CYREG_SCB3_INTR_S_SET 0x40080f44u
#define CYREG_SCB3_INTR_S_MASK 0x40080f48u
#define CYREG_SCB3_INTR_S_MASKED 0x40080f4cu
#define CYREG_SCB3_INTR_TX 0x40080f80u
#define CYREG_SCB3_INTR_TX_SET 0x40080f84u
#define CYREG_SCB3_INTR_TX_MASK 0x40080f88u
#define CYREG_SCB3_INTR_TX_MASKED 0x40080f8cu
#define CYREG_SCB3_INTR_RX 0x40080fc0u
#define CYREG_SCB3_INTR_RX_SET 0x40080fc4u
#define CYREG_SCB3_INTR_RX_MASK 0x40080fc8u
#define CYREG_SCB3_INTR_RX_MASKED 0x40080fccu
#define CYDEV_TCPWM_BASE 0x40090000u
#define CYDEV_TCPWM_SIZE 0x00010000u
#define CYREG_TCPWM_CTRL 0x40090000u
#define CYFLD_TCPWM_COUNTER_ENABLED__OFFSET 0x00000000u
#define CYFLD_TCPWM_COUNTER_ENABLED__SIZE 0x00000004u
#define CYREG_TCPWM_CMD 0x40090008u
#define CYFLD_TCPWM_COUNTER_CAPTURE__OFFSET 0x00000000u
#define CYFLD_TCPWM_COUNTER_CAPTURE__SIZE 0x00000004u
#define CYFLD_TCPWM_COUNTER_RELOAD__OFFSET 0x00000008u
#define CYFLD_TCPWM_COUNTER_RELOAD__SIZE 0x00000004u
#define CYFLD_TCPWM_COUNTER_STOP__OFFSET 0x00000010u
#define CYFLD_TCPWM_COUNTER_STOP__SIZE 0x00000004u
#define CYFLD_TCPWM_COUNTER_START__OFFSET 0x00000018u
#define CYFLD_TCPWM_COUNTER_START__SIZE 0x00000004u
#define CYREG_TCPWM_INTR_CAUSE 0x4009000cu
#define CYFLD_TCPWM_COUNTER_INT__OFFSET 0x00000000u
#define CYFLD_TCPWM_COUNTER_INT__SIZE 0x00000004u
#define CYDEV_TCPWM_CNT0_BASE 0x40090100u
#define CYDEV_TCPWM_CNT0_SIZE 0x00000040u
#define CYREG_TCPWM_CNT0_CTRL 0x40090100u
#define CYFLD_TCPWM_CNT_AUTO_RELOAD_CC__OFFSET 0x00000000u
#define CYFLD_TCPWM_CNT_AUTO_RELOAD_CC__SIZE 0x00000001u
#define CYFLD_TCPWM_CNT_AUTO_RELOAD_PERIOD__OFFSET 0x00000001u
#define CYFLD_TCPWM_CNT_AUTO_RELOAD_PERIOD__SIZE 0x00000001u
#define CYFLD_TCPWM_CNT_PWM_SYNC_KILL__OFFSET 0x00000002u
#define CYFLD_TCPWM_CNT_PWM_SYNC_KILL__SIZE 0x00000001u
#define CYFLD_TCPWM_CNT_PWM_STOP_ON_KILL__OFFSET 0x00000003u
#define CYFLD_TCPWM_CNT_PWM_STOP_ON_KILL__SIZE 0x00000001u
#define CYFLD_TCPWM_CNT_GENERIC__OFFSET 0x00000008u
#define CYFLD_TCPWM_CNT_GENERIC__SIZE 0x00000008u
#define CYVAL_TCPWM_CNT_GENERIC_DIVBY1 0x00000000u
#define CYVAL_TCPWM_CNT_GENERIC_DIVBY2 0x00000001u
#define CYVAL_TCPWM_CNT_GENERIC_DIVBY4 0x00000002u
#define CYVAL_TCPWM_CNT_GENERIC_DIVBY8 0x00000003u
#define CYVAL_TCPWM_CNT_GENERIC_DIVBY16 0x00000004u
#define CYVAL_TCPWM_CNT_GENERIC_DIVBY32 0x00000005u
#define CYVAL_TCPWM_CNT_GENERIC_DIVBY64 0x00000006u
#define CYVAL_TCPWM_CNT_GENERIC_DIVBY128 0x00000007u
#define CYFLD_TCPWM_CNT_UP_DOWN_MODE__OFFSET 0x00000010u
#define CYFLD_TCPWM_CNT_UP_DOWN_MODE__SIZE 0x00000002u
#define CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_UP 0x00000000u
#define CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_DOWN 0x00000001u
#define CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_UPDN1 0x00000002u
#define CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_UPDN2 0x00000003u
#define CYFLD_TCPWM_CNT_ONE_SHOT__OFFSET 0x00000012u
#define CYFLD_TCPWM_CNT_ONE_SHOT__SIZE 0x00000001u
#define CYFLD_TCPWM_CNT_QUADRATURE_MODE__OFFSET 0x00000014u
#define CYFLD_TCPWM_CNT_QUADRATURE_MODE__SIZE 0x00000002u
#define CYVAL_TCPWM_CNT_QUADRATURE_MODE_X1 0x00000000u
#define CYVAL_TCPWM_CNT_QUADRATURE_MODE_X2 0x00000001u
#define CYVAL_TCPWM_CNT_QUADRATURE_MODE_X4 0x00000002u
#define CYVAL_TCPWM_CNT_QUADRATURE_MODE_INV_OUT 0x00000001u
#define CYVAL_TCPWM_CNT_QUADRATURE_MODE_INV_COMPL_OUT 0x00000002u
#define CYFLD_TCPWM_CNT_MODE__OFFSET 0x00000018u
#define CYFLD_TCPWM_CNT_MODE__SIZE 0x00000003u
#define CYVAL_TCPWM_CNT_MODE_TIMER 0x00000000u
#define CYVAL_TCPWM_CNT_MODE_CAPTURE 0x00000002u
#define CYVAL_TCPWM_CNT_MODE_QUAD 0x00000003u
#define CYVAL_TCPWM_CNT_MODE_PWM 0x00000004u
#define CYVAL_TCPWM_CNT_MODE_PWM_DT 0x00000005u
#define CYVAL_TCPWM_CNT_MODE_PWM_PR 0x00000006u
#define CYREG_TCPWM_CNT0_STATUS 0x40090104u
#define CYFLD_TCPWM_CNT_DOWN__OFFSET 0x00000000u
#define CYFLD_TCPWM_CNT_DOWN__SIZE 0x00000001u
#define CYFLD_TCPWM_CNT_RUNNING__OFFSET 0x0000001fu
#define CYFLD_TCPWM_CNT_RUNNING__SIZE 0x00000001u
#define CYREG_TCPWM_CNT0_COUNTER 0x40090108u
#define CYFLD_TCPWM_CNT_COUNTER__OFFSET 0x00000000u
#define CYFLD_TCPWM_CNT_COUNTER__SIZE 0x00000010u
#define CYREG_TCPWM_CNT0_CC 0x4009010cu
#define CYFLD_TCPWM_CNT_CC__OFFSET 0x00000000u
#define CYFLD_TCPWM_CNT_CC__SIZE 0x00000010u
#define CYREG_TCPWM_CNT0_CC_BUFF 0x40090110u
#define CYREG_TCPWM_CNT0_PERIOD 0x40090114u
#define CYFLD_TCPWM_CNT_PERIOD__OFFSET 0x00000000u
#define CYFLD_TCPWM_CNT_PERIOD__SIZE 0x00000010u
#define CYREG_TCPWM_CNT0_PERIOD_BUFF 0x40090118u
#define CYREG_TCPWM_CNT0_TR_CTRL0 0x40090120u
#define CYFLD_TCPWM_CNT_CAPTURE_SEL__OFFSET 0x00000000u
#define CYFLD_TCPWM_CNT_CAPTURE_SEL__SIZE 0x00000004u
#define CYFLD_TCPWM_CNT_COUNT_SEL__OFFSET 0x00000004u
#define CYFLD_TCPWM_CNT_COUNT_SEL__SIZE 0x00000004u
#define CYFLD_TCPWM_CNT_RELOAD_SEL__OFFSET 0x00000008u
#define CYFLD_TCPWM_CNT_RELOAD_SEL__SIZE 0x00000004u
#define CYFLD_TCPWM_CNT_STOP_SEL__OFFSET 0x0000000cu
#define CYFLD_TCPWM_CNT_STOP_SEL__SIZE 0x00000004u
#define CYFLD_TCPWM_CNT_START_SEL__OFFSET 0x00000010u
#define CYFLD_TCPWM_CNT_START_SEL__SIZE 0x00000004u
#define CYREG_TCPWM_CNT0_TR_CTRL1 0x40090124u
#define CYFLD_TCPWM_CNT_CAPTURE_EDGE__OFFSET 0x00000000u
#define CYFLD_TCPWM_CNT_CAPTURE_EDGE__SIZE 0x00000002u
#define CYVAL_TCPWM_CNT_CAPTURE_EDGE_RISING_EDGE 0x00000000u
#define CYVAL_TCPWM_CNT_CAPTURE_EDGE_FALLING_EDGE 0x00000001u
#define CYVAL_TCPWM_CNT_CAPTURE_EDGE_BOTH_EDGES 0x00000002u
#define CYVAL_TCPWM_CNT_CAPTURE_EDGE_NO_EDGE_DET 0x00000003u
#define CYFLD_TCPWM_CNT_COUNT_EDGE__OFFSET 0x00000002u
#define CYFLD_TCPWM_CNT_COUNT_EDGE__SIZE 0x00000002u
#define CYVAL_TCPWM_CNT_COUNT_EDGE_RISING_EDGE 0x00000000u
#define CYVAL_TCPWM_CNT_COUNT_EDGE_FALLING_EDGE 0x00000001u
#define CYVAL_TCPWM_CNT_COUNT_EDGE_BOTH_EDGES 0x00000002u
#define CYVAL_TCPWM_CNT_COUNT_EDGE_NO_EDGE_DET 0x00000003u
#define CYFLD_TCPWM_CNT_RELOAD_EDGE__OFFSET 0x00000004u
#define CYFLD_TCPWM_CNT_RELOAD_EDGE__SIZE 0x00000002u
#define CYVAL_TCPWM_CNT_RELOAD_EDGE_RISING_EDGE 0x00000000u
#define CYVAL_TCPWM_CNT_RELOAD_EDGE_FALLING_EDGE 0x00000001u
#define CYVAL_TCPWM_CNT_RELOAD_EDGE_BOTH_EDGES 0x00000002u
#define CYVAL_TCPWM_CNT_RELOAD_EDGE_NO_EDGE_DET 0x00000003u
#define CYFLD_TCPWM_CNT_STOP_EDGE__OFFSET 0x00000006u
#define CYFLD_TCPWM_CNT_STOP_EDGE__SIZE 0x00000002u
#define CYVAL_TCPWM_CNT_STOP_EDGE_RISING_EDGE 0x00000000u
#define CYVAL_TCPWM_CNT_STOP_EDGE_FALLING_EDGE 0x00000001u
#define CYVAL_TCPWM_CNT_STOP_EDGE_BOTH_EDGES 0x00000002u
#define CYVAL_TCPWM_CNT_STOP_EDGE_NO_EDGE_DET 0x00000003u
#define CYFLD_TCPWM_CNT_START_EDGE__OFFSET 0x00000008u
#define CYFLD_TCPWM_CNT_START_EDGE__SIZE 0x00000002u
#define CYVAL_TCPWM_CNT_START_EDGE_RISING_EDGE 0x00000000u
#define CYVAL_TCPWM_CNT_START_EDGE_FALLING_EDGE 0x00000001u
#define CYVAL_TCPWM_CNT_START_EDGE_BOTH_EDGES 0x00000002u
#define CYVAL_TCPWM_CNT_START_EDGE_NO_EDGE_DET 0x00000003u
#define CYREG_TCPWM_CNT0_TR_CTRL2 0x40090128u
#define CYFLD_TCPWM_CNT_CC_MATCH_MODE__OFFSET 0x00000000u
#define CYFLD_TCPWM_CNT_CC_MATCH_MODE__SIZE 0x00000002u
#define CYVAL_TCPWM_CNT_CC_MATCH_MODE_SET 0x00000000u
#define CYVAL_TCPWM_CNT_CC_MATCH_MODE_CLEAR 0x00000001u
#define CYVAL_TCPWM_CNT_CC_MATCH_MODE_INVERT 0x00000002u
#define CYVAL_TCPWM_CNT_CC_MATCH_MODE_NO_CHANGE 0x00000003u
#define CYFLD_TCPWM_CNT_OVERFLOW_MODE__OFFSET 0x00000002u
#define CYFLD_TCPWM_CNT_OVERFLOW_MODE__SIZE 0x00000002u
#define CYVAL_TCPWM_CNT_OVERFLOW_MODE_SET 0x00000000u
#define CYVAL_TCPWM_CNT_OVERFLOW_MODE_CLEAR 0x00000001u
#define CYVAL_TCPWM_CNT_OVERFLOW_MODE_INVERT 0x00000002u
#define CYVAL_TCPWM_CNT_OVERFLOW_MODE_NO_CHANGE 0x00000003u
#define CYFLD_TCPWM_CNT_UNDERFLOW_MODE__OFFSET 0x00000004u
#define CYFLD_TCPWM_CNT_UNDERFLOW_MODE__SIZE 0x00000002u
#define CYVAL_TCPWM_CNT_UNDERFLOW_MODE_SET 0x00000000u
#define CYVAL_TCPWM_CNT_UNDERFLOW_MODE_CLEAR 0x00000001u
#define CYVAL_TCPWM_CNT_UNDERFLOW_MODE_INVERT 0x00000002u
#define CYVAL_TCPWM_CNT_UNDERFLOW_MODE_NO_CHANGE 0x00000003u
#define CYREG_TCPWM_CNT0_INTR 0x40090130u
#define CYFLD_TCPWM_CNT_TC__OFFSET 0x00000000u
#define CYFLD_TCPWM_CNT_TC__SIZE 0x00000001u
#define CYFLD_TCPWM_CNT_CC_MATCH__OFFSET 0x00000001u
#define CYFLD_TCPWM_CNT_CC_MATCH__SIZE 0x00000001u
#define CYREG_TCPWM_CNT0_INTR_SET 0x40090134u
#define CYREG_TCPWM_CNT0_INTR_MASK 0x40090138u
#define CYREG_TCPWM_CNT0_INTR_MASKED 0x4009013cu
#define CYDEV_TCPWM_CNT1_BASE 0x40090140u
#define CYDEV_TCPWM_CNT1_SIZE 0x00000040u
#define CYREG_TCPWM_CNT1_CTRL 0x40090140u
#define CYREG_TCPWM_CNT1_STATUS 0x40090144u
#define CYREG_TCPWM_CNT1_COUNTER 0x40090148u
#define CYREG_TCPWM_CNT1_CC 0x4009014cu
#define CYREG_TCPWM_CNT1_CC_BUFF 0x40090150u
#define CYREG_TCPWM_CNT1_PERIOD 0x40090154u
#define CYREG_TCPWM_CNT1_PERIOD_BUFF 0x40090158u
#define CYREG_TCPWM_CNT1_TR_CTRL0 0x40090160u
#define CYREG_TCPWM_CNT1_TR_CTRL1 0x40090164u
#define CYREG_TCPWM_CNT1_TR_CTRL2 0x40090168u
#define CYREG_TCPWM_CNT1_INTR 0x40090170u
#define CYREG_TCPWM_CNT1_INTR_SET 0x40090174u
#define CYREG_TCPWM_CNT1_INTR_MASK 0x40090178u
#define CYREG_TCPWM_CNT1_INTR_MASKED 0x4009017cu
#define CYDEV_TCPWM_CNT2_BASE 0x40090180u
#define CYDEV_TCPWM_CNT2_SIZE 0x00000040u
#define CYREG_TCPWM_CNT2_CTRL 0x40090180u
#define CYREG_TCPWM_CNT2_STATUS 0x40090184u
#define CYREG_TCPWM_CNT2_COUNTER 0x40090188u
#define CYREG_TCPWM_CNT2_CC 0x4009018cu
#define CYREG_TCPWM_CNT2_CC_BUFF 0x40090190u
#define CYREG_TCPWM_CNT2_PERIOD 0x40090194u
#define CYREG_TCPWM_CNT2_PERIOD_BUFF 0x40090198u
#define CYREG_TCPWM_CNT2_TR_CTRL0 0x400901a0u
#define CYREG_TCPWM_CNT2_TR_CTRL1 0x400901a4u
#define CYREG_TCPWM_CNT2_TR_CTRL2 0x400901a8u
#define CYREG_TCPWM_CNT2_INTR 0x400901b0u
#define CYREG_TCPWM_CNT2_INTR_SET 0x400901b4u
#define CYREG_TCPWM_CNT2_INTR_MASK 0x400901b8u
#define CYREG_TCPWM_CNT2_INTR_MASKED 0x400901bcu
#define CYDEV_TCPWM_CNT3_BASE 0x400901c0u
#define CYDEV_TCPWM_CNT3_SIZE 0x00000040u
#define CYREG_TCPWM_CNT3_CTRL 0x400901c0u
#define CYREG_TCPWM_CNT3_STATUS 0x400901c4u
#define CYREG_TCPWM_CNT3_COUNTER 0x400901c8u
#define CYREG_TCPWM_CNT3_CC 0x400901ccu
#define CYREG_TCPWM_CNT3_CC_BUFF 0x400901d0u
#define CYREG_TCPWM_CNT3_PERIOD 0x400901d4u
#define CYREG_TCPWM_CNT3_PERIOD_BUFF 0x400901d8u
#define CYREG_TCPWM_CNT3_TR_CTRL0 0x400901e0u
#define CYREG_TCPWM_CNT3_TR_CTRL1 0x400901e4u
#define CYREG_TCPWM_CNT3_TR_CTRL2 0x400901e8u
#define CYREG_TCPWM_CNT3_INTR 0x400901f0u
#define CYREG_TCPWM_CNT3_INTR_SET 0x400901f4u
#define CYREG_TCPWM_CNT3_INTR_MASK 0x400901f8u
#define CYREG_TCPWM_CNT3_INTR_MASKED 0x400901fcu
#define CYDEV_USBPD_BASE 0x400a0000u
#define CYDEV_USBPD_SIZE 0x00010000u
#define CYREG_USBPD_CTRL 0x400a0000u
#define CYFLD_USBPD_TX_BYPASS_EN__OFFSET 0x00000000u
#define CYFLD_USBPD_TX_BYPASS_EN__SIZE 0x00000001u
#define CYFLD_USBPD_RX_BYPASS_EN__OFFSET 0x00000001u
#define CYFLD_USBPD_RX_BYPASS_EN__SIZE 0x00000002u
#define CYVAL_USBPD_RX_BYPASS_EN_NO_BYPASS 0x00000000u
#define CYVAL_USBPD_RX_BYPASS_EN_RX_SOP_ALLIGN 0x00000001u
#define CYVAL_USBPD_RX_BYPASS_EN_NO_RX_SOP_ALLGN 0x00000002u
#define CYVAL_USBPD_RX_BYPASS_EN_RSVD_BYPASS 0x00000003u
#define CYFLD_USBPD_HPD_DIRECTION__OFFSET 0x00000003u
#define CYFLD_USBPD_HPD_DIRECTION__SIZE 0x00000001u
#define CYFLD_USBPD_HPD_ENABLED__OFFSET 0x0000001du
#define CYFLD_USBPD_HPD_ENABLED__SIZE 0x00000001u
#define CYFLD_USBPD_HPDT_ENABLED__OFFSET 0x0000001eu
#define CYFLD_USBPD_HPDT_ENABLED__SIZE 0x00000001u
#define CYFLD_USBPD_IP_ENABLED__OFFSET 0x0000001fu
#define CYFLD_USBPD_IP_ENABLED__SIZE 0x00000001u
#define CYREG_USBPD_HEADER_INFO 0x400a0004u
#define CYFLD_USBPD_EN_RX_EXTENDED_DATA__OFFSET 0x00000000u
#define CYFLD_USBPD_EN_RX_EXTENDED_DATA__SIZE 0x00000001u
#define CYFLD_USBPD_EN_TX_EXTENDED_DATA__OFFSET 0x00000001u
#define CYFLD_USBPD_EN_TX_EXTENDED_DATA__SIZE 0x00000001u
#define CYFLD_USBPD_EXTENDED_DATA_BIT_LOCATION__OFFSET 0x00000008u
#define CYFLD_USBPD_EXTENDED_DATA_BIT_LOCATION__SIZE 0x00000004u
#define CYFLD_USBPD_EXTENDED_DATA_BYTE_FIRST_BIT_LOCATION__OFFSET 0x0000000cu
#define CYFLD_USBPD_EXTENDED_DATA_BYTE_FIRST_BIT_LOCATION__SIZE 0x00000005u
#define CYFLD_USBPD_EXTENDED_DATA_BYTE_LAST_BIT_LOCATION__OFFSET 0x00000011u
#define CYFLD_USBPD_EXTENDED_DATA_BYTE_LAST_BIT_LOCATION__SIZE 0x00000005u
#define CYFLD_USBPD_CHUNK_BIT_LOCATION__OFFSET 0x00000016u
#define CYFLD_USBPD_CHUNK_BIT_LOCATION__SIZE 0x00000004u
#define CYREG_USBPD_TX_HEADER 0x400a000cu
#define CYFLD_USBPD_TX_HEADER__OFFSET 0x00000000u
#define CYFLD_USBPD_TX_HEADER__SIZE 0x00000020u
#define CYREG_USBPD_TX_MEM_DATA0 0x400a0010u
#define CYFLD_USBPD_DATA__OFFSET 0x00000000u
#define CYFLD_USBPD_DATA__SIZE 0x00000020u
#define CYREG_USBPD_TX_MEM_DATA1 0x400a0014u
#define CYREG_USBPD_TX_MEM_DATA2 0x400a0018u
#define CYREG_USBPD_TX_MEM_DATA3 0x400a001cu
#define CYREG_USBPD_TX_MEM_DATA4 0x400a0020u
#define CYREG_USBPD_TX_MEM_DATA5 0x400a0024u
#define CYREG_USBPD_TX_MEM_DATA6 0x400a0028u
#define CYREG_USBPD_TX_MEM_DATA7 0x400a002cu
#define CYREG_USBPD_TX_MEM_DATA8 0x400a0030u
#define CYREG_USBPD_TX_MEM_DATA9 0x400a0034u
#define CYREG_USBPD_TX_MEM_DATA10 0x400a0038u
#define CYREG_USBPD_TX_MEM_DATA11 0x400a003cu
#define CYREG_USBPD_TX_MEM_DATA12 0x400a0040u
#define CYREG_USBPD_TX_MEM_DATA13 0x400a0044u
#define CYREG_USBPD_TX_MEM_DATA14 0x400a0048u
#define CYREG_USBPD_TX_MEM_DATA15 0x400a004cu
#define CYREG_USBPD_RX_HEADER 0x400a005cu
#define CYFLD_USBPD_RX_HEADER__OFFSET 0x00000000u
#define CYFLD_USBPD_RX_HEADER__SIZE 0x00000020u
#define CYREG_USBPD_RX_MEM_DATA0 0x400a0060u
#define CYREG_USBPD_RX_MEM_DATA1 0x400a0064u
#define CYREG_USBPD_RX_MEM_DATA2 0x400a0068u
#define CYREG_USBPD_RX_MEM_DATA3 0x400a006cu
#define CYREG_USBPD_RX_MEM_DATA4 0x400a0070u
#define CYREG_USBPD_RX_MEM_DATA5 0x400a0074u
#define CYREG_USBPD_RX_MEM_DATA6 0x400a0078u
#define CYREG_USBPD_RX_MEM_DATA7 0x400a007cu
#define CYREG_USBPD_RX_MEM_DATA8 0x400a0080u
#define CYREG_USBPD_RX_MEM_DATA9 0x400a0084u
#define CYREG_USBPD_RX_MEM_DATA10 0x400a0088u
#define CYREG_USBPD_RX_MEM_DATA11 0x400a008cu
#define CYREG_USBPD_RX_MEM_DATA12 0x400a0090u
#define CYREG_USBPD_RX_MEM_DATA13 0x400a0094u
#define CYREG_USBPD_RX_MEM_DATA14 0x400a0098u
#define CYREG_USBPD_RX_MEM_DATA15 0x400a009cu
#define CYREG_USBPD_SRAM_PTR 0x400a00a0u
#define CYFLD_USBPD_TX_FUNC_RD_PTR__OFFSET 0x00000000u
#define CYFLD_USBPD_TX_FUNC_RD_PTR__SIZE 0x00000005u
#define CYFLD_USBPD_RX_FUNC_WR_PTR__OFFSET 0x00000008u
#define CYFLD_USBPD_RX_FUNC_WR_PTR__SIZE 0x00000005u
#define CYREG_USBPD_STATUS 0x400a00a4u
#define CYFLD_USBPD_RX_BUSY__OFFSET 0x00000000u
#define CYFLD_USBPD_RX_BUSY__SIZE 0x00000001u
#define CYFLD_USBPD_TX_BUSY__OFFSET 0x00000001u
#define CYFLD_USBPD_TX_BUSY__SIZE 0x00000001u
#define CYFLD_USBPD_CC_DATA_VALID__OFFSET 0x00000002u
#define CYFLD_USBPD_CC_DATA_VALID__SIZE 0x00000001u
#define CYFLD_USBPD_SOP_TYPE_DETECTED__OFFSET 0x00000003u
#define CYFLD_USBPD_SOP_TYPE_DETECTED__SIZE 0x00000003u
#define CYVAL_USBPD_SOP_TYPE_DETECTED_NO_SOP_RCVD 0x00000000u
#define CYVAL_USBPD_SOP_TYPE_DETECTED_DEFAULT_SOP_RCVD 0x00000001u
#define CYVAL_USBPD_SOP_TYPE_DETECTED_PRIME_SOP_RCVD 0x00000002u
#define CYVAL_USBPD_SOP_TYPE_DETECTED_DBL_PRIME_SOP_RCVD 0x00000003u
#define CYVAL_USBPD_SOP_TYPE_DETECTED_DBG_PRIME_SOP_RCVD 0x00000004u
#define CYVAL_USBPD_SOP_TYPE_DETECTED_DBG_DBL_PRIME_SOP_RCVD 0x00000005u
#define CYVAL_USBPD_SOP_TYPE_DETECTED_RSVD1_SOP_RCVD 0x00000006u
#define CYVAL_USBPD_SOP_TYPE_DETECTED_RSVD2_SOP_RCVD 0x00000007u
#define CYFLD_USBPD_GOODCRC_MSG_SOP_TYPE_DETECTED__OFFSET 0x00000006u
#define CYFLD_USBPD_GOODCRC_MSG_SOP_TYPE_DETECTED__SIZE 0x00000003u
#define CYVAL_USBPD_GOODCRC_MSG_SOP_TYPE_DETECTED_NO_SOP_GOODCRC_RCVD 0x00000000u
#define CYVAL_USBPD_GOODCRC_MSG_SOP_TYPE_DETECTED_DEFAULT_SOP_GOODCRC_RCVD 0x00000001u
#define CYVAL_USBPD_GOODCRC_MSG_SOP_TYPE_DETECTED_PRIME_SOP_GOODCRC_RCVD 0x00000002u
#define CYVAL_USBPD_GOODCRC_MSG_SOP_TYPE_DETECTED_DBL_PRIME_SOP_GOODCRC_RCVD 0x00000003u
#define CYVAL_USBPD_GOODCRC_MSG_SOP_TYPE_DETECTED_DBG_PRIME_SOP_GOODCRC_RCVD 0x00000004u
#define CYVAL_USBPD_GOODCRC_MSG_SOP_TYPE_DETECTED_DBG_DBL_PRIME_SOP_GOODCRC_RCVD 0x00000005u
#define CYVAL_USBPD_GOODCRC_MSG_SOP_TYPE_DETECTED_RSVD1_SOP_GOODCRC_RCVD 0x00000006u
#define CYVAL_USBPD_GOODCRC_MSG_SOP_TYPE_DETECTED_RSVD2_SOP_GOODCRC_RCVD 0x00000007u
#define CYFLD_USBPD_RST_TYPE_DET__OFFSET 0x00000009u
#define CYFLD_USBPD_RST_TYPE_DET__SIZE 0x00000003u
#define CYVAL_USBPD_RST_TYPE_DET_RESERVED_RESET 0x00000000u
#define CYVAL_USBPD_RST_TYPE_DET_HARD_RESET_RCVD 0x00000001u
#define CYVAL_USBPD_RST_TYPE_DET_CABLE_RESET_RCVD 0x00000002u
#define CYVAL_USBPD_RST_TYPE_DET_RSVD1_RESET_RCVD 0x00000003u
#define CYVAL_USBPD_RST_TYPE_DET_RSVD2_RESET_RCVD 0x00000004u
#define CYFLD_USBPD_VCONN1_STATUS__OFFSET 0x0000000cu
#define CYFLD_USBPD_VCONN1_STATUS__SIZE 0x00000001u
#define CYFLD_USBPD_CC1_STATUS__OFFSET 0x0000000eu
#define CYFLD_USBPD_CC1_STATUS__SIZE 0x00000001u
#define CYFLD_USBPD_CC2_STATUS__OFFSET 0x0000000fu
#define CYFLD_USBPD_CC2_STATUS__SIZE 0x00000001u
#define CYFLD_USBPD_VCMP_LA_STATUS__OFFSET 0x00000010u
#define CYFLD_USBPD_VCMP_LA_STATUS__SIZE 0x00000001u
#define CYFLD_USBPD_VCMP_UP_STATUS__OFFSET 0x00000011u
#define CYFLD_USBPD_VCMP_UP_STATUS__SIZE 0x00000001u
#define CYFLD_USBPD_VCMP_DN_STATUS__OFFSET 0x00000012u
#define CYFLD_USBPD_VCMP_DN_STATUS__SIZE 0x00000001u
#define CYFLD_USBPD_VCMP_FS__OFFSET 0x00000013u
#define CYFLD_USBPD_VCMP_FS__SIZE 0x00000001u
#define CYFLD_USBPD_SENDING_GOODCRC_MSG__OFFSET 0x00000014u
#define CYFLD_USBPD_SENDING_GOODCRC_MSG__SIZE 0x00000001u
#define CYFLD_USBPD_V5V_STATUS__OFFSET 0x00000015u
#define CYFLD_USBPD_V5V_STATUS__SIZE 0x00000001u
#define CYFLD_USBPD_ADC1_CMP_OUT_STATUS__OFFSET 0x00000016u
#define CYFLD_USBPD_ADC1_CMP_OUT_STATUS__SIZE 0x00000001u
#define CYFLD_USBPD_ADC2_CMP_OUT_STATUS__OFFSET 0x00000017u
#define CYFLD_USBPD_ADC2_CMP_OUT_STATUS__SIZE 0x00000001u
#define CYFLD_USBPD_HPD_STATUS__OFFSET 0x00000018u
#define CYFLD_USBPD_HPD_STATUS__SIZE 0x00000001u
#define CYFLD_USBPD_SPARE6_STATUS__OFFSET 0x00000019u
#define CYFLD_USBPD_SPARE6_STATUS__SIZE 0x00000001u
#define CYFLD_USBPD_SPARE7_STATUS__OFFSET 0x0000001au
#define CYFLD_USBPD_SPARE7_STATUS__SIZE 0x00000001u
#define CYREG_USBPD_RX_SOP_GOOD_CRC_EN_CTRL 0x400a00a8u
#define CYFLD_USBPD_TX_SEND_DEFAULT_SOP_GOOD_CRC_EN__OFFSET 0x00000000u
#define CYFLD_USBPD_TX_SEND_DEFAULT_SOP_GOOD_CRC_EN__SIZE 0x00000001u
#define CYFLD_USBPD_TX_SEND_PRIME_SOP_GOOD_CRC_EN__OFFSET 0x00000001u
#define CYFLD_USBPD_TX_SEND_PRIME_SOP_GOOD_CRC_EN__SIZE 0x00000001u
#define CYFLD_USBPD_TX_SEND_DBL_PRIME_SOP_GOOD_CRC_EN__OFFSET 0x00000002u
#define CYFLD_USBPD_TX_SEND_DBL_PRIME_SOP_GOOD_CRC_EN__SIZE 0x00000001u
#define CYFLD_USBPD_EXT_TX_SEND_DEFAULT_SOP_GOOD_CRC_EN__OFFSET 0x00000003u
#define CYFLD_USBPD_EXT_TX_SEND_DEFAULT_SOP_GOOD_CRC_EN__SIZE 0x00000001u
#define CYFLD_USBPD_EXT_TX_SEND_PRIME_SOP_GOOD_CRC_EN__OFFSET 0x00000004u
#define CYFLD_USBPD_EXT_TX_SEND_PRIME_SOP_GOOD_CRC_EN__SIZE 0x00000001u
#define CYFLD_USBPD_EXT_TX_SEND_DBL_PRIME_SOP_GOOD_CRC_EN__OFFSET 0x00000005u
#define CYFLD_USBPD_EXT_TX_SEND_DBL_PRIME_SOP_GOOD_CRC_EN__SIZE 0x00000001u
#define CYFLD_USBPD_SEND_GOOD_CRC_BAD_EOP__OFFSET 0x00000006u
#define CYFLD_USBPD_SEND_GOOD_CRC_BAD_EOP__SIZE 0x00000001u
#define CYFLD_USBPD_SEND_GOOD_CRC_BAD_KCHAR__OFFSET 0x00000007u
#define CYFLD_USBPD_SEND_GOOD_CRC_BAD_KCHAR__SIZE 0x00000001u
#define CYFLD_USBPD_SEND_GOOD_CRC_SRAM_OVERFLOW__OFFSET 0x00000008u
#define CYFLD_USBPD_SEND_GOOD_CRC_SRAM_OVERFLOW__SIZE 0x00000001u
#define CYREG_USBPD_RX_DEFAULT_SOP_GOODCRC_CTRL_0 0x400a00acu
#define CYFLD_USBPD_SEND_GOOD_CRC_PER_CTRL_MSG_TYP__OFFSET 0x00000000u
#define CYFLD_USBPD_SEND_GOOD_CRC_PER_CTRL_MSG_TYP__SIZE 0x00000020u
#define CYREG_USBPD_RX_DEFAULT_SOP_GOODCRC_CTRL_1 0x400a00b0u
#define CYFLD_USBPD_SEND_GOOD_CRC_PER_DATA_MSG_TYP__OFFSET 0x00000000u
#define CYFLD_USBPD_SEND_GOOD_CRC_PER_DATA_MSG_TYP__SIZE 0x00000020u
#define CYREG_USBPD_RX_DEFAULT_SOP_GOODCRC_CTRL_2 0x400a00b4u
#define CYREG_USBPD_RX_PRIME_SOP_GOODCRC_CTRL_0 0x400a00b8u
#define CYREG_USBPD_RX_PRIME_SOP_GOODCRC_CTRL_1 0x400a00bcu
#define CYREG_USBPD_RX_PRIME_SOP_GOODCRC_CTRL_2 0x400a00c0u
#define CYREG_USBPD_RX_DBL_PRIME_SOP_GOODCRC_CTRL_0 0x400a00c4u
#define CYREG_USBPD_RX_DBL_PRIME_SOP_GOODCRC_CTRL_1 0x400a00c8u
#define CYREG_USBPD_RX_DBL_PRIME_SOP_GOODCRC_CTRL_2 0x400a00ccu
#define CYREG_USBPD_RX_EXPECT_GOODCRC_MSG 0x400a00d0u
#define CYFLD_USBPD_EXPECTED_HEADER__OFFSET 0x00000000u
#define CYFLD_USBPD_EXPECTED_HEADER__SIZE 0x00000010u
#define CYFLD_USBPD_EXPECTED_SOP__OFFSET 0x00000010u
#define CYFLD_USBPD_EXPECTED_SOP__SIZE 0x00000003u
#define CYVAL_USBPD_EXPECTED_SOP_EXP_RESERVED 0x00000000u
#define CYVAL_USBPD_EXPECTED_SOP_EXP_DEFAULT_SOP_RCVD 0x00000001u
#define CYVAL_USBPD_EXPECTED_SOP_EXP_PRIME_SOP_RCVD 0x00000002u
#define CYVAL_USBPD_EXPECTED_SOP_EXP_DBL_PRIME_SOP_RCVD 0x00000003u
#define CYVAL_USBPD_EXPECTED_SOP_EXP_DBG_PRIME_SOP_RCVD 0x00000004u
#define CYVAL_USBPD_EXPECTED_SOP_EXP_DBG_DBL_PRIME_SOP_RCVD 0x00000005u
#define CYVAL_USBPD_EXPECTED_SOP_EXP_RSVD1_SOP_RCVD 0x00000006u
#define CYVAL_USBPD_EXPECTED_SOP_EXP_RSVD2_SOP_RCVD 0x00000007u
#define CYFLD_USBPD_DISABLE_RX_CRC_TIMER__OFFSET 0x00000013u
#define CYFLD_USBPD_DISABLE_RX_CRC_TIMER__SIZE 0x00000001u
#define CYREG_USBPD_RX_GOODCRC_MSG 0x400a00d4u
#define CYFLD_USBPD_HEADER__OFFSET 0x00000000u
#define CYFLD_USBPD_HEADER__SIZE 0x00000010u
#define CYREG_USBPD_RX_CC 0x400a00d8u
#define CYFLD_USBPD_RX_CNT_MAX__OFFSET 0x00000000u
#define CYFLD_USBPD_RX_CNT_MAX__SIZE 0x00000008u
#define CYFLD_USBPD_RX_UI_BOUNDARY_DELTA__OFFSET 0x00000008u
#define CYFLD_USBPD_RX_UI_BOUNDARY_DELTA__SIZE 0x00000006u
#define CYFLD_USBPD_DELAY_HALF__OFFSET 0x0000000eu
#define CYFLD_USBPD_DELAY_HALF__SIZE 0x00000001u
#define CYFLD_USBPD_DELAY_VALUE__OFFSET 0x0000000fu
#define CYFLD_USBPD_DELAY_VALUE__SIZE 0x00000004u
#define CYFLD_USBPD_DELAY_WIDEN_HIGH__OFFSET 0x00000013u
#define CYFLD_USBPD_DELAY_WIDEN_HIGH__SIZE 0x00000001u
#define CYFLD_USBPD_DELAY_AUTO__OFFSET 0x00000014u
#define CYFLD_USBPD_DELAY_AUTO__SIZE 0x00000001u
#define CYREG_USBPD_RX_CC2 0x400a00e0u
#define CYFLD_USBPD_MIN_PULSE_VALUE__OFFSET 0x00000000u
#define CYFLD_USBPD_MIN_PULSE_VALUE__SIZE 0x00000008u
#define CYFLD_USBPD_MAX_PULSE_VALUE__OFFSET 0x00000008u
#define CYFLD_USBPD_MAX_PULSE_VALUE__SIZE 0x00000008u
#define CYFLD_USBPD_DELAY_VALID_COUNT__OFFSET 0x00000010u
#define CYFLD_USBPD_DELAY_VALID_COUNT__SIZE 0x00000004u
#define CYREG_USBPD_RX_ORDER_SET_CTRL 0x400a00e4u
#define CYFLD_USBPD_SOP_CMP_OPT__OFFSET 0x00000000u
#define CYFLD_USBPD_SOP_CMP_OPT__SIZE 0x00000001u
#define CYFLD_USBPD_RST_CMP_OPT__OFFSET 0x00000001u
#define CYFLD_USBPD_RST_CMP_OPT__SIZE 0x00000001u
#define CYFLD_USBPD_PREAMBLE_SOP_EN__OFFSET 0x00000002u
#define CYFLD_USBPD_PREAMBLE_SOP_EN__SIZE 0x00000001u
#define CYFLD_USBPD_PREAMBLE_RST_EN__OFFSET 0x00000003u
#define CYFLD_USBPD_PREAMBLE_RST_EN__SIZE 0x00000001u
#define CYFLD_USBPD_SOP_RST_EN__OFFSET 0x00000008u
#define CYFLD_USBPD_SOP_RST_EN__SIZE 0x0000000bu
#define CYVAL_USBPD_SOP_RST_EN_EN_DEFAULT_SOP_DET 0x00000001u
#define CYVAL_USBPD_SOP_RST_EN_EN_PRIME_SOP_DET 0x00000002u
#define CYVAL_USBPD_SOP_RST_EN_EN_DBL_PRIME_SOP_DET 0x00000004u
#define CYVAL_USBPD_SOP_RST_EN_EN_DEBUG_PRIME_SOP_DET 0x00000008u
#define CYVAL_USBPD_SOP_RST_EN_EN_DEBUG_DBL_PRIME_DET 0x00000010u
#define CYVAL_USBPD_SOP_RST_EN_EN_RX_CABLE_RESET_DET 0x00000020u
#define CYVAL_USBPD_SOP_RST_EN_EN_RX_HARD_RESET_DET 0x00000040u
#define CYVAL_USBPD_SOP_RST_EN_RESERVED1_CFG 0x00000080u
#define CYVAL_USBPD_SOP_RST_EN_EN_RESERVED1 0x00000100u
#define CYVAL_USBPD_SOP_RST_EN_RESERVED2_CFG 0x00000200u
#define CYVAL_USBPD_SOP_RST_EN_EN_RESERVED2 0x00000400u
#define CYREG_USBPD_RX_RESERVED1_ORDER_SET 0x400a00e8u
#define CYFLD_USBPD_RX_RESERVED1_OS__OFFSET 0x00000000u
#define CYFLD_USBPD_RX_RESERVED1_OS__SIZE 0x00000020u
#define CYREG_USBPD_RX_RESERVED2_ORDER_SET 0x400a00ecu
#define CYFLD_USBPD_RX_RESERVED2_OS__OFFSET 0x00000000u
#define CYFLD_USBPD_RX_RESERVED2_OS__SIZE 0x00000014u
#define CYREG_USBPD_TX_GOODCRC_MSG_ORDER_SET 0x400a00f0u
#define CYFLD_USBPD_TX_GOODCRC_OS__OFFSET 0x00000000u
#define CYFLD_USBPD_TX_GOODCRC_OS__SIZE 0x00000020u
#define CYREG_USBPD_TX_CTRL 0x400a00f4u
#define CYFLD_USBPD_GOODCRC_MSG_BITS__OFFSET 0x00000000u
#define CYFLD_USBPD_GOODCRC_MSG_BITS__SIZE 0x00000010u
#define CYFLD_USBPD_EN_TX_BIST_CM2__OFFSET 0x00000010u
#define CYFLD_USBPD_EN_TX_BIST_CM2__SIZE 0x00000001u
#define CYFLD_USBPD_TX_GO__OFFSET 0x00000011u
#define CYFLD_USBPD_TX_GO__SIZE 0x00000001u
#define CYFLD_USBPD_TX_SEND_RST__OFFSET 0x00000012u
#define CYFLD_USBPD_TX_SEND_RST__SIZE 0x00000001u
#define CYFLD_USBPD_TX_RETRY_ENABLE__OFFSET 0x00000013u
#define CYFLD_USBPD_TX_RETRY_ENABLE__SIZE 0x00000001u
#define CYFLD_USBPD_TX_REG_EN__OFFSET 0x00000014u
#define CYFLD_USBPD_TX_REG_EN__SIZE 0x00000001u
#define CYFLD_USBPD_TX_REG_CFG__OFFSET 0x00000015u
#define CYFLD_USBPD_TX_REG_CFG__SIZE 0x00000001u
#define CYFLD_USBPD_TX_REG_TIMER__OFFSET 0x00000018u
#define CYFLD_USBPD_TX_REG_TIMER__SIZE 0x00000006u
#define CYFLD_USBPD_TX_CORRUPT_CRC_ON_UNDER_FLOW__OFFSET 0x0000001fu
#define CYFLD_USBPD_TX_CORRUPT_CRC_ON_UNDER_FLOW__SIZE 0x00000001u
#define CYREG_USBPD_TX_SOP_ORDER_SET 0x400a00f8u
#define CYFLD_USBPD_TX_SOP_OS__OFFSET 0x00000000u
#define CYFLD_USBPD_TX_SOP_OS__SIZE 0x00000014u
#define CYREG_USBPD_TX_HARD_CABLE_ORDER_SET 0x400a00fcu
#define CYFLD_USBPD_TX_RESET_OS__OFFSET 0x00000000u
#define CYFLD_USBPD_TX_RESET_OS__SIZE 0x00000014u
#define CYREG_USBPD_CRC_COUNTER 0x400a0100u
#define CYFLD_USBPD_CRC_COUNTER__OFFSET 0x00000000u
#define CYFLD_USBPD_CRC_COUNTER__SIZE 0x00000010u
#define CYREG_USBPD_INTER_PACKET_COUNTER 0x400a0104u
#define CYFLD_USBPD_BUS_IDLE_CNT__OFFSET 0x00000000u
#define CYFLD_USBPD_BUS_IDLE_CNT__SIZE 0x0000000bu
#define CYFLD_USBPD_IDLE_COUNTER__OFFSET 0x0000000bu
#define CYFLD_USBPD_IDLE_COUNTER__SIZE 0x0000000au
#define CYFLD_USBPD_IFG_COUNTER__OFFSET 0x00000015u
#define CYFLD_USBPD_IFG_COUNTER__SIZE 0x0000000bu
#define CYREG_USBPD_TIMER_TRIGGER 0x400a0108u
#define CYFLD_USBPD_EN_TRIGGER0__OFFSET 0x00000000u
#define CYFLD_USBPD_EN_TRIGGER0__SIZE 0x00000001u
#define CYFLD_USBPD_EN_TRIGGER1__OFFSET 0x00000001u
#define CYFLD_USBPD_EN_TRIGGER1__SIZE 0x00000001u
#define CYFLD_USBPD_EN_TRIGGER2__OFFSET 0x00000002u
#define CYFLD_USBPD_EN_TRIGGER2__SIZE 0x00000001u
#define CYFLD_USBPD_EN_TRIGGER3__OFFSET 0x00000003u
#define CYFLD_USBPD_EN_TRIGGER3__SIZE 0x00000001u
#define CYFLD_USBPD_EN_TRIGGER4__OFFSET 0x00000004u
#define CYFLD_USBPD_EN_TRIGGER4__SIZE 0x00000001u
#define CYFLD_USBPD_EN_TRIGGER5__OFFSET 0x00000005u
#define CYFLD_USBPD_EN_TRIGGER5__SIZE 0x00000001u
#define CYFLD_USBPD_EN_TRIGGER6__OFFSET 0x00000006u
#define CYFLD_USBPD_EN_TRIGGER6__SIZE 0x00000001u
#define CYREG_USBPD_INTR_DDFT_MUX 0x400a010cu
#define CYFLD_USBPD_intr_ddft0_sel__OFFSET 0x00000000u
#define CYFLD_USBPD_intr_ddft0_sel__SIZE 0x00000007u
#define CYFLD_USBPD_intr_ddft1_sel__OFFSET 0x00000007u
#define CYFLD_USBPD_intr_ddft1_sel__SIZE 0x00000007u
#define CYREG_USBPD_DDFT_MUX 0x400a0110u
#define CYFLD_USBPD_ddft0_sel__OFFSET 0x00000000u
#define CYFLD_USBPD_ddft0_sel__SIZE 0x00000006u
#define CYFLD_USBPD_ddft1_sel__OFFSET 0x00000006u
#define CYFLD_USBPD_ddft1_sel__SIZE 0x00000006u
#define CYREG_USBPD_INTR_1_CFG 0x400a0114u
#define CYFLD_USBPD_VCONN1_CFG__OFFSET 0x00000000u
#define CYFLD_USBPD_VCONN1_CFG__SIZE 0x00000002u
#define CYVAL_USBPD_VCONN1_CFG_POS_EDG_DIS_NEG_EDG_DIS 0x00000000u
#define CYVAL_USBPD_VCONN1_CFG_POS_EDG_DIS_NEG_EDG_EN 0x00000001u
#define CYVAL_USBPD_VCONN1_CFG_POS_EDG_EN_NEG_EDG_DIS 0x00000002u
#define CYVAL_USBPD_VCONN1_CFG_POS_EDG_EN_NEG_EDG_EN 0x00000003u
#define CYFLD_USBPD_CC1_CFG__OFFSET 0x00000004u
#define CYFLD_USBPD_CC1_CFG__SIZE 0x00000002u
#define CYVAL_USBPD_CC1_CFG_POS_EDG_DIS_NEG_EDG_DIS 0x00000000u
#define CYVAL_USBPD_CC1_CFG_POS_EDG_DIS_NEG_EDG_EN 0x00000001u
#define CYVAL_USBPD_CC1_CFG_POS_EDG_EN_NEG_EDG_DIS 0x00000002u
#define CYVAL_USBPD_CC1_CFG_POS_EDG_EN_NEG_EDG_EN 0x00000003u
#define CYFLD_USBPD_CC2_CFG__OFFSET 0x00000006u
#define CYFLD_USBPD_CC2_CFG__SIZE 0x00000002u
#define CYVAL_USBPD_CC2_CFG_POS_EDG_DIS_NEG_EDG_DIS 0x00000000u
#define CYVAL_USBPD_CC2_CFG_POS_EDG_DIS_NEG_EDG_EN 0x00000001u
#define CYVAL_USBPD_CC2_CFG_POS_EDG_EN_NEG_EDG_DIS 0x00000002u
#define CYVAL_USBPD_CC2_CFG_POS_EDG_EN_NEG_EDG_EN 0x00000003u
#define CYFLD_USBPD_VCMP_UP_CFG__OFFSET 0x00000008u
#define CYFLD_USBPD_VCMP_UP_CFG__SIZE 0x00000002u
#define CYVAL_USBPD_VCMP_UP_CFG_POS_EDG_DIS_NEG_EDG_DIS 0x00000000u
#define CYVAL_USBPD_VCMP_UP_CFG_POS_EDG_DIS_NEG_EDG_EN 0x00000001u
#define CYVAL_USBPD_VCMP_UP_CFG_POS_EDG_EN_NEG_EDG_DIS 0x00000002u
#define CYVAL_USBPD_VCMP_UP_CFG_POS_EDG_EN_NEG_EDG_EN 0x00000003u
#define CYFLD_USBPD_VCMP_DN_CFG__OFFSET 0x0000000au
#define CYFLD_USBPD_VCMP_DN_CFG__SIZE 0x00000002u
#define CYVAL_USBPD_VCMP_DN_CFG_POS_EDG_DIS_NEG_EDG_DIS 0x00000000u
#define CYVAL_USBPD_VCMP_DN_CFG_POS_EDG_DIS_NEG_EDG_EN 0x00000001u
#define CYVAL_USBPD_VCMP_DN_CFG_POS_EDG_EN_NEG_EDG_DIS 0x00000002u
#define CYVAL_USBPD_VCMP_DN_CFG_POS_EDG_EN_NEG_EDG_EN 0x00000003u
#define CYFLD_USBPD_VCMP_LA_CFG__OFFSET 0x0000000cu
#define CYFLD_USBPD_VCMP_LA_CFG__SIZE 0x00000002u
#define CYVAL_USBPD_VCMP_LA_CFG_POS_EDG_DIS_NEG_EDG_DIS 0x00000000u
#define CYVAL_USBPD_VCMP_LA_CFG_POS_EDG_DIS_NEG_EDG_EN 0x00000001u
#define CYVAL_USBPD_VCMP_LA_CFG_POS_EDG_EN_NEG_EDG_DIS 0x00000002u
#define CYVAL_USBPD_VCMP_LA_CFG_POS_EDG_EN_NEG_EDG_EN 0x00000003u
#define CYFLD_USBPD_VCONN1_FILT_EN__OFFSET 0x0000000eu
#define CYFLD_USBPD_VCONN1_FILT_EN__SIZE 0x00000001u
#define CYFLD_USBPD_CC1_CFG_FILT_EN__OFFSET 0x00000010u
#define CYFLD_USBPD_CC1_CFG_FILT_EN__SIZE 0x00000001u
#define CYFLD_USBPD_CC2_FILT_EN__OFFSET 0x00000011u
#define CYFLD_USBPD_CC2_FILT_EN__SIZE 0x00000001u
#define CYFLD_USBPD_VCMP_UP_FILT_EN__OFFSET 0x00000012u
#define CYFLD_USBPD_VCMP_UP_FILT_EN__SIZE 0x00000001u
#define CYFLD_USBPD_VCMP_DN_FILT_EN__OFFSET 0x00000013u
#define CYFLD_USBPD_VCMP_DN_FILT_EN__SIZE 0x00000001u
#define CYFLD_USBPD_V5V_FILT_EN__OFFSET 0x00000014u
#define CYFLD_USBPD_V5V_FILT_EN__SIZE 0x00000001u
#define CYFLD_USBPD_V5V_CFG__OFFSET 0x00000015u
#define CYFLD_USBPD_V5V_CFG__SIZE 0x00000002u
#define CYVAL_USBPD_V5V_CFG_POS_EDG_DIS_NEG_EDG_DIS 0x00000000u
#define CYVAL_USBPD_V5V_CFG_POS_EDG_DIS_NEG_EDG_EN 0x00000001u
#define CYVAL_USBPD_V5V_CFG_POS_EDG_EN_NEG_EDG_DIS 0x00000002u
#define CYVAL_USBPD_V5V_CFG_POS_EDG_EN_NEG_EDG_EN 0x00000003u
#define CYFLD_USBPD_CMP_OUT1_FILT_EN__OFFSET 0x00000017u
#define CYFLD_USBPD_CMP_OUT1_FILT_EN__SIZE 0x00000001u
#define CYFLD_USBPD_ADC1_CFG__OFFSET 0x00000018u
#define CYFLD_USBPD_ADC1_CFG__SIZE 0x00000002u
#define CYVAL_USBPD_ADC1_CFG_POS_EDG_DIS_NEG_EDG_DIS 0x00000000u
#define CYVAL_USBPD_ADC1_CFG_POS_EDG_DIS_NEG_EDG_EN 0x00000001u
#define CYVAL_USBPD_ADC1_CFG_POS_EDG_EN_NEG_EDG_DIS 0x00000002u
#define CYVAL_USBPD_ADC1_CFG_POS_EDG_EN_NEG_EDG_EN 0x00000003u
#define CYFLD_USBPD_CMP_OUT2_FILT_EN__OFFSET 0x0000001au
#define CYFLD_USBPD_CMP_OUT2_FILT_EN__SIZE 0x00000001u
#define CYFLD_USBPD_ADC2_CFG__OFFSET 0x0000001bu
#define CYFLD_USBPD_ADC2_CFG__SIZE 0x00000002u
#define CYVAL_USBPD_ADC2_CFG_POS_EDG_DIS_NEG_EDG_DIS 0x00000000u
#define CYVAL_USBPD_ADC2_CFG_POS_EDG_DIS_NEG_EDG_EN 0x00000001u
#define CYVAL_USBPD_ADC2_CFG_POS_EDG_EN_NEG_EDG_DIS 0x00000002u
#define CYVAL_USBPD_ADC2_CFG_POS_EDG_EN_NEG_EDG_EN 0x00000003u
#define CYFLD_USBPD_HPDIN_CFG__OFFSET 0x0000001du
#define CYFLD_USBPD_HPDIN_CFG__SIZE 0x00000002u
#define CYVAL_USBPD_HPDIN_CFG_POS_EDG_DIS_NEG_EDG_DIS 0x00000000u
#define CYVAL_USBPD_HPDIN_CFG_POS_EDG_DIS_NEG_EDG_EN 0x00000001u
#define CYVAL_USBPD_HPDIN_CFG_POS_EDG_EN_NEG_EDG_DIS 0x00000002u
#define CYVAL_USBPD_HPDIN_CFG_POS_EDG_EN_NEG_EDG_EN 0x00000003u
#define CYFLD_USBPD_HPDIN_FILT_EN__OFFSET 0x0000001fu
#define CYFLD_USBPD_HPDIN_FILT_EN__SIZE 0x00000001u
#define CYREG_USBPD_INTR0 0x400a0118u
#define CYFLD_USBPD_RCV_GOOD_PACKET_COMPLETE__OFFSET 0x00000000u
#define CYFLD_USBPD_RCV_GOOD_PACKET_COMPLETE__SIZE 0x00000001u
#define CYFLD_USBPD_RCV_BAD_PACKET_COMPLETE__OFFSET 0x00000001u
#define CYFLD_USBPD_RCV_BAD_PACKET_COMPLETE__SIZE 0x00000001u
#define CYFLD_USBPD_RX_SOP__OFFSET 0x00000002u
#define CYFLD_USBPD_RX_SOP__SIZE 0x00000001u
#define CYFLD_USBPD_RCV_GOODCRC_MSG_COMPLETE__OFFSET 0x00000003u
#define CYFLD_USBPD_RCV_GOODCRC_MSG_COMPLETE__SIZE 0x00000001u
#define CYFLD_USBPD_RCV_EXPT_GOODCRC_MSG_COMPLETE__OFFSET 0x00000004u
#define CYFLD_USBPD_RCV_EXPT_GOODCRC_MSG_COMPLETE__SIZE 0x00000001u
#define CYFLD_USBPD_EOP_ERROR__OFFSET 0x00000005u
#define CYFLD_USBPD_EOP_ERROR__SIZE 0x00000001u
#define CYFLD_USBPD_RX_OVER_RUN__OFFSET 0x00000006u
#define CYFLD_USBPD_RX_OVER_RUN__SIZE 0x00000001u
#define CYFLD_USBPD_TX_PACKET_DONE__OFFSET 0x00000007u
#define CYFLD_USBPD_TX_PACKET_DONE__SIZE 0x00000001u
#define CYFLD_USBPD_TX_HARD_RST_DONE__OFFSET 0x00000008u
#define CYFLD_USBPD_TX_HARD_RST_DONE__SIZE 0x00000001u
#define CYFLD_USBPD_RCV_RST__OFFSET 0x00000009u
#define CYFLD_USBPD_RCV_RST__SIZE 0x00000001u
#define CYFLD_USBPD_SAR1_DONE__OFFSET 0x0000000au
#define CYFLD_USBPD_SAR1_DONE__SIZE 0x00000001u
#define CYFLD_USBPD_TX_GOODCRC_MSG_DONE__OFFSET 0x0000000bu
#define CYFLD_USBPD_TX_GOODCRC_MSG_DONE__SIZE 0x00000001u
#define CYFLD_USBPD_CC_VALID_DATA_DETECTED__OFFSET 0x0000000cu
#define CYFLD_USBPD_CC_VALID_DATA_DETECTED__SIZE 0x00000001u
#define CYFLD_USBPD_CC_NO_VALID_DATA_DETECTED__OFFSET 0x0000000du
#define CYFLD_USBPD_CC_NO_VALID_DATA_DETECTED__SIZE 0x00000001u
#define CYFLD_USBPD_CRC_RX_TIMER_EXP__OFFSET 0x0000000eu
#define CYFLD_USBPD_CRC_RX_TIMER_EXP__SIZE 0x00000001u
#define CYFLD_USBPD_COLLISION_TYPE1__OFFSET 0x0000000fu
#define CYFLD_USBPD_COLLISION_TYPE1__SIZE 0x00000001u
#define CYFLD_USBPD_COLLISION_TYPE2__OFFSET 0x00000010u
#define CYFLD_USBPD_COLLISION_TYPE2__SIZE 0x00000001u
#define CYFLD_USBPD_COLLISION_TYPE3__OFFSET 0x00000011u
#define CYFLD_USBPD_COLLISION_TYPE3__SIZE 0x00000001u
#define CYFLD_USBPD_COLLISION_TYPE4__OFFSET 0x00000012u
#define CYFLD_USBPD_COLLISION_TYPE4__SIZE 0x00000001u
#define CYFLD_USBPD_CMP_OUT1_DET__OFFSET 0x00000013u
#define CYFLD_USBPD_CMP_OUT1_DET__SIZE 0x00000001u
#define CYFLD_USBPD_TX_SRAM_HALF_END__OFFSET 0x00000014u
#define CYFLD_USBPD_TX_SRAM_HALF_END__SIZE 0x00000001u
#define CYFLD_USBPD_RX_SRAM_HALF_END__OFFSET 0x00000015u
#define CYFLD_USBPD_RX_SRAM_HALF_END__SIZE 0x00000001u
#define CYFLD_USBPD_TX_RETRY_ENABLE_CLRD__OFFSET 0x00000016u
#define CYFLD_USBPD_TX_RETRY_ENABLE_CLRD__SIZE 0x00000001u
#define CYFLD_USBPD_KCHAR_ERROR__OFFSET 0x00000017u
#define CYFLD_USBPD_KCHAR_ERROR__SIZE 0x00000001u
#define CYFLD_USBPD_TX_CC_DATA_OEN_ASSERT__OFFSET 0x00000018u
#define CYFLD_USBPD_TX_CC_DATA_OEN_ASSERT__SIZE 0x00000001u
#define CYFLD_USBPD_TX_CC_DATA_OEN_DEASSERT__OFFSET 0x00000019u
#define CYFLD_USBPD_TX_CC_DATA_OEN_DEASSERT__SIZE 0x00000001u
#define CYFLD_USBPD_TX_REGULATOR_ENABLED__OFFSET 0x0000001au
#define CYFLD_USBPD_TX_REGULATOR_ENABLED__SIZE 0x00000001u
#define CYFLD_USBPD_TX_STATE_IDLE__OFFSET 0x0000001bu
#define CYFLD_USBPD_TX_STATE_IDLE__SIZE 0x00000001u
#define CYFLD_USBPD_RX_STATE_IDLE__OFFSET 0x0000001cu
#define CYFLD_USBPD_RX_STATE_IDLE__SIZE 0x00000001u
#define CYFLD_USBPD_SAR2_DONE__OFFSET 0x0000001du
#define CYFLD_USBPD_SAR2_DONE__SIZE 0x00000001u
#define CYFLD_USBPD_CMP_OUT2_DET__OFFSET 0x0000001eu
#define CYFLD_USBPD_CMP_OUT2_DET__SIZE 0x00000001u
#define CYREG_USBPD_INTR1 0x400a011cu
#define CYFLD_USBPD_VCONN1_CHANGED__OFFSET 0x00000000u
#define CYFLD_USBPD_VCONN1_CHANGED__SIZE 0x00000001u
#define CYFLD_USBPD_CC1_CHANGED__OFFSET 0x00000002u
#define CYFLD_USBPD_CC1_CHANGED__SIZE 0x00000001u
#define CYFLD_USBPD_CC2_CHANGED__OFFSET 0x00000003u
#define CYFLD_USBPD_CC2_CHANGED__SIZE 0x00000001u
#define CYFLD_USBPD_VCMP_LA_CHANGED__OFFSET 0x00000004u
#define CYFLD_USBPD_VCMP_LA_CHANGED__SIZE 0x00000001u
#define CYFLD_USBPD_VCMP_UP_CHANGED__OFFSET 0x00000005u
#define CYFLD_USBPD_VCMP_UP_CHANGED__SIZE 0x00000001u
#define CYFLD_USBPD_VCMP_DN_CHANGED__OFFSET 0x00000006u
#define CYFLD_USBPD_VCMP_DN_CHANGED__SIZE 0x00000001u
#define CYFLD_USBPD_V5V_CHANGED__OFFSET 0x00000007u
#define CYFLD_USBPD_V5V_CHANGED__SIZE 0x00000001u
#define CYFLD_USBPD_CMP_OUT1_CHANGED__OFFSET 0x00000008u
#define CYFLD_USBPD_CMP_OUT1_CHANGED__SIZE 0x00000001u
#define CYFLD_USBPD_CMP_OUT2_CHANGED__OFFSET 0x00000009u
#define CYFLD_USBPD_CMP_OUT2_CHANGED__SIZE 0x00000001u
#define CYFLD_USBPD_HPDIN_CHANGED__OFFSET 0x0000000au
#define CYFLD_USBPD_HPDIN_CHANGED__SIZE 0x00000001u
#define CYFLD_USBPD_SPARE6__OFFSET 0x0000000bu
#define CYFLD_USBPD_SPARE6__SIZE 0x00000001u
#define CYFLD_USBPD_SPARE7__OFFSET 0x0000000cu
#define CYFLD_USBPD_SPARE7__SIZE 0x00000001u
#define CYREG_USBPD_INTR0_SET 0x400a0120u
#define CYREG_USBPD_INTR1_SET 0x400a0124u
#define CYREG_USBPD_INTR0_MASK 0x400a0128u
#define CYFLD_USBPD_RCV_GOOD_PACKET_COMPLETE_MASK__OFFSET 0x00000000u
#define CYFLD_USBPD_RCV_GOOD_PACKET_COMPLETE_MASK__SIZE 0x00000001u
#define CYFLD_USBPD_RCV_BAD_PACKET_COMPLETE_MASK__OFFSET 0x00000001u
#define CYFLD_USBPD_RCV_BAD_PACKET_COMPLETE_MASK__SIZE 0x00000001u
#define CYFLD_USBPD_RX_SOP_MASK__OFFSET 0x00000002u
#define CYFLD_USBPD_RX_SOP_MASK__SIZE 0x00000001u
#define CYFLD_USBPD_RCV_GOODCRC_MSG_COMPLETE_MASK__OFFSET 0x00000003u
#define CYFLD_USBPD_RCV_GOODCRC_MSG_COMPLETE_MASK__SIZE 0x00000001u
#define CYFLD_USBPD_RCV_EXPT_GOODCRC_MSG_COMPLETE_MASK__OFFSET 0x00000004u
#define CYFLD_USBPD_RCV_EXPT_GOODCRC_MSG_COMPLETE_MASK__SIZE 0x00000001u
#define CYFLD_USBPD_EOP_ERROR_MASK__OFFSET 0x00000005u
#define CYFLD_USBPD_EOP_ERROR_MASK__SIZE 0x00000001u
#define CYFLD_USBPD_RX_OVER_RUN_MASK__OFFSET 0x00000006u
#define CYFLD_USBPD_RX_OVER_RUN_MASK__SIZE 0x00000001u
#define CYFLD_USBPD_TX_PACKET_DONE_MASK__OFFSET 0x00000007u
#define CYFLD_USBPD_TX_PACKET_DONE_MASK__SIZE 0x00000001u
#define CYFLD_USBPD_TX_HARD_RST_DONE_MASK__OFFSET 0x00000008u
#define CYFLD_USBPD_TX_HARD_RST_DONE_MASK__SIZE 0x00000001u
#define CYFLD_USBPD_RCV_RST_MASK__OFFSET 0x00000009u
#define CYFLD_USBPD_RCV_RST_MASK__SIZE 0x00000001u
#define CYFLD_USBPD_SAR1_DONE_MASK__OFFSET 0x0000000au
#define CYFLD_USBPD_SAR1_DONE_MASK__SIZE 0x00000001u
#define CYFLD_USBPD_TX_GOODCRC_MSG_DONE_MASK__OFFSET 0x0000000bu
#define CYFLD_USBPD_TX_GOODCRC_MSG_DONE_MASK__SIZE 0x00000001u
#define CYFLD_USBPD_CC_VALID_DATA_DETECTED_MASK__OFFSET 0x0000000cu
#define CYFLD_USBPD_CC_VALID_DATA_DETECTED_MASK__SIZE 0x00000001u
#define CYFLD_USBPD_CC_NO_VALID_DATA_DETECTED_MASK__OFFSET 0x0000000du
#define CYFLD_USBPD_CC_NO_VALID_DATA_DETECTED_MASK__SIZE 0x00000001u
#define CYFLD_USBPD_CRC_RX_TIMER_EXP_MASK__OFFSET 0x0000000eu
#define CYFLD_USBPD_CRC_RX_TIMER_EXP_MASK__SIZE 0x00000001u
#define CYFLD_USBPD_COLLISION_TYPE1_MASK__OFFSET 0x0000000fu
#define CYFLD_USBPD_COLLISION_TYPE1_MASK__SIZE 0x00000001u
#define CYFLD_USBPD_COLLISION_TYPE2_MASK__OFFSET 0x00000010u
#define CYFLD_USBPD_COLLISION_TYPE2_MASK__SIZE 0x00000001u
#define CYFLD_USBPD_COLLISION_TYPE3_MASK__OFFSET 0x00000011u
#define CYFLD_USBPD_COLLISION_TYPE3_MASK__SIZE 0x00000001u
#define CYFLD_USBPD_COLLISION_TYPE4_MASK__OFFSET 0x00000012u
#define CYFLD_USBPD_COLLISION_TYPE4_MASK__SIZE 0x00000001u
#define CYFLD_USBPD_CMP_OUT1_DET_MASK__OFFSET 0x00000013u
#define CYFLD_USBPD_CMP_OUT1_DET_MASK__SIZE 0x00000001u
#define CYFLD_USBPD_TX_SRAM_HALF_END_MASK__OFFSET 0x00000014u
#define CYFLD_USBPD_TX_SRAM_HALF_END_MASK__SIZE 0x00000001u
#define CYFLD_USBPD_RX_SRAM_HALF_END_MASK__OFFSET 0x00000015u
#define CYFLD_USBPD_RX_SRAM_HALF_END_MASK__SIZE 0x00000001u
#define CYFLD_USBPD_TX_RETRY_ENABLE_CLRD_MASK__OFFSET 0x00000016u
#define CYFLD_USBPD_TX_RETRY_ENABLE_CLRD_MASK__SIZE 0x00000001u
#define CYFLD_USBPD_KCHAR_ERROR_MASK__OFFSET 0x00000017u
#define CYFLD_USBPD_KCHAR_ERROR_MASK__SIZE 0x00000001u
#define CYFLD_USBPD_TX_CC_DATA_OEN_ASSERT_MASK__OFFSET 0x00000018u
#define CYFLD_USBPD_TX_CC_DATA_OEN_ASSERT_MASK__SIZE 0x00000001u
#define CYFLD_USBPD_TX_CC_DATA_OEN_DEASSERT_MASK__OFFSET 0x00000019u
#define CYFLD_USBPD_TX_CC_DATA_OEN_DEASSERT_MASK__SIZE 0x00000001u
#define CYFLD_USBPD_TX_REGULATOR_ENABLED_MASK__OFFSET 0x0000001au
#define CYFLD_USBPD_TX_REGULATOR_ENABLED_MASK__SIZE 0x00000001u
#define CYFLD_USBPD_TX_STATE_IDLE_MASK__OFFSET 0x0000001bu
#define CYFLD_USBPD_TX_STATE_IDLE_MASK__SIZE 0x00000001u
#define CYFLD_USBPD_RX_STATE_IDLE_MASK__OFFSET 0x0000001cu
#define CYFLD_USBPD_RX_STATE_IDLE_MASK__SIZE 0x00000001u
#define CYFLD_USBPD_SAR2_DONE_MASK__OFFSET 0x0000001du
#define CYFLD_USBPD_SAR2_DONE_MASK__SIZE 0x00000001u
#define CYFLD_USBPD_CMP_OUT2_DET_MASK__OFFSET 0x0000001eu
#define CYFLD_USBPD_CMP_OUT2_DET_MASK__SIZE 0x00000001u
#define CYREG_USBPD_INTR1_MASK 0x400a012cu
#define CYFLD_USBPD_VCONN1_CHANGED_MASK__OFFSET 0x00000000u
#define CYFLD_USBPD_VCONN1_CHANGED_MASK__SIZE 0x00000001u
#define CYFLD_USBPD_CC1_CHANGED_MASK__OFFSET 0x00000002u
#define CYFLD_USBPD_CC1_CHANGED_MASK__SIZE 0x00000001u
#define CYFLD_USBPD_CC2_CHANGED_MASK__OFFSET 0x00000003u
#define CYFLD_USBPD_CC2_CHANGED_MASK__SIZE 0x00000001u
#define CYFLD_USBPD_VCMP_LA_CHANGED_MASK__OFFSET 0x00000004u
#define CYFLD_USBPD_VCMP_LA_CHANGED_MASK__SIZE 0x00000001u
#define CYFLD_USBPD_VCMP_UP_CHANGED_MASK__OFFSET 0x00000005u
#define CYFLD_USBPD_VCMP_UP_CHANGED_MASK__SIZE 0x00000001u
#define CYFLD_USBPD_VCMP_DN_CHANGED_MASK__OFFSET 0x00000006u
#define CYFLD_USBPD_VCMP_DN_CHANGED_MASK__SIZE 0x00000001u
#define CYFLD_USBPD_V5V_CHANGED_MASK__OFFSET 0x00000007u
#define CYFLD_USBPD_V5V_CHANGED_MASK__SIZE 0x00000001u
#define CYFLD_USBPD_CMP_OUT1_CHANGED_MASK__OFFSET 0x00000008u
#define CYFLD_USBPD_CMP_OUT1_CHANGED_MASK__SIZE 0x00000001u
#define CYFLD_USBPD_CMP_OUT2_CHANGED_MASK__OFFSET 0x00000009u
#define CYFLD_USBPD_CMP_OUT2_CHANGED_MASK__SIZE 0x00000001u
#define CYFLD_USBPD_HPDIN_CHANGED_MASK__OFFSET 0x0000000au
#define CYFLD_USBPD_HPDIN_CHANGED_MASK__SIZE 0x00000001u
#define CYFLD_USBPD_SPARE6_MASK__OFFSET 0x0000000bu
#define CYFLD_USBPD_SPARE6_MASK__SIZE 0x00000001u
#define CYFLD_USBPD_SPARE7_MASK__OFFSET 0x0000000cu
#define CYFLD_USBPD_SPARE7_MASK__SIZE 0x00000001u
#define CYREG_USBPD_INTR0_MASKED 0x400a0130u
#define CYFLD_USBPD_RCV_GOOD_PACKET_COMPLETE_MASKED__OFFSET 0x00000000u
#define CYFLD_USBPD_RCV_GOOD_PACKET_COMPLETE_MASKED__SIZE 0x00000001u
#define CYFLD_USBPD_RCV_BAD_PACKET_COMPLETE_MASKED__OFFSET 0x00000001u
#define CYFLD_USBPD_RCV_BAD_PACKET_COMPLETE_MASKED__SIZE 0x00000001u
#define CYFLD_USBPD_RX_SOP_MASKED__OFFSET 0x00000002u
#define CYFLD_USBPD_RX_SOP_MASKED__SIZE 0x00000001u
#define CYFLD_USBPD_RCV_GOODCRC_MSG_COMPLETE_MASKED__OFFSET 0x00000003u
#define CYFLD_USBPD_RCV_GOODCRC_MSG_COMPLETE_MASKED__SIZE 0x00000001u
#define CYFLD_USBPD_RCV_EXPT_GOODCRC_MSG_COMPLETE_MASKED__OFFSET 0x00000004u
#define CYFLD_USBPD_RCV_EXPT_GOODCRC_MSG_COMPLETE_MASKED__SIZE 0x00000001u
#define CYFLD_USBPD_EOP_ERROR_MASKED__OFFSET 0x00000005u
#define CYFLD_USBPD_EOP_ERROR_MASKED__SIZE 0x00000001u
#define CYFLD_USBPD_RX_OVER_RUN_MASKED__OFFSET 0x00000006u
#define CYFLD_USBPD_RX_OVER_RUN_MASKED__SIZE 0x00000001u
#define CYFLD_USBPD_TX_PACKET_DONE_MASKED__OFFSET 0x00000007u
#define CYFLD_USBPD_TX_PACKET_DONE_MASKED__SIZE 0x00000001u
#define CYFLD_USBPD_TX_HARD_RST_DONE_MASKED__OFFSET 0x00000008u
#define CYFLD_USBPD_TX_HARD_RST_DONE_MASKED__SIZE 0x00000001u
#define CYFLD_USBPD_RCV_RST_MASKED__OFFSET 0x00000009u
#define CYFLD_USBPD_RCV_RST_MASKED__SIZE 0x00000001u
#define CYFLD_USBPD_SAR1_DONE_MASKED__OFFSET 0x0000000au
#define CYFLD_USBPD_SAR1_DONE_MASKED__SIZE 0x00000001u
#define CYFLD_USBPD_TX_GOODCRC_MSG_DONE_MASKED__OFFSET 0x0000000bu
#define CYFLD_USBPD_TX_GOODCRC_MSG_DONE_MASKED__SIZE 0x00000001u
#define CYFLD_USBPD_CC_VALID_DATA_DETECTED_MASKED__OFFSET 0x0000000cu
#define CYFLD_USBPD_CC_VALID_DATA_DETECTED_MASKED__SIZE 0x00000001u
#define CYFLD_USBPD_CC_NO_VALID_DATA_DETECTED_MASKED__OFFSET 0x0000000du
#define CYFLD_USBPD_CC_NO_VALID_DATA_DETECTED_MASKED__SIZE 0x00000001u
#define CYFLD_USBPD_CRC_RX_TIMER_EXP_MASKED__OFFSET 0x0000000eu
#define CYFLD_USBPD_CRC_RX_TIMER_EXP_MASKED__SIZE 0x00000001u
#define CYFLD_USBPD_COLLISION_TYPE1_MASKED__OFFSET 0x0000000fu
#define CYFLD_USBPD_COLLISION_TYPE1_MASKED__SIZE 0x00000001u
#define CYFLD_USBPD_COLLISION_TYPE2_MASKED__OFFSET 0x00000010u
#define CYFLD_USBPD_COLLISION_TYPE2_MASKED__SIZE 0x00000001u
#define CYFLD_USBPD_COLLISION_TYPE3_MASKED__OFFSET 0x00000011u
#define CYFLD_USBPD_COLLISION_TYPE3_MASKED__SIZE 0x00000001u
#define CYFLD_USBPD_COLLISION_TYPE4_MASKED__OFFSET 0x00000012u
#define CYFLD_USBPD_COLLISION_TYPE4_MASKED__SIZE 0x00000001u
#define CYFLD_USBPD_CMP_OUT1_DET_MASKED__OFFSET 0x00000013u
#define CYFLD_USBPD_CMP_OUT1_DET_MASKED__SIZE 0x00000001u
#define CYFLD_USBPD_TX_SRAM_HALF_END_MASKED__OFFSET 0x00000014u
#define CYFLD_USBPD_TX_SRAM_HALF_END_MASKED__SIZE 0x00000001u
#define CYFLD_USBPD_RX_SRAM_HALF_END_MASKED__OFFSET 0x00000015u
#define CYFLD_USBPD_RX_SRAM_HALF_END_MASKED__SIZE 0x00000001u
#define CYFLD_USBPD_TX_RETRY_ENABLE_CLRD_MASKED__OFFSET 0x00000016u
#define CYFLD_USBPD_TX_RETRY_ENABLE_CLRD_MASKED__SIZE 0x00000001u
#define CYFLD_USBPD_KCHAR_ERROR_MASKED__OFFSET 0x00000017u
#define CYFLD_USBPD_KCHAR_ERROR_MASKED__SIZE 0x00000001u
#define CYFLD_USBPD_TX_CC_DATA_OEN_ASSERT_MASKED__OFFSET 0x00000018u
#define CYFLD_USBPD_TX_CC_DATA_OEN_ASSERT_MASKED__SIZE 0x00000001u
#define CYFLD_USBPD_TX_CC_DATA_OEN_DEASSERT_MASKED__OFFSET 0x00000019u
#define CYFLD_USBPD_TX_CC_DATA_OEN_DEASSERT_MASKED__SIZE 0x00000001u
#define CYFLD_USBPD_TX_REGULATOR_ENABLED_MASKED__OFFSET 0x0000001au
#define CYFLD_USBPD_TX_REGULATOR_ENABLED_MASKED__SIZE 0x00000001u
#define CYFLD_USBPD_TX_STATE_IDLE_MASKED__OFFSET 0x0000001bu
#define CYFLD_USBPD_TX_STATE_IDLE_MASKED__SIZE 0x00000001u
#define CYFLD_USBPD_RX_STATE_IDLE_MASKED__OFFSET 0x0000001cu
#define CYFLD_USBPD_RX_STATE_IDLE_MASKED__SIZE 0x00000001u
#define CYFLD_USBPD_SAR2_DONE_MASKED__OFFSET 0x0000001du
#define CYFLD_USBPD_SAR2_DONE_MASKED__SIZE 0x00000001u
#define CYFLD_USBPD_CMP_OUT2_DET_MASKED__OFFSET 0x0000001eu
#define CYFLD_USBPD_CMP_OUT2_DET_MASKED__SIZE 0x00000001u
#define CYREG_USBPD_INTR1_MASKED 0x400a0134u
#define CYFLD_USBPD_VCONN1_CHANGED_MASKED__OFFSET 0x00000000u
#define CYFLD_USBPD_VCONN1_CHANGED_MASKED__SIZE 0x00000001u
#define CYFLD_USBPD_CC1_CHANGED_MASKED__OFFSET 0x00000002u
#define CYFLD_USBPD_CC1_CHANGED_MASKED__SIZE 0x00000001u
#define CYFLD_USBPD_CC2_CHANGED_MASKED__OFFSET 0x00000003u
#define CYFLD_USBPD_CC2_CHANGED_MASKED__SIZE 0x00000001u
#define CYFLD_USBPD_VCMP_LA_CHANGED_MASKED__OFFSET 0x00000004u
#define CYFLD_USBPD_VCMP_LA_CHANGED_MASKED__SIZE 0x00000001u
#define CYFLD_USBPD_VCMP_UP_CHANGED_MASKED__OFFSET 0x00000005u
#define CYFLD_USBPD_VCMP_UP_CHANGED_MASKED__SIZE 0x00000001u
#define CYFLD_USBPD_VCMP_DN_CHANGED_MASKED__OFFSET 0x00000006u
#define CYFLD_USBPD_VCMP_DN_CHANGED_MASKED__SIZE 0x00000001u
#define CYFLD_USBPD_V5V_CHANGED_MASKED__OFFSET 0x00000007u
#define CYFLD_USBPD_V5V_CHANGED_MASKED__SIZE 0x00000001u
#define CYFLD_USBPD_CMP_OUT1_CHANGED_MASKED__OFFSET 0x00000008u
#define CYFLD_USBPD_CMP_OUT1_CHANGED_MASKED__SIZE 0x00000001u
#define CYFLD_USBPD_CMP_OUT2_CHANGED_MASKED__OFFSET 0x00000009u
#define CYFLD_USBPD_CMP_OUT2_CHANGED_MASKED__SIZE 0x00000001u
#define CYFLD_USBPD_HPDIN_CHANGED_MASKED__OFFSET 0x0000000au
#define CYFLD_USBPD_HPDIN_CHANGED_MASKED__SIZE 0x00000001u
#define CYFLD_USBPD_SPARE6_MASKED__OFFSET 0x0000000bu
#define CYFLD_USBPD_SPARE6_MASKED__SIZE 0x00000001u
#define CYFLD_USBPD_SPARE7_MASKED__OFFSET 0x0000000cu
#define CYFLD_USBPD_SPARE7_MASKED__SIZE 0x00000001u
#define CYREG_USBPD_DEBUG_CTRL 0x400a0138u
#define CYFLD_USBPD_RESET_RX__OFFSET 0x00000000u
#define CYFLD_USBPD_RESET_RX__SIZE 0x00000001u
#define CYFLD_USBPD_RX_MSG_CAL_STATE__OFFSET 0x00000001u
#define CYFLD_USBPD_RX_MSG_CAL_STATE__SIZE 0x00000003u
#define CYVAL_USBPD_RX_MSG_CAL_STATE_MSGSM_IDLE 0x00000000u
#define CYVAL_USBPD_RX_MSG_CAL_STATE_MSGSM_PRE_HDR 0x00000001u
#define CYVAL_USBPD_RX_MSG_CAL_STATE_MSGSM_HDR 0x00000002u
#define CYVAL_USBPD_RX_MSG_CAL_STATE_MSGSM_DATA 0x00000003u
#define CYVAL_USBPD_RX_MSG_CAL_STATE_MSGSM_CRC 0x00000004u
#define CYVAL_USBPD_RX_MSG_CAL_STATE_MSGSM_EOP 0x00000005u
#define CYVAL_USBPD_RX_MSG_CAL_STATE_MSGSM_STAT 0x00000006u
#define CYFLD_USBPD_RESET_TX__OFFSET 0x00000008u
#define CYFLD_USBPD_RESET_TX__SIZE 0x00000001u
#define CYFLD_USBPD_TX_MSG_STATE__OFFSET 0x00000009u
#define CYFLD_USBPD_TX_MSG_STATE__SIZE 0x00000003u
#define CYVAL_USBPD_TX_MSG_STATE_MSG_IDLE 0x00000000u
#define CYVAL_USBPD_TX_MSG_STATE_MSG_CAL 0x00000001u
#define CYVAL_USBPD_TX_MSG_STATE_MSG_SYN 0x00000002u
#define CYVAL_USBPD_TX_MSG_STATE_MSG_DOBJ 0x00000003u
#define CYVAL_USBPD_TX_MSG_STATE_MSG_CRC 0x00000004u
#define CYVAL_USBPD_TX_MSG_STATE_MSG_EOP 0x00000005u
#define CYVAL_USBPD_TX_MSG_STATE_MSG_RST 0x00000006u
#define CYVAL_USBPD_TX_MSG_STATE_MSG_BIDLE 0x00000007u
#define CYFLD_USBPD_TX_SRC_SEL_STATE__OFFSET 0x0000000du
#define CYFLD_USBPD_TX_SRC_SEL_STATE__SIZE 0x00000003u
#define CYVAL_USBPD_TX_SRC_SEL_STATE_IDLE_SEL 0x00000000u
#define CYVAL_USBPD_TX_SRC_SEL_STATE_CAL_SEL 0x00000001u
#define CYVAL_USBPD_TX_SRC_SEL_STATE_SYN_SEL 0x00000002u
#define CYVAL_USBPD_TX_SRC_SEL_STATE_KCHAR_SEL 0x00000003u
#define CYVAL_USBPD_TX_SRC_SEL_STATE_EOP_SEL 0x00000004u
#define CYVAL_USBPD_TX_SRC_SEL_STATE_RST_SEL 0x00000005u
#define CYFLD_USBPD_TX_PREAMBLE_CNT__OFFSET 0x00000010u
#define CYFLD_USBPD_TX_PREAMBLE_CNT__SIZE 0x00000006u
#define CYFLD_USBPD_EOP_VALUE__OFFSET 0x00000016u
#define CYFLD_USBPD_EOP_VALUE__SIZE 0x00000005u
#define CYFLD_USBPD_ENABLE_EXIT_ON_EOP__OFFSET 0x0000001bu
#define CYFLD_USBPD_ENABLE_EXIT_ON_EOP__SIZE 0x00000001u
#define CYREG_USBPD_DEBUG_CC_0 0x400a013cu
#define CYFLD_USBPD_TX_FIRST_BIT_LEVEL__OFFSET 0x00000000u
#define CYFLD_USBPD_TX_FIRST_BIT_LEVEL__SIZE 0x00000001u
#define CYFLD_USBPD_LOOP_BACK_NO_BMC__OFFSET 0x00000001u
#define CYFLD_USBPD_LOOP_BACK_NO_BMC__SIZE 0x00000001u
#define CYFLD_USBPD_LOOP_BACK_WITH_BMC__OFFSET 0x00000002u
#define CYFLD_USBPD_LOOP_BACK_WITH_BMC__SIZE 0x00000001u
#define CYFLD_USBPD_EXT_LOOP_BACK__OFFSET 0x00000003u
#define CYFLD_USBPD_EXT_LOOP_BACK__SIZE 0x00000001u
#define CYFLD_USBPD_RX_CLEAR__OFFSET 0x00000004u
#define CYFLD_USBPD_RX_CLEAR__SIZE 0x00000001u
#define CYFLD_USBPD_TX_CLEAR__OFFSET 0x00000005u
#define CYFLD_USBPD_TX_CLEAR__SIZE 0x00000001u
#define CYFLD_USBPD_TX_CC_DRIVE_SRC__OFFSET 0x00000006u
#define CYFLD_USBPD_TX_CC_DRIVE_SRC__SIZE 0x00000001u
#define CYFLD_USBPD_TX_CC_DATA__OFFSET 0x00000007u
#define CYFLD_USBPD_TX_CC_DATA__SIZE 0x00000001u
#define CYFLD_USBPD_DEBUG_SEL__OFFSET 0x00000008u
#define CYFLD_USBPD_DEBUG_SEL__SIZE 0x00000005u
#define CYFLD_USBPD_RX_CC_DATA_VALID_DIS__OFFSET 0x0000000du
#define CYFLD_USBPD_RX_CC_DATA_VALID_DIS__SIZE 0x00000001u
#define CYFLD_USBPD_TX_DELAY_FALLN_RISE__OFFSET 0x0000000eu
#define CYFLD_USBPD_TX_DELAY_FALLN_RISE__SIZE 0x00000001u
#define CYFLD_USBPD_TX_DELAY_VALUE__OFFSET 0x0000000fu
#define CYFLD_USBPD_TX_DELAY_VALUE__SIZE 0x00000004u
#define CYFLD_USBPD_DEBUG_OUT__OFFSET 0x00000014u
#define CYFLD_USBPD_DEBUG_OUT__SIZE 0x00000008u
#define CYFLD_USBPD_IREF_SEL__OFFSET 0x0000001cu
#define CYFLD_USBPD_IREF_SEL__SIZE 0x00000001u
#define CYFLD_USBPD_DISABLE_BIST_EOP__OFFSET 0x0000001du
#define CYFLD_USBPD_DISABLE_BIST_EOP__SIZE 0x00000001u
#define CYFLD_USBPD_VBUS_C_SWAP_SOURCE_SEL__OFFSET 0x0000001eu
#define CYFLD_USBPD_VBUS_C_SWAP_SOURCE_SEL__SIZE 0x00000001u
#define CYFLD_USBPD_CSA_BW_1__OFFSET 0x0000001fu
#define CYFLD_USBPD_CSA_BW_1__SIZE 0x00000001u
#define CYREG_USBPD_DEBUG_CC_1 0x400a0140u
#define CYFLD_USBPD_NUM_PREAMBLE_AVG__OFFSET 0x00000000u
#define CYFLD_USBPD_NUM_PREAMBLE_AVG__SIZE 0x00000003u
#define CYVAL_USBPD_NUM_PREAMBLE_AVG_FOUR_PREAM_AVG0 0x00000000u
#define CYVAL_USBPD_NUM_PREAMBLE_AVG_FOUR_PREAM_AVG1 0x00000001u
#define CYVAL_USBPD_NUM_PREAMBLE_AVG_FOUR_PREAM_AVG2 0x00000002u
#define CYVAL_USBPD_NUM_PREAMBLE_AVG_EIGHT_PREAM_AVG 0x00000003u
#define CYVAL_USBPD_NUM_PREAMBLE_AVG_SIXTEEN_PREAM_AVG 0x00000004u
#define CYVAL_USBPD_NUM_PREAMBLE_AVG_THIRTY_TWO_PREAM_AVG 0x00000005u
#define CYVAL_USBPD_NUM_PREAMBLE_AVG_RESERVED6_PREAM_AVG 0x00000006u
#define CYVAL_USBPD_NUM_PREAMBLE_AVG_RESERVED7_PREAM_AVG 0x00000007u
#define CYFLD_USBPD_NUM_TRANS_AVG__OFFSET 0x00000003u
#define CYFLD_USBPD_NUM_TRANS_AVG__SIZE 0x00000006u
#define CYFLD_USBPD_RX_DISABLE_AUTO_ADJ__OFFSET 0x00000009u
#define CYFLD_USBPD_RX_DISABLE_AUTO_ADJ__SIZE 0x00000001u
#define CYFLD_USBPD_RX_UI_PERIOD__OFFSET 0x0000000au
#define CYFLD_USBPD_RX_UI_PERIOD__SIZE 0x00000008u
#define CYFLD_USBPD_SPARE2__OFFSET 0x00000012u
#define CYFLD_USBPD_SPARE2__SIZE 0x0000000bu
#define CYREG_USBPD_DEBUG_CC_2 0x400a0144u
#define CYFLD_USBPD_RX_DELTA_POLARITY__OFFSET 0x00000000u
#define CYFLD_USBPD_RX_DELTA_POLARITY__SIZE 0x00000001u
#define CYFLD_USBPD_DIS_CC_MON_AUTO_CRC__OFFSET 0x00000001u
#define CYFLD_USBPD_DIS_CC_MON_AUTO_CRC__SIZE 0x00000001u
#define CYFLD_USBPD_RESET_RX_ON_EOP__OFFSET 0x00000002u
#define CYFLD_USBPD_RESET_RX_ON_EOP__SIZE 0x00000001u
#define CYFLD_USBPD_RX_IGNR_TRANS_NUM__OFFSET 0x00000006u
#define CYFLD_USBPD_RX_IGNR_TRANS_NUM__SIZE 0x00000006u
#define CYFLD_USBPD_EXPECTED_HEADER_MASK__OFFSET 0x00000010u
#define CYFLD_USBPD_EXPECTED_HEADER_MASK__SIZE 0x00000010u
#define CYREG_USBPD_DEBUG_SPARE_INTR_CFG 0x400a0148u
#define CYFLD_USBPD_SPARE6_CFG__OFFSET 0x00000000u
#define CYFLD_USBPD_SPARE6_CFG__SIZE 0x00000002u
#define CYVAL_USBPD_SPARE6_CFG_POS_EDG_DIS_NEG_EDG_DIS 0x00000000u
#define CYVAL_USBPD_SPARE6_CFG_POS_EDG_DIS_NEG_EDG_EN 0x00000001u
#define CYVAL_USBPD_SPARE6_CFG_POS_EDG_EN_NEG_EDG_DIS 0x00000002u
#define CYVAL_USBPD_SPARE6_CFG_POS_EDG_EN_NEG_EDG_EN 0x00000003u
#define CYFLD_USBPD_SPARE6_FILT_EN__OFFSET 0x00000002u
#define CYFLD_USBPD_SPARE6_FILT_EN__SIZE 0x00000001u
#define CYFLD_USBPD_SPARE6_FILT_SEL__OFFSET 0x00000003u
#define CYFLD_USBPD_SPARE6_FILT_SEL__SIZE 0x00000003u
#define CYFLD_USBPD_SPARE7_CFG__OFFSET 0x00000006u
#define CYFLD_USBPD_SPARE7_CFG__SIZE 0x00000002u
#define CYVAL_USBPD_SPARE7_CFG_POS_EDG_DIS_NEG_EDG_DIS 0x00000000u
#define CYVAL_USBPD_SPARE7_CFG_POS_EDG_DIS_NEG_EDG_EN 0x00000001u
#define CYVAL_USBPD_SPARE7_CFG_POS_EDG_EN_NEG_EDG_DIS 0x00000002u
#define CYVAL_USBPD_SPARE7_CFG_POS_EDG_EN_NEG_EDG_EN 0x00000003u
#define CYFLD_USBPD_SPARE7_FILT_EN__OFFSET 0x00000008u
#define CYFLD_USBPD_SPARE7_FILT_EN__SIZE 0x00000001u
#define CYFLD_USBPD_SPARE7_FILT_SEL__OFFSET 0x00000009u
#define CYFLD_USBPD_SPARE7_FILT_SEL__SIZE 0x00000003u
#define CYREG_USBPD_INTR2 0x400a014cu
#define CYFLD_USBPD_UI_CAL_DONE__OFFSET 0x00000000u
#define CYFLD_USBPD_UI_CAL_DONE__SIZE 0x00000001u
#define CYFLD_USBPD_PULSE_MIN_VIOLATED__OFFSET 0x00000001u
#define CYFLD_USBPD_PULSE_MIN_VIOLATED__SIZE 0x00000001u
#define CYFLD_USBPD_PULSE_MAX_VIOLATED__OFFSET 0x00000002u
#define CYFLD_USBPD_PULSE_MAX_VIOLATED__SIZE 0x00000001u
#define CYFLD_USBPD_HPD_IRQ__OFFSET 0x00000003u
#define CYFLD_USBPD_HPD_IRQ__SIZE 0x00000001u
#define CYFLD_USBPD_HPD_PLUGED__OFFSET 0x00000004u
#define CYFLD_USBPD_HPD_PLUGED__SIZE 0x00000001u
#define CYFLD_USBPD_HPD_UNPLUGED__OFFSET 0x00000005u
#define CYFLD_USBPD_HPD_UNPLUGED__SIZE 0x00000001u
#define CYFLD_USBPD_HPD_UNSTABLE__OFFSET 0x00000006u
#define CYFLD_USBPD_HPD_UNSTABLE__SIZE 0x00000001u
#define CYFLD_USBPD_HPD_QUEUE__OFFSET 0x00000007u
#define CYFLD_USBPD_HPD_QUEUE__SIZE 0x00000001u
#define CYFLD_USBPD_HPDT_COMMAND_DONE__OFFSET 0x00000008u
#define CYFLD_USBPD_HPDT_COMMAND_DONE__SIZE 0x00000001u
#define CYFLD_USBPD_EXTENDED_MSG_DET__OFFSET 0x00000009u
#define CYFLD_USBPD_EXTENDED_MSG_DET__SIZE 0x00000001u
#define CYFLD_USBPD_CHUNK_DET__OFFSET 0x0000000au
#define CYFLD_USBPD_CHUNK_DET__SIZE 0x00000001u
#define CYFLD_USBPD_RX_SRAM_OVER_FLOW__OFFSET 0x0000000bu
#define CYFLD_USBPD_RX_SRAM_OVER_FLOW__SIZE 0x00000001u
#define CYFLD_USBPD_TX_SRAM_UNDER_FLOW__OFFSET 0x0000000cu
#define CYFLD_USBPD_TX_SRAM_UNDER_FLOW__SIZE 0x00000001u
#define CYFLD_USBPD_SPARE3__OFFSET 0x0000000du
#define CYFLD_USBPD_SPARE3__SIZE 0x00000001u
#define CYFLD_USBPD_SPARE4__OFFSET 0x0000000eu
#define CYFLD_USBPD_SPARE4__SIZE 0x00000001u
#define CYFLD_USBPD_SPARE5__OFFSET 0x0000000fu
#define CYFLD_USBPD_SPARE5__SIZE 0x00000001u
#define CYFLD_USBPD_NGDO_C_SPACING_DONE__OFFSET 0x00000010u
#define CYFLD_USBPD_NGDO_C_SPACING_DONE__SIZE 0x00000001u
#define CYFLD_USBPD_NGDO_P_SPACING_DONE__OFFSET 0x00000011u
#define CYFLD_USBPD_NGDO_P_SPACING_DONE__SIZE 0x00000001u
#define CYFLD_USBPD_VREG20V_SWITCH_DONE__OFFSET 0x00000012u
#define CYFLD_USBPD_VREG20V_SWITCH_DONE__SIZE 0x00000001u
#define CYFLD_USBPD_VDDD_SW_SWITCH_DONE__OFFSET 0x00000013u
#define CYFLD_USBPD_VDDD_SW_SWITCH_DONE__SIZE 0x00000001u
#define CYFLD_USBPD_VSWAP_VBUS_LESS_5_DONE__OFFSET 0x00000014u
#define CYFLD_USBPD_VSWAP_VBUS_LESS_5_DONE__SIZE 0x00000001u
#define CYFLD_USBPD_SWAP_IRQ__OFFSET 0x00000015u
#define CYFLD_USBPD_SWAP_IRQ__SIZE 0x00000001u
#define CYFLD_USBPD_SWAP_PLUGED__OFFSET 0x00000016u
#define CYFLD_USBPD_SWAP_PLUGED__SIZE 0x00000001u
#define CYFLD_USBPD_SWAP_UNPLUGED__OFFSET 0x00000017u
#define CYFLD_USBPD_SWAP_UNPLUGED__SIZE 0x00000001u
#define CYFLD_USBPD_SWAP_UNSTABLE__OFFSET 0x00000018u
#define CYFLD_USBPD_SWAP_UNSTABLE__SIZE 0x00000001u
#define CYFLD_USBPD_SWAP_QUEUE__OFFSET 0x00000019u
#define CYFLD_USBPD_SWAP_QUEUE__SIZE 0x00000001u
#define CYFLD_USBPD_SWAP_COMMAND_DONE__OFFSET 0x0000001au
#define CYFLD_USBPD_SWAP_COMMAND_DONE__SIZE 0x00000001u
#define CYREG_USBPD_INTR2_SET 0x400a0150u
#define CYREG_USBPD_INTR2_MASK 0x400a0154u
#define CYFLD_USBPD_UI_CAL_DONE_MASK__OFFSET 0x00000000u
#define CYFLD_USBPD_UI_CAL_DONE_MASK__SIZE 0x00000001u
#define CYFLD_USBPD_PULSE_MIN_VIOLATED_MASK__OFFSET 0x00000001u
#define CYFLD_USBPD_PULSE_MIN_VIOLATED_MASK__SIZE 0x00000001u
#define CYFLD_USBPD_PULSE_MAX_VIOLATED_MASK__OFFSET 0x00000002u
#define CYFLD_USBPD_PULSE_MAX_VIOLATED_MASK__SIZE 0x00000001u
#define CYFLD_USBPD_HPD_IRQ_MASK__OFFSET 0x00000003u
#define CYFLD_USBPD_HPD_IRQ_MASK__SIZE 0x00000001u
#define CYFLD_USBPD_HPD_PLUGED_MASK__OFFSET 0x00000004u
#define CYFLD_USBPD_HPD_PLUGED_MASK__SIZE 0x00000001u
#define CYFLD_USBPD_HPD_UNPLUGED_MASK__OFFSET 0x00000005u
#define CYFLD_USBPD_HPD_UNPLUGED_MASK__SIZE 0x00000001u
#define CYFLD_USBPD_HPD_UNSTABLE_MASK__OFFSET 0x00000006u
#define CYFLD_USBPD_HPD_UNSTABLE_MASK__SIZE 0x00000001u
#define CYFLD_USBPD_HPD_QUEUE_MASK__OFFSET 0x00000007u
#define CYFLD_USBPD_HPD_QUEUE_MASK__SIZE 0x00000001u
#define CYFLD_USBPD_HPDT_COMMAND_DONE_MASK__OFFSET 0x00000008u
#define CYFLD_USBPD_HPDT_COMMAND_DONE_MASK__SIZE 0x00000001u
#define CYFLD_USBPD_EXTENDED_MSG_DET_MASK__OFFSET 0x00000009u
#define CYFLD_USBPD_EXTENDED_MSG_DET_MASK__SIZE 0x00000001u
#define CYFLD_USBPD_CHUNK_DET_MASK__OFFSET 0x0000000au
#define CYFLD_USBPD_CHUNK_DET_MASK__SIZE 0x00000001u
#define CYFLD_USBPD_RX_SRAM_OVER_FLOW_MASK__OFFSET 0x0000000bu
#define CYFLD_USBPD_RX_SRAM_OVER_FLOW_MASK__SIZE 0x00000001u
#define CYFLD_USBPD_TX_SRAM_UNDER_FLOW_MASK__OFFSET 0x0000000cu
#define CYFLD_USBPD_TX_SRAM_UNDER_FLOW_MASK__SIZE 0x00000001u
#define CYFLD_USBPD_SPARE3_MASK__OFFSET 0x0000000du
#define CYFLD_USBPD_SPARE3_MASK__SIZE 0x00000001u
#define CYFLD_USBPD_SPARE4_MASK__OFFSET 0x0000000eu
#define CYFLD_USBPD_SPARE4_MASK__SIZE 0x00000001u
#define CYFLD_USBPD_SPARE5_MASK__OFFSET 0x0000000fu
#define CYFLD_USBPD_SPARE5_MASK__SIZE 0x00000001u
#define CYFLD_USBPD_NGDO_C_SPACING_DONE_MASK__OFFSET 0x00000010u
#define CYFLD_USBPD_NGDO_C_SPACING_DONE_MASK__SIZE 0x00000001u
#define CYFLD_USBPD_NGDO_P_SPACING_DONE_MASK__OFFSET 0x00000011u
#define CYFLD_USBPD_NGDO_P_SPACING_DONE_MASK__SIZE 0x00000001u
#define CYFLD_USBPD_VREG20V_SWITCH_DONE_MASK__OFFSET 0x00000012u
#define CYFLD_USBPD_VREG20V_SWITCH_DONE_MASK__SIZE 0x00000001u
#define CYFLD_USBPD_VDDD_SW_SWITCH_DONE_MASK__OFFSET 0x00000013u
#define CYFLD_USBPD_VDDD_SW_SWITCH_DONE_MASK__SIZE 0x00000001u
#define CYFLD_USBPD_VSWAP_VBUS_LESS_5_DONE_MASK__OFFSET 0x00000014u
#define CYFLD_USBPD_VSWAP_VBUS_LESS_5_DONE_MASK__SIZE 0x00000001u
#define CYFLD_USBPD_SWAP_IRQ_MASK__OFFSET 0x00000015u
#define CYFLD_USBPD_SWAP_IRQ_MASK__SIZE 0x00000001u
#define CYFLD_USBPD_SWAP_PLUGED_MASK__OFFSET 0x00000016u
#define CYFLD_USBPD_SWAP_PLUGED_MASK__SIZE 0x00000001u
#define CYFLD_USBPD_SWAP_UNPLUGED_MASK__OFFSET 0x00000017u
#define CYFLD_USBPD_SWAP_UNPLUGED_MASK__SIZE 0x00000001u
#define CYFLD_USBPD_SWAP_UNSTABLE_MASK__OFFSET 0x00000018u
#define CYFLD_USBPD_SWAP_UNSTABLE_MASK__SIZE 0x00000001u
#define CYFLD_USBPD_SWAP_QUEUE_MASK__OFFSET 0x00000019u
#define CYFLD_USBPD_SWAP_QUEUE_MASK__SIZE 0x00000001u
#define CYFLD_USBPD_SWAP_COMMAND_DONE_MASK__OFFSET 0x0000001au
#define CYFLD_USBPD_SWAP_COMMAND_DONE_MASK__SIZE 0x00000001u
#define CYREG_USBPD_INTR2_MASKED 0x400a0158u
#define CYFLD_USBPD_UI_CAL_DONE_MASKED__OFFSET 0x00000000u
#define CYFLD_USBPD_UI_CAL_DONE_MASKED__SIZE 0x00000001u
#define CYFLD_USBPD_PULSE_MIN_VIOLATED_MASKED__OFFSET 0x00000001u
#define CYFLD_USBPD_PULSE_MIN_VIOLATED_MASKED__SIZE 0x00000001u
#define CYFLD_USBPD_PULSE_MAX_VIOLATED_MASKED__OFFSET 0x00000002u
#define CYFLD_USBPD_PULSE_MAX_VIOLATED_MASKED__SIZE 0x00000001u
#define CYFLD_USBPD_HPD_IRQ_MASKED__OFFSET 0x00000003u
#define CYFLD_USBPD_HPD_IRQ_MASKED__SIZE 0x00000001u
#define CYFLD_USBPD_HPD_PLUGED_MASKED__OFFSET 0x00000004u
#define CYFLD_USBPD_HPD_PLUGED_MASKED__SIZE 0x00000001u
#define CYFLD_USBPD_HPD_UNPLUGED_MASKED__OFFSET 0x00000005u
#define CYFLD_USBPD_HPD_UNPLUGED_MASKED__SIZE 0x00000001u
#define CYFLD_USBPD_HPD_UNSTABLE_MASKED__OFFSET 0x00000006u
#define CYFLD_USBPD_HPD_UNSTABLE_MASKED__SIZE 0x00000001u
#define CYFLD_USBPD_HPD_QUEUE_MASKED__OFFSET 0x00000007u
#define CYFLD_USBPD_HPD_QUEUE_MASKED__SIZE 0x00000001u
#define CYFLD_USBPD_HPDT_COMMAND_DONE_MASKED__OFFSET 0x00000008u
#define CYFLD_USBPD_HPDT_COMMAND_DONE_MASKED__SIZE 0x00000001u
#define CYFLD_USBPD_EXTENDED_MSG_DET_MASKED__OFFSET 0x00000009u
#define CYFLD_USBPD_EXTENDED_MSG_DET_MASKED__SIZE 0x00000001u
#define CYFLD_USBPD_CHUNK_DET_MASKED__OFFSET 0x0000000au
#define CYFLD_USBPD_CHUNK_DET_MASKED__SIZE 0x00000001u
#define CYFLD_USBPD_RX_SRAM_OVER_FLOW_MASKED__OFFSET 0x0000000bu
#define CYFLD_USBPD_RX_SRAM_OVER_FLOW_MASKED__SIZE 0x00000001u
#define CYFLD_USBPD_TX_SRAM_UNDER_FLOW_MASKED__OFFSET 0x0000000cu
#define CYFLD_USBPD_TX_SRAM_UNDER_FLOW_MASKED__SIZE 0x00000001u
#define CYFLD_USBPD_SPARE3_MASKED__OFFSET 0x0000000du
#define CYFLD_USBPD_SPARE3_MASKED__SIZE 0x00000001u
#define CYFLD_USBPD_SPARE4_MASKED__OFFSET 0x0000000eu
#define CYFLD_USBPD_SPARE4_MASKED__SIZE 0x00000001u
#define CYFLD_USBPD_SPARE5_MASKED__OFFSET 0x0000000fu
#define CYFLD_USBPD_SPARE5_MASKED__SIZE 0x00000001u
#define CYFLD_USBPD_NGDO_C_SPACING_DONE_MASKED__OFFSET 0x00000010u
#define CYFLD_USBPD_NGDO_C_SPACING_DONE_MASKED__SIZE 0x00000001u
#define CYFLD_USBPD_NGDO_P_SPACING_DONE_MASKED__OFFSET 0x00000011u
#define CYFLD_USBPD_NGDO_P_SPACING_DONE_MASKED__SIZE 0x00000001u
#define CYFLD_USBPD_VREG20V_SWITCH_DONE_MASKED__OFFSET 0x00000012u
#define CYFLD_USBPD_VREG20V_SWITCH_DONE_MASKED__SIZE 0x00000001u
#define CYFLD_USBPD_VDDD_SW_SWITCH_DONE_MASKED__OFFSET 0x00000013u
#define CYFLD_USBPD_VDDD_SW_SWITCH_DONE_MASKED__SIZE 0x00000001u
#define CYFLD_USBPD_VSWAP_VBUS_LESS_5_DONE_MASKED__OFFSET 0x00000014u
#define CYFLD_USBPD_VSWAP_VBUS_LESS_5_DONE_MASKED__SIZE 0x00000001u
#define CYFLD_USBPD_SWAP_IRQ_MASKED__OFFSET 0x00000015u
#define CYFLD_USBPD_SWAP_IRQ_MASKED__SIZE 0x00000001u
#define CYFLD_USBPD_SWAP_PLUGED_MASKED__OFFSET 0x00000016u
#define CYFLD_USBPD_SWAP_PLUGED_MASKED__SIZE 0x00000001u
#define CYFLD_USBPD_SWAP_UNPLUGED_MASKED__OFFSET 0x00000017u
#define CYFLD_USBPD_SWAP_UNPLUGED_MASKED__SIZE 0x00000001u
#define CYFLD_USBPD_SWAP_UNSTABLE_MASKED__OFFSET 0x00000018u
#define CYFLD_USBPD_SWAP_UNSTABLE_MASKED__SIZE 0x00000001u
#define CYFLD_USBPD_SWAP_QUEUE_MASKED__OFFSET 0x00000019u
#define CYFLD_USBPD_SWAP_QUEUE_MASKED__SIZE 0x00000001u
#define CYFLD_USBPD_SWAP_COMMAND_DONE_MASKED__OFFSET 0x0000001au
#define CYFLD_USBPD_SWAP_COMMAND_DONE_MASKED__SIZE 0x00000001u
#define CYREG_USBPD_HPD_CTRL1 0x400a015cu
#define CYFLD_USBPD_IRQ_MIN__OFFSET 0x00000000u
#define CYFLD_USBPD_IRQ_MIN__SIZE 0x0000000cu
#define CYFLD_USBPD_IRQ_MAX__OFFSET 0x0000000cu
#define CYFLD_USBPD_IRQ_MAX__SIZE 0x0000000cu
#define CYFLD_USBPD_FLUSH_QUEUE__OFFSET 0x00000018u
#define CYFLD_USBPD_FLUSH_QUEUE__SIZE 0x00000001u
#define CYFLD_USBPD_LOOPBACK_EN__OFFSET 0x0000001eu
#define CYFLD_USBPD_LOOPBACK_EN__SIZE 0x00000001u
#define CYFLD_USBPD_RESET_HPD_STATE__OFFSET 0x0000001fu
#define CYFLD_USBPD_RESET_HPD_STATE__SIZE 0x00000001u
#define CYREG_USBPD_HPD_CTRL2 0x400a0160u
#define CYFLD_USBPD_GLITCH_WIDTH_HIGH__OFFSET 0x00000000u
#define CYFLD_USBPD_GLITCH_WIDTH_HIGH__SIZE 0x0000000cu
#define CYFLD_USBPD_GLITCH_WIDTH_LOW__OFFSET 0x0000000cu
#define CYFLD_USBPD_GLITCH_WIDTH_LOW__SIZE 0x0000000cu
#define CYREG_USBPD_HPD_CTRL3 0x400a0164u
#define CYFLD_USBPD_STABLE_HIGH__OFFSET 0x00000000u
#define CYFLD_USBPD_STABLE_HIGH__SIZE 0x0000000cu
#define CYFLD_USBPD_STABLE_LOW__OFFSET 0x0000000cu
#define CYFLD_USBPD_STABLE_LOW__SIZE 0x0000000cu
#define CYREG_USBPD_HPD_CTRL4 0x400a0168u
#define CYFLD_USBPD_IRQ_SPACING__OFFSET 0x00000000u
#define CYFLD_USBPD_IRQ_SPACING__SIZE 0x0000000cu
#define CYREG_USBPD_HPD_CTRL5 0x400a016cu
#define CYFLD_USBPD_LONG_HIGH__OFFSET 0x00000000u
#define CYFLD_USBPD_LONG_HIGH__SIZE 0x00000010u
#define CYFLD_USBPD_LONG_LOW__OFFSET 0x00000010u
#define CYFLD_USBPD_LONG_LOW__SIZE 0x00000010u
#define CYREG_USBPD_HPD_QUEUE 0x400a0170u
#define CYFLD_USBPD_DATA_OUT__OFFSET 0x00000000u
#define CYFLD_USBPD_DATA_OUT__SIZE 0x00000008u
#define CYREG_USBPD_HPDT_CTRL1 0x400a0174u
#define CYFLD_USBPD_IRQ_WIDTH__OFFSET 0x00000000u
#define CYFLD_USBPD_IRQ_WIDTH__SIZE 0x0000000cu
#define CYFLD_USBPD_SET_IRQ_DELAY__OFFSET 0x0000000cu
#define CYFLD_USBPD_SET_IRQ_DELAY__SIZE 0x0000000cu
#define CYFLD_USBPD_DEFAULT_LEVEL__OFFSET 0x00000018u
#define CYFLD_USBPD_DEFAULT_LEVEL__SIZE 0x00000001u
#define CYFLD_USBPD_DATA_SOURCE_SELECT__OFFSET 0x00000019u
#define CYFLD_USBPD_DATA_SOURCE_SELECT__SIZE 0x00000001u
#define CYFLD_USBPD_DATA_SOURCE__OFFSET 0x0000001au
#define CYFLD_USBPD_DATA_SOURCE__SIZE 0x00000001u
#define CYFLD_USBPD_COMMAND__OFFSET 0x0000001bu
#define CYFLD_USBPD_COMMAND__SIZE 0x00000002u
#define CYFLD_USBPD_COMMAND_START__OFFSET 0x0000001du
#define CYFLD_USBPD_COMMAND_START__SIZE 0x00000001u
#define CYFLD_USBPD_RESET_HPDT_STATE__OFFSET 0x0000001eu
#define CYFLD_USBPD_RESET_HPDT_STATE__SIZE 0x00000001u
#define CYREG_USBPD_HPDT_CTRL2 0x400a0178u
#define CYFLD_USBPD_SET_LOW_DELAY__OFFSET 0x00000000u
#define CYFLD_USBPD_SET_LOW_DELAY__SIZE 0x0000000cu
#define CYFLD_USBPD_SET_HIGH_DELAY__OFFSET 0x0000000cu
#define CYFLD_USBPD_SET_HIGH_DELAY__SIZE 0x0000000cu
#define CYFLD_USBPD_DEFAULT_OE__OFFSET 0x00000018u
#define CYFLD_USBPD_DEFAULT_OE__SIZE 0x00000001u
#define CYFLD_USBPD_OE_SOURCE_SELECT__OFFSET 0x00000019u
#define CYFLD_USBPD_OE_SOURCE_SELECT__SIZE 0x00000001u
#define CYFLD_USBPD_HPDT_DEBUG_SEL__OFFSET 0x0000001au
#define CYFLD_USBPD_HPDT_DEBUG_SEL__SIZE 0x00000002u
#define CYFLD_USBPD_HPDT_DEBUG_OUT__OFFSET 0x0000001cu
#define CYFLD_USBPD_HPDT_DEBUG_OUT__SIZE 0x00000004u
#define CYREG_USBPD_SWAP_CTRL0 0x400a017cu
#define CYFLD_USBPD_SWAPT_SOURCE_SEL__OFFSET 0x00000000u
#define CYFLD_USBPD_SWAPT_SOURCE_SEL__SIZE 0x00000002u
#define CYVAL_USBPD_SWAPT_SOURCE_SEL_CPU_SOURCE 0x00000000u
#define CYVAL_USBPD_SWAPT_SOURCE_SEL_GPIO_SOURCE 0x00000001u
#define CYVAL_USBPD_SWAPT_SOURCE_SEL_ADC1_CMP_OUT 0x00000002u
#define CYVAL_USBPD_SWAPT_SOURCE_SEL_ADC2_CMP_OUT 0x00000003u
#define CYFLD_USBPD_SWAPR_SOURCE_SEL__OFFSET 0x00000002u
#define CYFLD_USBPD_SWAPR_SOURCE_SEL__SIZE 0x00000001u
#define CYFLD_USBPD_SWAPT_POLARITY__OFFSET 0x00000003u
#define CYFLD_USBPD_SWAPT_POLARITY__SIZE 0x00000001u
#define CYFLD_USBPD_SWAPT_EN_CC1_PULLDN__OFFSET 0x00000004u
#define CYFLD_USBPD_SWAPT_EN_CC1_PULLDN__SIZE 0x00000001u
#define CYFLD_USBPD_SWAPT_EN_CC2_PULLDN__OFFSET 0x00000005u
#define CYFLD_USBPD_SWAPT_EN_CC2_PULLDN__SIZE 0x00000001u
#define CYFLD_USBPD_SWAPT_TO_GPIO1_EN__OFFSET 0x00000006u
#define CYFLD_USBPD_SWAPT_TO_GPIO1_EN__SIZE 0x00000001u
#define CYFLD_USBPD_SWAPT_TO_GPIO2_EN__OFFSET 0x00000007u
#define CYFLD_USBPD_SWAPT_TO_GPIO2_EN__SIZE 0x00000001u
#define CYFLD_USBPD_SWAP_ENABLED__OFFSET 0x0000001fu
#define CYFLD_USBPD_SWAP_ENABLED__SIZE 0x00000001u
#define CYREG_USBPD_SWAP_CTRL1 0x400a0180u
#define CYFLD_USBPD_RESET_SWAP_STATE__OFFSET 0x0000001fu
#define CYFLD_USBPD_RESET_SWAP_STATE__SIZE 0x00000001u
#define CYREG_USBPD_SWAP_CTRL2 0x400a0184u
#define CYREG_USBPD_SWAP_CTRL3 0x400a0188u
#define CYREG_USBPD_SWAP_CTRL4 0x400a018cu
#define CYREG_USBPD_SWAP_CTRL5 0x400a0190u
#define CYREG_USBPD_SWAP_QUEUE 0x400a0194u
#define CYREG_USBPD_SWAPT_CTRL1 0x400a0198u
#define CYFLD_USBPD_RESET_SWAPT_STATE__OFFSET 0x0000001eu
#define CYFLD_USBPD_RESET_SWAPT_STATE__SIZE 0x00000001u
#define CYREG_USBPD_SWAPT_CTRL2 0x400a019cu
#define CYFLD_USBPD_SWAPT_DEBUG_SEL__OFFSET 0x0000001au
#define CYFLD_USBPD_SWAPT_DEBUG_SEL__SIZE 0x00000002u
#define CYFLD_USBPD_SWAPT_DEBUG_OUT__OFFSET 0x0000001cu
#define CYFLD_USBPD_SWAPT_DEBUG_OUT__SIZE 0x00000004u
#define CYREG_USBPD_ADC1_SAR_CTRL 0x400a01a0u
#define CYFLD_USBPD_SAR_EN__OFFSET 0x00000000u
#define CYFLD_USBPD_SAR_EN__SIZE 0x00000001u
#define CYFLD_USBPD_MID_VAL__OFFSET 0x00000008u
#define CYFLD_USBPD_MID_VAL__SIZE 0x00000008u
#define CYFLD_USBPD_SAR_OUT__OFFSET 0x00000010u
#define CYFLD_USBPD_SAR_OUT__SIZE 0x00000008u
#define CYFLD_USBPD_INTR_CMP_SEL__OFFSET 0x00000018u
#define CYFLD_USBPD_INTR_CMP_SEL__SIZE 0x00000002u
#define CYVAL_USBPD_INTR_CMP_SEL_DIS_INT0_CMP_OUT_DET_1 0x00000000u
#define CYVAL_USBPD_INTR_CMP_SEL_EN_RISE_EDGE_1 0x00000001u
#define CYVAL_USBPD_INTR_CMP_SEL_EN_FALL_EDGE_1 0x00000002u
#define CYVAL_USBPD_INTR_CMP_SEL_EN_BOTH_EDGE_1 0x00000003u
#define CYFLD_USBPD_CMP_OUT_TO_GPIO_FILT_SEL__OFFSET 0x0000001au
#define CYFLD_USBPD_CMP_OUT_TO_GPIO_FILT_SEL__SIZE 0x00000003u
#define CYREG_USBPD_ADC1_CTRL 0x400a01a4u
#define CYFLD_USBPD_DAC_CNTRL__OFFSET 0x00000000u
#define CYFLD_USBPD_DAC_CNTRL__SIZE 0x00000008u
#define CYFLD_USBPD_DFT_MUXSEL__OFFSET 0x00000008u
#define CYFLD_USBPD_DFT_MUXSEL__SIZE 0x00000001u
#define CYFLD_USBPD_ADC_ISO_N__OFFSET 0x00000009u
#define CYFLD_USBPD_ADC_ISO_N__SIZE 0x00000001u
#define CYFLD_USBPD_CMP_OUT__OFFSET 0x0000000fu
#define CYFLD_USBPD_CMP_OUT__SIZE 0x00000001u
#define CYFLD_USBPD_VSEL__OFFSET 0x00000011u
#define CYFLD_USBPD_VSEL__SIZE 0x00000002u
#define CYVAL_USBPD_VSEL_ANA_IN1_AMUX_A_1 0x00000000u
#define CYVAL_USBPD_VSEL_ANA_IN2_AMUX_A_1 0x00000001u
#define CYVAL_USBPD_VSEL_BAND_GAP_1 0x00000002u
#define CYVAL_USBPD_VSEL_BJT_1 0x00000003u
#define CYFLD_USBPD_PD_LV__OFFSET 0x0000001fu
#define CYFLD_USBPD_PD_LV__SIZE 0x00000001u
#define CYREG_USBPD_ADC2_SAR_CTRL 0x400a01a8u
#define CYREG_USBPD_ADC2_CTRL 0x400a01acu
#define CYREG_USBPD_CC_CTRL_0 0x400a01b0u
#define CYFLD_USBPD_TX_EN__OFFSET 0x00000000u
#define CYFLD_USBPD_TX_EN__SIZE 0x00000001u
#define CYFLD_USBPD_RX_EN__OFFSET 0x00000001u
#define CYFLD_USBPD_RX_EN__SIZE 0x00000001u
#define CYFLD_USBPD_CC_1V2__OFFSET 0x00000002u
#define CYFLD_USBPD_CC_1V2__SIZE 0x00000001u
#define CYFLD_USBPD_CMP_EN__OFFSET 0x00000003u
#define CYFLD_USBPD_CMP_EN__SIZE 0x00000001u
#define CYFLD_USBPD_CMP_DN_CC1V2__OFFSET 0x00000004u
#define CYFLD_USBPD_CMP_DN_CC1V2__SIZE 0x00000001u
#define CYFLD_USBPD_CMP_DN_VSEL__OFFSET 0x00000005u
#define CYFLD_USBPD_CMP_DN_VSEL__SIZE 0x00000003u
#define CYVAL_USBPD_CMP_DN_VSEL_SEL_0_2_VOL 0x00000000u
#define CYVAL_USBPD_CMP_DN_VSEL_SEL_0_4_VOL 0x00000001u
#define CYVAL_USBPD_CMP_DN_VSEL_SEL_0_55_VOL 0x00000002u
#define CYVAL_USBPD_CMP_DN_VSEL_SEL_0_655_VOL 0x00000003u
#define CYVAL_USBPD_CMP_DN_VSEL_SEL_0_8_VOL 0x00000004u
#define CYVAL_USBPD_CMP_DN_VSEL_SEL_1_235_VOL 0x00000005u
#define CYVAL_USBPD_CMP_DN_VSEL_SEL_1_575_VOL 0x00000006u
#define CYVAL_USBPD_CMP_DN_VSEL_SEL_2_6_VOL 0x00000007u
#define CYFLD_USBPD_CMP_UP_CC1V2__OFFSET 0x00000008u
#define CYFLD_USBPD_CMP_UP_CC1V2__SIZE 0x00000001u
#define CYFLD_USBPD_CMP_UP_VSEL__OFFSET 0x00000009u
#define CYFLD_USBPD_CMP_UP_VSEL__SIZE 0x00000003u
#define CYVAL_USBPD_CMP_UP_VSEL_SEL_0_2_VOL 0x00000000u
#define CYVAL_USBPD_CMP_UP_VSEL_SEL_0_4_VOL 0x00000001u
#define CYVAL_USBPD_CMP_UP_VSEL_SEL_0_3_VOL 0x00000002u
#define CYVAL_USBPD_CMP_UP_VSEL_SEL_0_655_VOL 0x00000003u
#define CYVAL_USBPD_CMP_UP_VSEL_SEL_0_8_VOL 0x00000004u
#define CYVAL_USBPD_CMP_UP_VSEL_SEL_1_235_VOL 0x00000005u
#define CYVAL_USBPD_CMP_UP_VSEL_SEL_1_575_VOL 0x00000006u
#define CYVAL_USBPD_CMP_UP_VSEL_SEL_2_6_VOL 0x00000007u
#define CYFLD_USBPD_CMP_UP_OFFSET__OFFSET 0x0000000cu
#define CYFLD_USBPD_CMP_UP_OFFSET__SIZE 0x00000003u
#define CYVAL_USBPD_CMP_UP_OFFSET_SEL_MINUS_50_MV 0x00000000u
#define CYVAL_USBPD_CMP_UP_OFFSET_SEL_MINUS_100_MV 0x00000001u
#define CYVAL_USBPD_CMP_UP_OFFSET_SEL_MINUS_150_MV 0x00000002u
#define CYVAL_USBPD_CMP_UP_OFFSET_SEL_MINUS_200_MV 0x00000003u
#define CYVAL_USBPD_CMP_UP_OFFSET_SEL_PLUS_50_MV 0x00000004u
#define CYVAL_USBPD_CMP_UP_OFFSET_SEL_PLUS_100_MV 0x00000005u
#define CYVAL_USBPD_CMP_UP_OFFSET_SEL_PLUS_150_MV 0x00000006u
#define CYVAL_USBPD_CMP_UP_OFFSET_SEL_PLUS_200_MV 0x00000007u
#define CYFLD_USBPD_CMP_UP_OFFSET_EN__OFFSET 0x0000000fu
#define CYFLD_USBPD_CMP_UP_OFFSET_EN__SIZE 0x00000001u
#define CYFLD_USBPD_CMP_LA_CC1V2__OFFSET 0x00000010u
#define CYFLD_USBPD_CMP_LA_CC1V2__SIZE 0x00000001u
#define CYFLD_USBPD_CMP_LA_VSEL__OFFSET 0x00000011u
#define CYFLD_USBPD_CMP_LA_VSEL__SIZE 0x00000003u
#define CYVAL_USBPD_CMP_LA_VSEL_SEL_0_2_VOL 0x00000000u
#define CYVAL_USBPD_CMP_LA_VSEL_SEL_0_4_VOL 0x00000001u
#define CYVAL_USBPD_CMP_LA_VSEL_SEL_0_55_VOL 0x00000002u
#define CYVAL_USBPD_CMP_LA_VSEL_SEL_0_655_VOL 0x00000003u
#define CYVAL_USBPD_CMP_LA_VSEL_SEL_0_8_VOL 0x00000004u
#define CYVAL_USBPD_CMP_LA_VSEL_SEL_1_235_VOL 0x00000005u
#define CYVAL_USBPD_CMP_LA_VSEL_SEL_1_575_VOL 0x00000006u
#define CYVAL_USBPD_CMP_LA_VSEL_SEL_2_6_VOL 0x00000007u
#define CYFLD_USBPD_RD_CC1_DB_DIS__OFFSET 0x00000014u
#define CYFLD_USBPD_RD_CC1_DB_DIS__SIZE 0x00000001u
#define CYFLD_USBPD_RD_CC2_DB_DIS__OFFSET 0x00000015u
#define CYFLD_USBPD_RD_CC2_DB_DIS__SIZE 0x00000001u
#define CYFLD_USBPD_RD_CC1_EN__OFFSET 0x00000016u
#define CYFLD_USBPD_RD_CC1_EN__SIZE 0x00000001u
#define CYFLD_USBPD_RD_CC2_EN__OFFSET 0x00000017u
#define CYFLD_USBPD_RD_CC2_EN__SIZE 0x00000001u
#define CYFLD_USBPD_RP_CC1_EN__OFFSET 0x00000018u
#define CYFLD_USBPD_RP_CC1_EN__SIZE 0x00000001u
#define CYFLD_USBPD_RP_CC2_EN__OFFSET 0x00000019u
#define CYFLD_USBPD_RP_CC2_EN__SIZE 0x00000001u
#define CYFLD_USBPD_RP_MODE__OFFSET 0x0000001au
#define CYFLD_USBPD_RP_MODE__SIZE 0x00000002u
#define CYVAL_USBPD_RP_MODE_PU0_80_UA 0x00000000u
#define CYVAL_USBPD_RP_MODE_PU1_1p5_A 0x00000001u
#define CYVAL_USBPD_RP_MODE_PU2_80_UA 0x00000002u
#define CYVAL_USBPD_RP_MODE_PU3_3A 0x00000003u
#define CYFLD_USBPD_EN_HYST__OFFSET 0x0000001cu
#define CYFLD_USBPD_EN_HYST__SIZE 0x00000001u
#define CYFLD_USBPD_HYST_MODE__OFFSET 0x0000001du
#define CYFLD_USBPD_HYST_MODE__SIZE 0x00000001u
#define CYFLD_USBPD_DFP_EN__OFFSET 0x0000001eu
#define CYFLD_USBPD_DFP_EN__SIZE 0x00000001u
#define CYFLD_USBPD_PWR_DISABLE__OFFSET 0x0000001fu
#define CYFLD_USBPD_PWR_DISABLE__SIZE 0x00000001u
#define CYREG_USBPD_CC_CTRL_1 0x400a01b4u
#define CYFLD_USBPD_CC_ADFT_EN__OFFSET 0x00000000u
#define CYFLD_USBPD_CC_ADFT_EN__SIZE 0x00000001u
#define CYFLD_USBPD_CC_ADFT_CTRL__OFFSET 0x00000001u
#define CYFLD_USBPD_CC_ADFT_CTRL__SIZE 0x00000004u
#define CYFLD_USBPD_RX_OFFSET_EN__OFFSET 0x00000006u
#define CYFLD_USBPD_RX_OFFSET_EN__SIZE 0x00000001u
#define CYFLD_USBPD_RX_OFFSET__OFFSET 0x00000007u
#define CYFLD_USBPD_RX_OFFSET__SIZE 0x00000003u
#define CYVAL_USBPD_RX_OFFSET_SEL_MINUS_50_MV 0x00000000u
#define CYVAL_USBPD_RX_OFFSET_SEL_MINUS_100_MV 0x00000001u
#define CYVAL_USBPD_RX_OFFSET_SEL_MINUS_150_MV 0x00000002u
#define CYVAL_USBPD_RX_OFFSET_SEL_MINUS_200_MV 0x00000003u
#define CYVAL_USBPD_RX_OFFSET_SEL_PLUS_50_MV 0x00000004u
#define CYVAL_USBPD_RX_OFFSET_SEL_PLUS_100_MV 0x00000005u
#define CYVAL_USBPD_RX_OFFSET_SEL_PLUS_150_MV 0x00000006u
#define CYVAL_USBPD_RX_OFFSET_SEL_PLUS_200_MV 0x00000007u
#define CYFLD_USBPD_DS_ATTACH_DET_EN__OFFSET 0x0000000au
#define CYFLD_USBPD_DS_ATTACH_DET_EN__SIZE 0x00000001u
#define CYFLD_USBPD_VTX_SEL__OFFSET 0x0000000bu
#define CYFLD_USBPD_VTX_SEL__SIZE 0x00000003u
#define CYVAL_USBPD_VTX_SEL_SEL_0_93_V 0x00000000u
#define CYVAL_USBPD_VTX_SEL_SEL_1_03_V 0x00000001u
#define CYVAL_USBPD_VTX_SEL_SEL_1_125_V 0x00000002u
#define CYVAL_USBPD_VTX_SEL_SEL_1_225_V 0x00000003u
#define CYVAL_USBPD_VTX_SEL_SEL_1_33_V 0x00000004u
#define CYVAL_USBPD_VTX_SEL_SEL_1_43_V 0x00000005u
#define CYVAL_USBPD_VTX_SEL_SEL_1_53_V 0x00000006u
#define CYVAL_USBPD_VTX_SEL_SEL_1_63_V 0x00000007u
#define CYFLD_USBPD_CC_ISO_N__OFFSET 0x0000000eu
#define CYFLD_USBPD_CC_ISO_N__SIZE 0x00000001u
#define CYREG_USBPD_DPSLP_REF_CTRL 0x400a01b8u
#define CYFLD_USBPD_IGEN_EN__OFFSET 0x00000000u
#define CYFLD_USBPD_IGEN_EN__SIZE 0x00000001u
#define CYFLD_USBPD_DPSLP_ADFT_EN__OFFSET 0x00000001u
#define CYFLD_USBPD_DPSLP_ADFT_EN__SIZE 0x00000001u
#define CYFLD_USBPD_ADFT_CTRL__OFFSET 0x00000002u
#define CYFLD_USBPD_ADFT_CTRL__SIZE 0x00000001u
#define CYFLD_USBPD_PD_DPSLP__OFFSET 0x00000003u
#define CYFLD_USBPD_PD_DPSLP__SIZE 0x00000001u
#define CYFLD_USBPD_PCTAT_CTRL__OFFSET 0x00000004u
#define CYFLD_USBPD_PCTAT_CTRL__SIZE 0x00000002u
#define CYREG_USBPD_VCONN_CTRL 0x400a01bcu
#define CYFLD_USBPD_PUMP_EN__OFFSET 0x00000000u
#define CYFLD_USBPD_PUMP_EN__SIZE 0x00000001u
#define CYFLD_USBPD_EN_COMP1__OFFSET 0x00000001u
#define CYFLD_USBPD_EN_COMP1__SIZE 0x00000001u
#define CYFLD_USBPD_LEAKER_CONFIG1__OFFSET 0x00000003u
#define CYFLD_USBPD_LEAKER_CONFIG1__SIZE 0x00000003u
#define CYVAL_USBPD_LEAKER_CONFIG1_LEAKER_DIS 0x00000000u
#define CYVAL_USBPD_LEAKER_CONFIG1_SEL_200_UA 0x00000001u
#define CYVAL_USBPD_LEAKER_CONFIG1_SEL_0_1_UF 0x00000002u
#define CYVAL_USBPD_LEAKER_CONFIG1_SEL_0_5_UF 0x00000003u
#define CYVAL_USBPD_LEAKER_CONFIG1_SEL_1_UF 0x00000004u
#define CYVAL_USBPD_LEAKER_CONFIG1_SEL_2_UF 0x00000005u
#define CYVAL_USBPD_LEAKER_CONFIG1_SEL_5_UF 0x00000006u
#define CYVAL_USBPD_LEAKER_CONFIG1_SEL_10_UF 0x00000007u
#define CYREG_USBPD_PUMP_CTRL 0x400a01c0u
#define CYFLD_USBPD_ADFT__OFFSET 0x00000000u
#define CYFLD_USBPD_ADFT__SIZE 0x00000002u
#define CYFLD_USBPD_BYPASS_LV__OFFSET 0x00000002u
#define CYFLD_USBPD_BYPASS_LV__SIZE 0x00000001u
#define CYFLD_USBPD_CLK_SEL__OFFSET 0x00000003u
#define CYFLD_USBPD_CLK_SEL__SIZE 0x00000001u
#define CYFLD_USBPD_PD_PUMP__OFFSET 0x00000004u
#define CYFLD_USBPD_PD_PUMP__SIZE 0x00000001u
#define CYREG_USBPD_PFET300_CTRL 0x400a01c4u
#define CYFLD_USBPD_EN_COMP__OFFSET 0x00000000u
#define CYFLD_USBPD_EN_COMP__SIZE 0x00000001u
#define CYFLD_USBPD_EN_SWITCH_CC1__OFFSET 0x00000001u
#define CYFLD_USBPD_EN_SWITCH_CC1__SIZE 0x00000001u
#define CYFLD_USBPD_EN_SWITCH_CC2__OFFSET 0x00000002u
#define CYFLD_USBPD_EN_SWITCH_CC2__SIZE 0x00000001u
#define CYREG_USBPD_UVOV_CTRL 0x400a01c8u
#define CYFLD_USBPD_UV_IN__OFFSET 0x00000000u
#define CYFLD_USBPD_UV_IN__SIZE 0x00000006u
#define CYFLD_USBPD_OV_IN__OFFSET 0x00000006u
#define CYFLD_USBPD_OV_IN__SIZE 0x00000006u
#define CYFLD_USBPD_UVOV_ISO_N__OFFSET 0x0000000cu
#define CYFLD_USBPD_UVOV_ISO_N__SIZE 0x00000001u
#define CYFLD_USBPD_UVOV_ADFT_EN__OFFSET 0x0000000du
#define CYFLD_USBPD_UVOV_ADFT_EN__SIZE 0x00000001u
#define CYFLD_USBPD_UVOV_ADFT_CTRL__OFFSET 0x0000000eu
#define CYFLD_USBPD_UVOV_ADFT_CTRL__SIZE 0x00000002u
#define CYFLD_USBPD_UVOV_SPARE__OFFSET 0x00000010u
#define CYFLD_USBPD_UVOV_SPARE__SIZE 0x00000008u
#define CYFLD_USBPD_PD_UVOV__OFFSET 0x0000001eu
#define CYFLD_USBPD_PD_UVOV__SIZE 0x00000001u
#define CYREG_USBPD_CSA_CTRL 0x400a01ccu
#define CYFLD_USBPD_AV1__OFFSET 0x00000000u
#define CYFLD_USBPD_AV1__SIZE 0x00000003u
#define CYFLD_USBPD_SEL_OUT_D__OFFSET 0x00000006u
#define CYFLD_USBPD_SEL_OUT_D__SIZE 0x00000001u
#define CYFLD_USBPD_CSA_ISO_N__OFFSET 0x00000007u
#define CYFLD_USBPD_CSA_ISO_N__SIZE 0x00000001u
#define CYFLD_USBPD_CSA_ADFT_CTRL__OFFSET 0x00000008u
#define CYFLD_USBPD_CSA_ADFT_CTRL__SIZE 0x00000004u
#define CYFLD_USBPD_CSA_VREF_SEL__OFFSET 0x0000000cu
#define CYFLD_USBPD_CSA_VREF_SEL__SIZE 0x00000006u
#define CYFLD_USBPD_CSA_SPARE__OFFSET 0x00000012u
#define CYFLD_USBPD_CSA_SPARE__SIZE 0x00000004u
#define CYFLD_USBPD_VREFIN_SEL__OFFSET 0x0000001cu
#define CYFLD_USBPD_VREFIN_SEL__SIZE 0x00000001u
#define CYFLD_USBPD_HYST_EN__OFFSET 0x0000001du
#define CYFLD_USBPD_HYST_EN__SIZE 0x00000001u
#define CYFLD_USBPD_BW__OFFSET 0x0000001eu
#define CYFLD_USBPD_BW__SIZE 0x00000001u
#define CYFLD_USBPD_PD_CSA__OFFSET 0x0000001fu
#define CYFLD_USBPD_PD_CSA__SIZE 0x00000001u
#define CYREG_USBPD_VREG_CTRL 0x400a01d0u
#define CYFLD_USBPD_VREG20_ADFT_CTRL__OFFSET 0x00000000u
#define CYFLD_USBPD_VREG20_ADFT_CTRL__SIZE 0x00000002u
#define CYFLD_USBPD_VREG_ISO_N__OFFSET 0x00000002u
#define CYFLD_USBPD_VREG_ISO_N__SIZE 0x00000001u
#define CYFLD_USBPD_VBG_EN__OFFSET 0x00000008u
#define CYFLD_USBPD_VBG_EN__SIZE 0x00000001u
#define CYFLD_USBPD_VREG_SPARE__OFFSET 0x00000009u
#define CYFLD_USBPD_VREG_SPARE__SIZE 0x00000007u
#define CYREG_USBPD_SBU_CTRL 0x400a01d4u
#define CYFLD_USBPD_SBU_ADFT_EN__OFFSET 0x00000000u
#define CYFLD_USBPD_SBU_ADFT_EN__SIZE 0x00000001u
#define CYFLD_USBPD_SBU_ADFT_SEL__OFFSET 0x00000001u
#define CYFLD_USBPD_SBU_ADFT_SEL__SIZE 0x00000004u
#define CYFLD_USBPD_IN1_OUT1_EN__OFFSET 0x00000005u
#define CYFLD_USBPD_IN1_OUT1_EN__SIZE 0x00000001u
#define CYFLD_USBPD_IN2_OUT1_EN__OFFSET 0x00000006u
#define CYFLD_USBPD_IN2_OUT1_EN__SIZE 0x00000001u
#define CYFLD_USBPD_IN1_OUT2_EN__OFFSET 0x00000007u
#define CYFLD_USBPD_IN1_OUT2_EN__SIZE 0x00000001u
#define CYFLD_USBPD_IN2_OUT2_EN__OFFSET 0x00000008u
#define CYFLD_USBPD_IN2_OUT2_EN__SIZE 0x00000001u
#define CYFLD_USBPD_OUT1_1MEG_EN_PU__OFFSET 0x00000009u
#define CYFLD_USBPD_OUT1_1MEG_EN_PU__SIZE 0x00000001u
#define CYFLD_USBPD_OUT1_100K_EN_PD__OFFSET 0x0000000au
#define CYFLD_USBPD_OUT1_100K_EN_PD__SIZE 0x00000001u
#define CYFLD_USBPD_OUT1_470K_EN_PD__OFFSET 0x0000000bu
#define CYFLD_USBPD_OUT1_470K_EN_PD__SIZE 0x00000001u
#define CYFLD_USBPD_OUT2_100K_EN_PU__OFFSET 0x0000000cu
#define CYFLD_USBPD_OUT2_100K_EN_PU__SIZE 0x00000001u
#define CYFLD_USBPD_OUT2_4P7MEG_EN_PD__OFFSET 0x0000000du
#define CYFLD_USBPD_OUT2_4P7MEG_EN_PD__SIZE 0x00000001u
#define CYFLD_USBPD_OUT2_1MEG_EN_PD__OFFSET 0x0000000eu
#define CYFLD_USBPD_OUT2_1MEG_EN_PD__SIZE 0x00000001u
#define CYFLD_USBPD_SBU_SPARE__OFFSET 0x00000010u
#define CYFLD_USBPD_SBU_SPARE__SIZE 0x00000008u
#define CYREG_USBPD_VSYS_CTRL 0x400a01d8u
#define CYFLD_USBPD_VSYS_ISO_N__OFFSET 0x00000000u
#define CYFLD_USBPD_VSYS_ISO_N__SIZE 0x00000001u
#define CYFLD_USBPD_ADFT_EN__OFFSET 0x00000001u
#define CYFLD_USBPD_ADFT_EN__SIZE 0x00000001u
#define CYFLD_USBPD_ADFT_SEL__OFFSET 0x00000002u
#define CYFLD_USBPD_ADFT_SEL__SIZE 0x00000002u
#define CYFLD_USBPD_VSYS_SPARE__OFFSET 0x00000008u
#define CYFLD_USBPD_VSYS_SPARE__SIZE 0x00000008u
#define CYREG_USBPD_VREG_VSYS_CTRL 0x400a01dcu
#define CYFLD_USBPD_VREG20_EN__OFFSET 0x00000000u
#define CYFLD_USBPD_VREG20_EN__SIZE 0x00000001u
#define CYFLD_USBPD_VREG20_ONOFF_CNTR__OFFSET 0x00000008u
#define CYFLD_USBPD_VREG20_ONOFF_CNTR__SIZE 0x00000008u
#define CYFLD_USBPD_ENABLE_VDDD_SWITCH__OFFSET 0x00000010u
#define CYFLD_USBPD_ENABLE_VDDD_SWITCH__SIZE 0x00000001u
#define CYFLD_USBPD_VDDD_SW_ONOFF_CNTR__OFFSET 0x00000011u
#define CYFLD_USBPD_VDDD_SW_ONOFF_CNTR__SIZE 0x00000008u
#define CYREG_USBPD_NGDO_CTRL_0 0x400a01e0u
#define CYFLD_USBPD_NGDO_VBUS_C_CLKIN_SEL_LV__OFFSET 0x00000000u
#define CYFLD_USBPD_NGDO_VBUS_C_CLKIN_SEL_LV__SIZE 0x00000001u
#define CYFLD_USBPD_NGDO_VBUS_C_CLKSEL_LV__OFFSET 0x00000001u
#define CYFLD_USBPD_NGDO_VBUS_C_CLKSEL_LV__SIZE 0x00000002u
#define CYFLD_USBPD_NGDO_VBUS_C_NGDO_EN_LV__OFFSET 0x00000003u
#define CYFLD_USBPD_NGDO_VBUS_C_NGDO_EN_LV__SIZE 0x00000002u
#define CYFLD_USBPD_NGDO_VBUS_C_PULLDN_EN_LV__OFFSET 0x00000005u
#define CYFLD_USBPD_NGDO_VBUS_C_PULLDN_EN_LV__SIZE 0x00000002u
#define CYFLD_USBPD_NGDO_VBUS_C_DFT_EN_LV__OFFSET 0x00000007u
#define CYFLD_USBPD_NGDO_VBUS_C_DFT_EN_LV__SIZE 0x00000001u
#define CYFLD_USBPD_NGDO_VBUS_C_DFT_CLKOUT_SEL_LV__OFFSET 0x00000008u
#define CYFLD_USBPD_NGDO_VBUS_C_DFT_CLKOUT_SEL_LV__SIZE 0x00000001u
#define CYFLD_USBPD_NGDO_VBUS_P_CLKIN_SEL_LV__OFFSET 0x00000009u
#define CYFLD_USBPD_NGDO_VBUS_P_CLKIN_SEL_LV__SIZE 0x00000001u
#define CYFLD_USBPD_NGDO_VBUS_P_CLKSEL_LV__OFFSET 0x0000000au
#define CYFLD_USBPD_NGDO_VBUS_P_CLKSEL_LV__SIZE 0x00000002u
#define CYFLD_USBPD_NGDO_VBUS_P_NGDO_EN_LV__OFFSET 0x0000000cu
#define CYFLD_USBPD_NGDO_VBUS_P_NGDO_EN_LV__SIZE 0x00000002u
#define CYFLD_USBPD_NGDO_VBUS_P_PULLDN_EN_LV__OFFSET 0x0000000eu
#define CYFLD_USBPD_NGDO_VBUS_P_PULLDN_EN_LV__SIZE 0x00000002u
#define CYFLD_USBPD_NGDO_VBUS_P_DFT_EN_LV__OFFSET 0x00000010u
#define CYFLD_USBPD_NGDO_VBUS_P_DFT_EN_LV__SIZE 0x00000001u
#define CYFLD_USBPD_NGDO_VBUS_P_DFT_CLKOUT_SEL_LV__OFFSET 0x00000011u
#define CYFLD_USBPD_NGDO_VBUS_P_DFT_CLKOUT_SEL_LV__SIZE 0x00000001u
#define CYFLD_USBPD_NGDO_SPARE__OFFSET 0x00000018u
#define CYFLD_USBPD_NGDO_SPARE__SIZE 0x00000008u
#define CYREG_USBPD_NGDO_CTRL_C 0x400a01e4u
#define CYFLD_USBPD_AUTO_MODE__OFFSET 0x00000000u
#define CYFLD_USBPD_AUTO_MODE__SIZE 0x00000001u
#define CYFLD_USBPD_RST_EDGE_DET__OFFSET 0x00000001u
#define CYFLD_USBPD_RST_EDGE_DET__SIZE 0x00000001u
#define CYFLD_USBPD_TURN_OFF_SEL__OFFSET 0x00000002u
#define CYFLD_USBPD_TURN_OFF_SEL__SIZE 0x00000001u
#define CYFLD_USBPD_BYPASS_2DFF__OFFSET 0x00000003u
#define CYFLD_USBPD_BYPASS_2DFF__SIZE 0x00000001u
#define CYFLD_USBPD_TURN_OFF_SPACING__OFFSET 0x00000004u
#define CYFLD_USBPD_TURN_OFF_SPACING__SIZE 0x00000004u
#define CYFLD_USBPD_SEL_OV__OFFSET 0x00000008u
#define CYFLD_USBPD_SEL_OV__SIZE 0x00000001u
#define CYFLD_USBPD_SEL_UV__OFFSET 0x00000009u
#define CYFLD_USBPD_SEL_UV__SIZE 0x00000001u
#define CYFLD_USBPD_SEL_OC__OFFSET 0x0000000au
#define CYFLD_USBPD_SEL_OC__SIZE 0x00000001u
#define CYFLD_USBPD_SEL_SWAP_VBUS_LESS_5__OFFSET 0x0000000bu
#define CYFLD_USBPD_SEL_SWAP_VBUS_LESS_5__SIZE 0x00000001u
#define CYFLD_USBPD_EN_LV_OFF_VALUE__OFFSET 0x0000000cu
#define CYFLD_USBPD_EN_LV_OFF_VALUE__SIZE 0x00000002u
#define CYFLD_USBPD_PULLDN_EN_LV_OFF_VALUE__OFFSET 0x0000000eu
#define CYFLD_USBPD_PULLDN_EN_LV_OFF_VALUE__SIZE 0x00000002u
#define CYFLD_USBPD_EN_LV_ON_VALUE__OFFSET 0x00000010u
#define CYFLD_USBPD_EN_LV_ON_VALUE__SIZE 0x00000002u
#define CYFLD_USBPD_PULLDN_EN_LV_ON_VALUE__OFFSET 0x00000012u
#define CYFLD_USBPD_PULLDN_EN_LV_ON_VALUE__SIZE 0x00000002u
#define CYREG_USBPD_NGDO_CTRL_P 0x400a01e8u
#define CYREG_USBPD_VBUS_CTRL 0x400a01ecu
#define CYFLD_USBPD_DISCHG_EN__OFFSET 0x00000000u
#define CYFLD_USBPD_DISCHG_EN__SIZE 0x00000001u
#define CYFLD_USBPD_VBUS_SPARE__OFFSET 0x00000008u
#define CYFLD_USBPD_VBUS_SPARE__SIZE 0x00000008u
#define CYREG_USBPD_CHGDET_CTRL_0 0x400a01f0u
#define CYFLD_USBPD_EN_CHGDET__OFFSET 0x00000000u
#define CYFLD_USBPD_EN_CHGDET__SIZE 0x00000001u
#define CYFLD_USBPD_IDP_SNK_EN__OFFSET 0x00000001u
#define CYFLD_USBPD_IDP_SNK_EN__SIZE 0x00000001u
#define CYFLD_USBPD_IDM_SNK_EN__OFFSET 0x00000002u
#define CYFLD_USBPD_IDM_SNK_EN__SIZE 0x00000001u
#define CYFLD_USBPD_VDP_SRC_EN__OFFSET 0x00000003u
#define CYFLD_USBPD_VDP_SRC_EN__SIZE 0x00000001u
#define CYFLD_USBPD_VDM_SRC_EN__OFFSET 0x00000004u
#define CYFLD_USBPD_VDM_SRC_EN__SIZE 0x00000001u
#define CYFLD_USBPD_IDP_SRC_EN__OFFSET 0x00000005u
#define CYFLD_USBPD_IDP_SRC_EN__SIZE 0x00000001u
#define CYFLD_USBPD_DCP_EN__OFFSET 0x00000006u
#define CYFLD_USBPD_DCP_EN__SIZE 0x00000001u
#define CYFLD_USBPD_RDM_PD_EN__OFFSET 0x00000007u
#define CYFLD_USBPD_RDM_PD_EN__SIZE 0x00000001u
#define CYFLD_USBPD_RDM_PU_EN__OFFSET 0x00000008u
#define CYFLD_USBPD_RDM_PU_EN__SIZE 0x00000001u
#define CYFLD_USBPD_RDP_PD_EN__OFFSET 0x00000009u
#define CYFLD_USBPD_RDP_PD_EN__SIZE 0x00000001u
#define CYFLD_USBPD_RDP_PU_EN__OFFSET 0x0000000au
#define CYFLD_USBPD_RDP_PU_EN__SIZE 0x00000001u
#define CYFLD_USBPD_RDAT_LKG_DP_EN__OFFSET 0x0000000bu
#define CYFLD_USBPD_RDAT_LKG_DP_EN__SIZE 0x00000001u
#define CYFLD_USBPD_RDAT_LKG_DM_EN__OFFSET 0x0000000cu
#define CYFLD_USBPD_RDAT_LKG_DM_EN__SIZE 0x00000001u
#define CYFLD_USBPD_CMP_INN_SEL__OFFSET 0x0000000du
#define CYFLD_USBPD_CMP_INN_SEL__SIZE 0x00000002u
#define CYFLD_USBPD_CMP_INP_SEL__OFFSET 0x0000000fu
#define CYFLD_USBPD_CMP_INP_SEL__SIZE 0x00000002u
#define CYFLD_USBPD_VREF_SEL__OFFSET 0x00000011u
#define CYFLD_USBPD_VREF_SEL__SIZE 0x00000003u
#define CYFLD_USBPD_EN_COMP_CHGDET__OFFSET 0x00000014u
#define CYFLD_USBPD_EN_COMP_CHGDET__SIZE 0x00000001u
#define CYFLD_USBPD_CMP_OFFSET_SEL__OFFSET 0x00000015u
#define CYFLD_USBPD_CMP_OFFSET_SEL__SIZE 0x00000003u
#define CYFLD_USBPD_CMPP_OFFSET_EN__OFFSET 0x00000018u
#define CYFLD_USBPD_CMPP_OFFSET_EN__SIZE 0x00000001u
#define CYFLD_USBPD_CMP_UGM_EN__OFFSET 0x00000019u
#define CYFLD_USBPD_CMP_UGM_EN__SIZE 0x00000001u
#define CYFLD_USBPD_PD__OFFSET 0x0000001fu
#define CYFLD_USBPD_PD__SIZE 0x00000001u
#define CYREG_USBPD_CHGDET_CTRL_1 0x400a01f4u
#define CYFLD_USBPD_CHGDET_ADFT_EN__OFFSET 0x00000000u
#define CYFLD_USBPD_CHGDET_ADFT_EN__SIZE 0x00000001u
#define CYFLD_USBPD_CHGDET_ADFT_CTRL__OFFSET 0x00000001u
#define CYFLD_USBPD_CHGDET_ADFT_CTRL__SIZE 0x00000004u
#define CYFLD_USBPD_CHGDET_ISO_N__OFFSET 0x00000005u
#define CYFLD_USBPD_CHGDET_ISO_N__SIZE 0x00000001u
#define CYFLD_USBPD_CHGDET_APP_DET__OFFSET 0x00000006u
#define CYFLD_USBPD_CHGDET_APP_DET__SIZE 0x00000001u
#define CYFLD_USBPD_CHGDET_APPLE_MODE_DM__OFFSET 0x00000007u
#define CYFLD_USBPD_CHGDET_APPLE_MODE_DM__SIZE 0x00000002u
#define CYFLD_USBPD_CHGDET_APPLE_MODE_DP__OFFSET 0x00000009u
#define CYFLD_USBPD_CHGDET_APPLE_MODE_DP__SIZE 0x00000002u
#define CYFLD_USBPD_CHGDET_SPARE__OFFSET 0x00000010u
#define CYFLD_USBPD_CHGDET_SPARE__SIZE 0x00000008u
#define CYREG_USBPD_INTR3_CFG_0 0x400a01f8u
#define CYFLD_USBPD_CSA_POS_FILT_EN__OFFSET 0x00000000u
#define CYFLD_USBPD_CSA_POS_FILT_EN__SIZE 0x00000001u
#define CYFLD_USBPD_CSA_POS_FILT_SEL__OFFSET 0x00000001u
#define CYFLD_USBPD_CSA_POS_FILT_SEL__SIZE 0x00000003u
#define CYFLD_USBPD_CSA_NEG_FILT_EN__OFFSET 0x00000004u
#define CYFLD_USBPD_CSA_NEG_FILT_EN__SIZE 0x00000001u
#define CYFLD_USBPD_CSA_NEG_FILT_SEL__OFFSET 0x00000005u
#define CYFLD_USBPD_CSA_NEG_FILT_SEL__SIZE 0x00000003u
#define CYFLD_USBPD_OV_POS_FILT_EN__OFFSET 0x00000008u
#define CYFLD_USBPD_OV_POS_FILT_EN__SIZE 0x00000001u
#define CYFLD_USBPD_OV_POS_FILT_SEL__OFFSET 0x00000009u
#define CYFLD_USBPD_OV_POS_FILT_SEL__SIZE 0x00000003u
#define CYFLD_USBPD_OV_NEG_FILT_EN__OFFSET 0x0000000cu
#define CYFLD_USBPD_OV_NEG_FILT_EN__SIZE 0x00000001u
#define CYFLD_USBPD_OV_NEG_FILT_SEL__OFFSET 0x0000000du
#define CYFLD_USBPD_OV_NEG_FILT_SEL__SIZE 0x00000003u
#define CYFLD_USBPD_UV_POS_FILT_EN__OFFSET 0x00000010u
#define CYFLD_USBPD_UV_POS_FILT_EN__SIZE 0x00000001u
#define CYFLD_USBPD_UV_POS_FILT_SEL__OFFSET 0x00000011u
#define CYFLD_USBPD_UV_POS_FILT_SEL__SIZE 0x00000003u
#define CYFLD_USBPD_UV_NEG_FILT_EN__OFFSET 0x00000014u
#define CYFLD_USBPD_UV_NEG_FILT_EN__SIZE 0x00000001u
#define CYFLD_USBPD_UV_NEG_FILT_SEL__OFFSET 0x00000015u
#define CYFLD_USBPD_UV_NEG_FILT_SEL__SIZE 0x00000003u
#define CYFLD_USBPD_CHGDET_CFG__OFFSET 0x00000018u
#define CYFLD_USBPD_CHGDET_CFG__SIZE 0x00000002u
#define CYVAL_USBPD_CHGDET_CFG_POS_EDG_DIS_NEG_EDG_DIS 0x00000000u
#define CYVAL_USBPD_CHGDET_CFG_POS_EDG_DIS_NEG_EDG_EN 0x00000001u
#define CYVAL_USBPD_CHGDET_CFG_POS_EDG_EN_NEG_EDG_DIS 0x00000002u
#define CYVAL_USBPD_CHGDET_CFG_POS_EDG_EN_NEG_EDG_EN 0x00000003u
#define CYFLD_USBPD_CHGDET_FILT_EN__OFFSET 0x0000001au
#define CYFLD_USBPD_CHGDET_FILT_EN__SIZE 0x00000001u
#define CYFLD_USBPD_CHGDET_FILT_SEL__OFFSET 0x0000001bu
#define CYFLD_USBPD_CHGDET_FILT_SEL__SIZE 0x00000003u
#define CYREG_USBPD_INTR3_CFG_1 0x400a01fcu
#define CYFLD_USBPD_VSYS_CFG__OFFSET 0x00000000u
#define CYFLD_USBPD_VSYS_CFG__SIZE 0x00000002u
#define CYVAL_USBPD_VSYS_CFG_POS_EDG_DIS_NEG_EDG_DIS 0x00000000u
#define CYVAL_USBPD_VSYS_CFG_POS_EDG_DIS_NEG_EDG_EN 0x00000001u
#define CYVAL_USBPD_VSYS_CFG_POS_EDG_EN_NEG_EDG_DIS 0x00000002u
#define CYVAL_USBPD_VSYS_CFG_POS_EDG_EN_NEG_EDG_EN 0x00000003u
#define CYFLD_USBPD_VSYS_FILT_EN__OFFSET 0x00000002u
#define CYFLD_USBPD_VSYS_FILT_EN__SIZE 0x00000001u
#define CYFLD_USBPD_VSYS_FILT_SEL__OFFSET 0x00000003u
#define CYFLD_USBPD_VSYS_FILT_SEL__SIZE 0x00000003u
#define CYFLD_USBPD_VBUS_C_CFG__OFFSET 0x00000006u
#define CYFLD_USBPD_VBUS_C_CFG__SIZE 0x00000002u
#define CYVAL_USBPD_VBUS_C_CFG_POS_EDG_DIS_NEG_EDG_DIS 0x00000000u
#define CYVAL_USBPD_VBUS_C_CFG_POS_EDG_DIS_NEG_EDG_EN 0x00000001u
#define CYVAL_USBPD_VBUS_C_CFG_POS_EDG_EN_NEG_EDG_DIS 0x00000002u
#define CYVAL_USBPD_VBUS_C_CFG_POS_EDG_EN_NEG_EDG_EN 0x00000003u
#define CYFLD_USBPD_VBUS_C_FILT_EN__OFFSET 0x00000008u
#define CYFLD_USBPD_VBUS_C_FILT_EN__SIZE 0x00000001u
#define CYFLD_USBPD_VBUS_C_FILT_SEL__OFFSET 0x00000009u
#define CYFLD_USBPD_VBUS_C_FILT_SEL__SIZE 0x00000003u
#define CYFLD_USBPD_VBUS_P_CFG__OFFSET 0x0000000cu
#define CYFLD_USBPD_VBUS_P_CFG__SIZE 0x00000002u
#define CYVAL_USBPD_VBUS_P_CFG_POS_EDG_DIS_NEG_EDG_DIS 0x00000000u
#define CYVAL_USBPD_VBUS_P_CFG_POS_EDG_DIS_NEG_EDG_EN 0x00000001u
#define CYVAL_USBPD_VBUS_P_CFG_POS_EDG_EN_NEG_EDG_DIS 0x00000002u
#define CYVAL_USBPD_VBUS_P_CFG_POS_EDG_EN_NEG_EDG_EN 0x00000003u
#define CYFLD_USBPD_VBUS_P_FILT_EN__OFFSET 0x0000000eu
#define CYFLD_USBPD_VBUS_P_FILT_EN__SIZE 0x00000001u
#define CYFLD_USBPD_VBUS_P_FILT_SEL__OFFSET 0x0000000fu
#define CYFLD_USBPD_VBUS_P_FILT_SEL__SIZE 0x00000003u
#define CYREG_USBPD_NCELL_STATUS 0x400a0200u
#define CYFLD_USBPD_VSYS_STATUS__OFFSET 0x00000000u
#define CYFLD_USBPD_VSYS_STATUS__SIZE 0x00000001u
#define CYFLD_USBPD_CSA_STATUS__OFFSET 0x00000001u
#define CYFLD_USBPD_CSA_STATUS__SIZE 0x00000001u
#define CYFLD_USBPD_UV_STATUS__OFFSET 0x00000002u
#define CYFLD_USBPD_UV_STATUS__SIZE 0x00000001u
#define CYFLD_USBPD_OV_STATUS__OFFSET 0x00000003u
#define CYFLD_USBPD_OV_STATUS__SIZE 0x00000001u
#define CYFLD_USBPD_CHGDET_STATUS__OFFSET 0x00000004u
#define CYFLD_USBPD_CHGDET_STATUS__SIZE 0x00000001u
#define CYFLD_USBPD_VBUS_C_STATUS__OFFSET 0x00000005u
#define CYFLD_USBPD_VBUS_C_STATUS__SIZE 0x00000001u
#define CYFLD_USBPD_VBUS_P_STATUS__OFFSET 0x00000006u
#define CYFLD_USBPD_VBUS_P_STATUS__SIZE 0x00000001u
#define CYREG_USBPD_INTR3 0x400a0204u
#define CYFLD_USBPD_VSYS_CHANGED__OFFSET 0x00000000u
#define CYFLD_USBPD_VSYS_CHANGED__SIZE 0x00000001u
#define CYFLD_USBPD_POS_CSA_CHANGED__OFFSET 0x00000001u
#define CYFLD_USBPD_POS_CSA_CHANGED__SIZE 0x00000001u
#define CYFLD_USBPD_POS_OV_CHANGED__OFFSET 0x00000002u
#define CYFLD_USBPD_POS_OV_CHANGED__SIZE 0x00000001u
#define CYFLD_USBPD_POS_UV_CHANGED__OFFSET 0x00000003u
#define CYFLD_USBPD_POS_UV_CHANGED__SIZE 0x00000001u
#define CYFLD_USBPD_NEG_CSA_CHANGED__OFFSET 0x00000004u
#define CYFLD_USBPD_NEG_CSA_CHANGED__SIZE 0x00000001u
#define CYFLD_USBPD_NEG_OV_CHANGED__OFFSET 0x00000005u
#define CYFLD_USBPD_NEG_OV_CHANGED__SIZE 0x00000001u
#define CYFLD_USBPD_NEG_UV_CHANGED__OFFSET 0x00000006u
#define CYFLD_USBPD_NEG_UV_CHANGED__SIZE 0x00000001u
#define CYFLD_USBPD_CHGDET_CHANGED__OFFSET 0x00000007u
#define CYFLD_USBPD_CHGDET_CHANGED__SIZE 0x00000001u
#define CYFLD_USBPD_VBUS_C_CHANGED__OFFSET 0x00000008u
#define CYFLD_USBPD_VBUS_C_CHANGED__SIZE 0x00000001u
#define CYFLD_USBPD_VBUS_P_CHANGED__OFFSET 0x00000009u
#define CYFLD_USBPD_VBUS_P_CHANGED__SIZE 0x00000001u
#define CYREG_USBPD_INTR3_SET 0x400a0208u
#define CYREG_USBPD_INTR3_MASK 0x400a020cu
#define CYFLD_USBPD_VSYS_CHANGED_MASK__OFFSET 0x00000000u
#define CYFLD_USBPD_VSYS_CHANGED_MASK__SIZE 0x00000001u
#define CYFLD_USBPD_POS_CSA_CHANGED_MASK__OFFSET 0x00000001u
#define CYFLD_USBPD_POS_CSA_CHANGED_MASK__SIZE 0x00000001u
#define CYFLD_USBPD_POS_OV_CHANGED_MASK__OFFSET 0x00000002u
#define CYFLD_USBPD_POS_OV_CHANGED_MASK__SIZE 0x00000001u
#define CYFLD_USBPD_POS_UV_CHANGED_MASK__OFFSET 0x00000003u
#define CYFLD_USBPD_POS_UV_CHANGED_MASK__SIZE 0x00000001u
#define CYFLD_USBPD_NEG_CSA_CHANGED_MASK__OFFSET 0x00000004u
#define CYFLD_USBPD_NEG_CSA_CHANGED_MASK__SIZE 0x00000001u
#define CYFLD_USBPD_NEG_OV_CHANGED_MASK__OFFSET 0x00000005u
#define CYFLD_USBPD_NEG_OV_CHANGED_MASK__SIZE 0x00000001u
#define CYFLD_USBPD_NEG_UV_CHANGED_MASK__OFFSET 0x00000006u
#define CYFLD_USBPD_NEG_UV_CHANGED_MASK__SIZE 0x00000001u
#define CYFLD_USBPD_CHGDET_CHANGED_MASK__OFFSET 0x00000007u
#define CYFLD_USBPD_CHGDET_CHANGED_MASK__SIZE 0x00000001u
#define CYFLD_USBPD_VBUS_C_CHANGED_MASK__OFFSET 0x00000008u
#define CYFLD_USBPD_VBUS_C_CHANGED_MASK__SIZE 0x00000001u
#define CYFLD_USBPD_VBUS_P_CHANGED_MASK__OFFSET 0x00000009u
#define CYFLD_USBPD_VBUS_P_CHANGED_MASK__SIZE 0x00000001u
#define CYREG_USBPD_INTR3_MASKED 0x400a0210u
#define CYFLD_USBPD_VSYS_CHANGED_MASKED__OFFSET 0x00000000u
#define CYFLD_USBPD_VSYS_CHANGED_MASKED__SIZE 0x00000001u
#define CYFLD_USBPD_POS_CSA_CHANGED_MASKED__OFFSET 0x00000001u
#define CYFLD_USBPD_POS_CSA_CHANGED_MASKED__SIZE 0x00000001u
#define CYFLD_USBPD_POS_OV_CHANGED_MASKED__OFFSET 0x00000002u
#define CYFLD_USBPD_POS_OV_CHANGED_MASKED__SIZE 0x00000001u
#define CYFLD_USBPD_POS_UV_CHANGED_MASKED__OFFSET 0x00000003u
#define CYFLD_USBPD_POS_UV_CHANGED_MASKED__SIZE 0x00000001u
#define CYFLD_USBPD_NEG_CSA_CHANGED_MASKED__OFFSET 0x00000004u
#define CYFLD_USBPD_NEG_CSA_CHANGED_MASKED__SIZE 0x00000001u
#define CYFLD_USBPD_NEG_OV_CHANGED_MASKED__OFFSET 0x00000005u
#define CYFLD_USBPD_NEG_OV_CHANGED_MASKED__SIZE 0x00000001u
#define CYFLD_USBPD_NEG_UV_CHANGED_MASKED__OFFSET 0x00000006u
#define CYFLD_USBPD_NEG_UV_CHANGED_MASKED__SIZE 0x00000001u
#define CYFLD_USBPD_CHGDET_CHANGED_MASKED__OFFSET 0x00000007u
#define CYFLD_USBPD_CHGDET_CHANGED_MASKED__SIZE 0x00000001u
#define CYFLD_USBPD_VBUS_C_CHANGED_MASKED__OFFSET 0x00000008u
#define CYFLD_USBPD_VBUS_C_CHANGED_MASKED__SIZE 0x00000001u
#define CYFLD_USBPD_VBUS_P_CHANGED_MASKED__OFFSET 0x00000009u
#define CYFLD_USBPD_VBUS_P_CHANGED_MASKED__SIZE 0x00000001u
#define CYREG_USBPD_NCELL_DDFT_MUX 0x400a0214u
#define CYFLD_USBPD_ncell_ddft0_sel__OFFSET 0x00000000u
#define CYFLD_USBPD_ncell_ddft0_sel__SIZE 0x00000006u
#define CYFLD_USBPD_ncell_ddft1_sel__OFFSET 0x00000006u
#define CYFLD_USBPD_ncell_ddft1_sel__SIZE 0x00000006u
#define CYREG_USBPD_GPIO_DDFT_MUX 0x400a0218u
#define CYFLD_USBPD_gpio_ddft0_sel__OFFSET 0x00000000u
#define CYFLD_USBPD_gpio_ddft0_sel__SIZE 0x00000006u
#define CYFLD_USBPD_gpio_ddft1_sel__OFFSET 0x00000006u
#define CYFLD_USBPD_gpio_ddft1_sel__SIZE 0x00000006u
#define CYREG_USBPD_GPIO_INTR_DDFT_MUX 0x400a021cu
#define CYFLD_USBPD_gpio_intr_ddft0_sel__OFFSET 0x00000000u
#define CYFLD_USBPD_gpio_intr_ddft0_sel__SIZE 0x00000007u
#define CYFLD_USBPD_gpio_intr_ddft1_sel__OFFSET 0x00000007u
#define CYFLD_USBPD_gpio_intr_ddft1_sel__SIZE 0x00000007u
#define CYREG_USBPD_GPIO_NCELL_DDFT_MUX 0x400a0220u
#define CYFLD_USBPD_gpio_ncell_ddft0_sel__OFFSET 0x00000000u
#define CYFLD_USBPD_gpio_ncell_ddft0_sel__SIZE 0x00000006u
#define CYFLD_USBPD_gpio_ncell_ddft1_sel__OFFSET 0x00000006u
#define CYFLD_USBPD_gpio_ncell_ddft1_sel__SIZE 0x00000006u
#define CYREG_USBPD_SWAP_CNTRL_0 0x400a0224u
#define CYFLD_USBPD_CP_REF_SEL__OFFSET 0x00000000u
#define CYFLD_USBPD_CP_REF_SEL__SIZE 0x00000001u
#define CYFLD_USBPD_CMP_FS_CC1V2__OFFSET 0x00000001u
#define CYFLD_USBPD_CMP_FS_CC1V2__SIZE 0x00000001u
#define CYFLD_USBPD_CMP_FS_VSEL__OFFSET 0x00000002u
#define CYFLD_USBPD_CMP_FS_VSEL__SIZE 0x00000003u
#define CYFLD_USBPD_SWAP_1__OFFSET 0x00000005u
#define CYFLD_USBPD_SWAP_1__SIZE 0x00000003u
#define CYFLD_USBPD_SWAP_2__OFFSET 0x00000008u
#define CYFLD_USBPD_SWAP_2__SIZE 0x00000008u
#define CYFLD_USBPD_SWAP_3__OFFSET 0x00000010u
#define CYFLD_USBPD_SWAP_3__SIZE 0x00000008u
#define CYFLD_USBPD_SWAP_4__OFFSET 0x00000018u
#define CYFLD_USBPD_SWAP_4__SIZE 0x00000008u
#define CYREG_USBPD_SWAP_CNTRL_1 0x400a0228u
#define CYFLD_USBPD_SWAP_5__OFFSET 0x00000000u
#define CYFLD_USBPD_SWAP_5__SIZE 0x00000008u
#define CYFLD_USBPD_SWAP_6__OFFSET 0x00000008u
#define CYFLD_USBPD_SWAP_6__SIZE 0x00000008u
#define CYFLD_USBPD_SWAP_7__OFFSET 0x00000010u
#define CYFLD_USBPD_SWAP_7__SIZE 0x00000008u
#define CYFLD_USBPD_SWAP_8__OFFSET 0x00000018u
#define CYFLD_USBPD_SWAP_8__SIZE 0x00000008u
#define CYREG_USBPD_S8USBPD_TRIM_0 0x400aff00u
#define CYFLD_USBPD_ZDRV_TRIM__OFFSET 0x00000000u
#define CYFLD_USBPD_ZDRV_TRIM__SIZE 0x00000002u
#define CYFLD_USBPD_TX_TRIM__OFFSET 0x00000002u
#define CYFLD_USBPD_TX_TRIM__SIZE 0x00000002u
#define CYFLD_USBPD_RD_TRIM__OFFSET 0x00000004u
#define CYFLD_USBPD_RD_TRIM__SIZE 0x00000004u
#define CYREG_USBPD_S8USBPD_TRIM_1 0x400aff04u
#define CYFLD_USBPD_RP_CC1_TRIM__OFFSET 0x00000000u
#define CYFLD_USBPD_RP_CC1_TRIM__SIZE 0x00000006u
#define CYFLD_USBPD_TC_I_TRIM_9P__OFFSET 0x00000006u
#define CYFLD_USBPD_TC_I_TRIM_9P__SIZE 0x00000002u
#define CYREG_USBPD_S8USBPD_TRIM_2 0x400aff08u
#define CYFLD_USBPD_RP_CC2_TRIM__OFFSET 0x00000000u
#define CYFLD_USBPD_RP_CC2_TRIM__SIZE 0x00000006u
#define CYFLD_USBPD_TC_I_TRIM_4P__OFFSET 0x00000006u
#define CYFLD_USBPD_TC_I_TRIM_4P__SIZE 0x00000002u
#define CYREG_USBPD_S8USBPD_TRIM_3 0x400aff0cu
#define CYFLD_USBPD_V0P55_TRIM__OFFSET 0x00000000u
#define CYFLD_USBPD_V0P55_TRIM__SIZE 0x00000003u
#define CYFLD_USBPD_V0P655_TRIM__OFFSET 0x00000003u
#define CYFLD_USBPD_V0P655_TRIM__SIZE 0x00000003u
#define CYREG_USBPD_S8USBPD_TRIM_4 0x400aff10u
#define CYFLD_USBPD_V0P74_TRIM__OFFSET 0x00000000u
#define CYFLD_USBPD_V0P74_TRIM__SIZE 0x00000004u
#define CYFLD_USBPD_V0P8_TRIM__OFFSET 0x00000004u
#define CYFLD_USBPD_V0P8_TRIM__SIZE 0x00000003u
#define CYREG_USBPD_S8USBPD_TRIM_5 0x400aff14u
#define CYFLD_USBPD_V1P125_TRIM__OFFSET 0x00000000u
#define CYFLD_USBPD_V1P125_TRIM__SIZE 0x00000003u
#define CYFLD_USBPD_V1P235_TRIM__OFFSET 0x00000003u
#define CYFLD_USBPD_V1P235_TRIM__SIZE 0x00000003u
#define CYREG_USBPD_S8USBPD_TRIM_6 0x400aff18u
#define CYFLD_USBPD_V1P575_TRIM__OFFSET 0x00000000u
#define CYFLD_USBPD_V1P575_TRIM__SIZE 0x00000003u
#define CYFLD_USBPD_REF_TRIM__OFFSET 0x00000003u
#define CYFLD_USBPD_REF_TRIM__SIZE 0x00000004u
#define CYREG_USBPD_S8USBPD_TRIM_7 0x400aff1cu
#define CYFLD_USBPD_I_TRIM__OFFSET 0x00000000u
#define CYFLD_USBPD_I_TRIM__SIZE 0x00000008u
#define CYREG_USBPD_S8USBPD_TRIM_SPARE1 0x400aff20u
#define CYFLD_USBPD_VREG_TRIM__OFFSET 0x00000000u
#define CYFLD_USBPD_VREG_TRIM__SIZE 0x00000003u
#define CYFLD_USBPD_SPARE1_TRIM__OFFSET 0x00000003u
#define CYFLD_USBPD_SPARE1_TRIM__SIZE 0x00000005u
#define CYREG_USBPD_S8USBPD_TRIM_SPARE2 0x400aff24u
#define CYFLD_USBPD_SPARE2_TRIM__OFFSET 0x00000000u
#define CYFLD_USBPD_SPARE2_TRIM__SIZE 0x00000008u
#define CYREG_USBPD_S8USBPD_TRIM_CSA_0 0x400aff28u
#define CYFLD_USBPD_OS_EL__OFFSET 0x00000000u
#define CYFLD_USBPD_OS_EL__SIZE 0x00000004u
#define CYFLD_USBPD_INP_DIV_TR__OFFSET 0x00000004u
#define CYFLD_USBPD_INP_DIV_TR__SIZE 0x00000004u
#define CYREG_USBPD_S8USBPD_TRIM_CSA_1 0x400aff2cu
#define CYFLD_USBPD_AV1_TR__OFFSET 0x00000000u
#define CYFLD_USBPD_AV1_TR__SIZE 0x00000004u
#define CYFLD_USBPD_SPARE__OFFSET 0x00000004u
#define CYFLD_USBPD_SPARE__SIZE 0x00000004u
#define CYREG_USBPD_S8USBPD_TRIM_CSA_2 0x400aff30u
#define CYFLD_USBPD_VREF_TR__OFFSET 0x00000000u
#define CYFLD_USBPD_VREF_TR__SIZE 0x00000004u
#define CYREG_USBPD_S8USBPD_TRIM_CHGDET_0 0x400aff34u
#define CYFLD_USBPD_V600M_TRIM__OFFSET 0x00000000u
#define CYFLD_USBPD_V600M_TRIM__SIZE 0x00000003u
#define CYFLD_USBPD_V0P74_CHGDET_TRIM__OFFSET 0x00000003u
#define CYFLD_USBPD_V0P74_CHGDET_TRIM__SIZE 0x00000004u
#define CYREG_USBPD_S8USBPD_TRIM_CHGDET_1 0x400aff38u
#define CYFLD_USBPD_V325M_TRIM__OFFSET 0x00000000u
#define CYFLD_USBPD_V325M_TRIM__SIZE 0x00000002u
#define CYFLD_USBPD_V2V_TRIM__OFFSET 0x00000002u
#define CYFLD_USBPD_V2V_TRIM__SIZE 0x00000002u
#define CYFLD_USBPD_VAPP_TRIM__OFFSET 0x00000004u
#define CYFLD_USBPD_VAPP_TRIM__SIZE 0x00000003u
#define CYREG_USBPD_S8USBPD_TRIM_CHGDET_2 0x400aff3cu
#define CYFLD_USBPD_V850M_TRIM__OFFSET 0x00000000u
#define CYFLD_USBPD_V850M_TRIM__SIZE 0x00000002u
#define CYFLD_USBPD_V2P2V_TRIM__OFFSET 0x00000002u
#define CYFLD_USBPD_V2P2V_TRIM__SIZE 0x00000002u
#define CYFLD_USBPD_V2P9V_TRIM__OFFSET 0x00000004u
#define CYFLD_USBPD_V2P9V_TRIM__SIZE 0x00000002u
#define CYFLD_USBPD_V2P5V_TRIM__OFFSET 0x00000006u
#define CYFLD_USBPD_V2P5V_TRIM__SIZE 0x00000002u
#define CYREG_USBPD_S8USBPD_TRIM_SBU_0 0x400aff40u
#define CYFLD_USBPD_SBU_1MEG_TRIM__OFFSET 0x00000000u
#define CYFLD_USBPD_SBU_1MEG_TRIM__SIZE 0x00000003u
#define CYFLD_USBPD_SBU_100K_TRIM__OFFSET 0x00000003u
#define CYFLD_USBPD_SBU_100K_TRIM__SIZE 0x00000003u
#define CYREG_USBPD_S8USBPD_TRIM_SBU_1 0x400aff44u
#define CYFLD_USBPD_SBU_470K_PD_TRIM__OFFSET 0x00000000u
#define CYFLD_USBPD_SBU_470K_PD_TRIM__SIZE 0x00000003u
#define CYREG_USBPD_S8USBPD_TRIM_SBU_2 0x400aff48u
#define CYFLD_USBPD_SBU_4P7MEG_PD_TRIM__OFFSET 0x00000000u
#define CYFLD_USBPD_SBU_4P7MEG_PD_TRIM__SIZE 0x00000003u
#define CYREG_USBPD_S8USBPD_TRIM_SPARE3 0x400aff4cu
#define CYFLD_USBPD_SPARE3_TRIM__OFFSET 0x00000000u
#define CYFLD_USBPD_SPARE3_TRIM__SIZE 0x00000008u
#define CYREG_USBPD_S8USBPD_TRIM_SPARE4 0x400aff50u
#define CYFLD_USBPD_SPARE4_TRIM__OFFSET 0x00000000u
#define CYFLD_USBPD_SPARE4_TRIM__SIZE 0x00000008u
#define CYDEV_CRYPTO_BASE 0x400b0000u
#define CYDEV_CRYPTO_SIZE 0x00010000u
#define CYREG_CRYPTO_CTL 0x400b0000u
#define CYFLD_CRYPTO_OPCODE__OFFSET 0x00000000u
#define CYFLD_CRYPTO_OPCODE__SIZE 0x00000005u
#define CYVAL_CRYPTO_OPCODE_AES_FORWARD 0x00000000u
#define CYVAL_CRYPTO_OPCODE_AES_INVERSE 0x00000001u
#define CYVAL_CRYPTO_OPCODE_SHA 0x00000010u
#define CYVAL_CRYPTO_OPCODE_CRC 0x00000018u
#define CYFLD_CRYPTO_ENABLED__OFFSET 0x0000001fu
#define CYFLD_CRYPTO_ENABLED__SIZE 0x00000001u
#define CYREG_CRYPTO_STATUS 0x400b0004u
#define CYFLD_CRYPTO_BUSY__OFFSET 0x00000000u
#define CYFLD_CRYPTO_BUSY__SIZE 0x00000001u
#define CYREG_CRYPTO_CMD 0x400b0008u
#define CYFLD_CRYPTO_START__OFFSET 0x00000000u
#define CYFLD_CRYPTO_START__SIZE 0x00000001u
#define CYREG_CRYPTO_SRC_CTL0 0x400b0010u
#define CYFLD_CRYPTO_OFFSET__OFFSET 0x00000002u
#define CYFLD_CRYPTO_OFFSET__SIZE 0x00000010u
#define CYREG_CRYPTO_SRC_CTL1 0x400b0014u
#define CYREG_CRYPTO_DST_CTL0 0x400b0020u
#define CYREG_CRYPTO_DST_CTL1 0x400b0024u
#define CYREG_CRYPTO_AES_CTL 0x400b0100u
#define CYFLD_CRYPTO_KEY_SIZE__OFFSET 0x00000000u
#define CYFLD_CRYPTO_KEY_SIZE__SIZE 0x00000002u
#define CYREG_CRYPTO_PR_CTL 0x400b0200u
#define CYFLD_CRYPTO_MAX__OFFSET 0x00000000u
#define CYFLD_CRYPTO_MAX__SIZE 0x00000020u
#define CYREG_CRYPTO_PR_CMD 0x400b0208u
#define CYREG_CRYPTO_PR_LFSR_CTL0 0x400b0210u
#define CYFLD_CRYPTO_LFSR32__OFFSET 0x00000000u
#define CYFLD_CRYPTO_LFSR32__SIZE 0x00000020u
#define CYREG_CRYPTO_PR_LFSR_CTL1 0x400b0214u
#define CYFLD_CRYPTO_LFSR31__OFFSET 0x00000000u
#define CYFLD_CRYPTO_LFSR31__SIZE 0x0000001fu
#define CYREG_CRYPTO_PR_LFSR_CTL2 0x400b0218u
#define CYFLD_CRYPTO_LFSR29__OFFSET 0x00000000u
#define CYFLD_CRYPTO_LFSR29__SIZE 0x0000001du
#define CYREG_CRYPTO_PR_RESULT 0x400b0220u
#define CYFLD_CRYPTO_DATA32__OFFSET 0x00000000u
#define CYFLD_CRYPTO_DATA32__SIZE 0x00000020u
#define CYREG_CRYPTO_TR_CTL0 0x400b0280u
#define CYFLD_CRYPTO_SAMPLE_CLOCK_DIV__OFFSET 0x00000000u
#define CYFLD_CRYPTO_SAMPLE_CLOCK_DIV__SIZE 0x00000008u
#define CYFLD_CRYPTO_RED_CLOCK_DIV__OFFSET 0x00000008u
#define CYFLD_CRYPTO_RED_CLOCK_DIV__SIZE 0x00000008u
#define CYFLD_CRYPTO_INIT_DELAY__OFFSET 0x00000010u
#define CYFLD_CRYPTO_INIT_DELAY__SIZE 0x00000008u
#define CYFLD_CRYPTO_VON_NEUMANN_CORR__OFFSET 0x00000018u
#define CYFLD_CRYPTO_VON_NEUMANN_CORR__SIZE 0x00000001u
#define CYFLD_CRYPTO_STOP_ON_AP_DETECT__OFFSET 0x0000001cu
#define CYFLD_CRYPTO_STOP_ON_AP_DETECT__SIZE 0x00000001u
#define CYFLD_CRYPTO_STOP_ON_RC_DETECT__OFFSET 0x0000001du
#define CYFLD_CRYPTO_STOP_ON_RC_DETECT__SIZE 0x00000001u
#define CYREG_CRYPTO_TR_CTL1 0x400b0284u
#define CYFLD_CRYPTO_DATA_BIT_SIZE__OFFSET 0x00000000u
#define CYFLD_CRYPTO_DATA_BIT_SIZE__SIZE 0x00000006u
#define CYREG_CRYPTO_TR_RESULT0 0x400b0288u
#define CYREG_CRYPTO_TR_RESULT1 0x400b028cu
#define CYREG_CRYPTO_TR_CMD 0x400b0290u
#define CYFLD_CRYPTO_START_RO11__OFFSET 0x00000000u
#define CYFLD_CRYPTO_START_RO11__SIZE 0x00000001u
#define CYFLD_CRYPTO_START_RO15__OFFSET 0x00000001u
#define CYFLD_CRYPTO_START_RO15__SIZE 0x00000001u
#define CYFLD_CRYPTO_START_GARO15__OFFSET 0x00000002u
#define CYFLD_CRYPTO_START_GARO15__SIZE 0x00000001u
#define CYFLD_CRYPTO_START_GARO31__OFFSET 0x00000003u
#define CYFLD_CRYPTO_START_GARO31__SIZE 0x00000001u
#define CYFLD_CRYPTO_START_FIRO15__OFFSET 0x00000004u
#define CYFLD_CRYPTO_START_FIRO15__SIZE 0x00000001u
#define CYFLD_CRYPTO_START_FIRO31__OFFSET 0x00000005u
#define CYFLD_CRYPTO_START_FIRO31__SIZE 0x00000001u
#define CYREG_CRYPTO_TR_GARO_CTL 0x400b02a0u
#define CYFLD_CRYPTO_POLYNOMIAL31__OFFSET 0x00000000u
#define CYFLD_CRYPTO_POLYNOMIAL31__SIZE 0x0000001fu
#define CYREG_CRYPTO_TR_FIRO_CTL 0x400b02a4u
#define CYREG_CRYPTO_TR_MON_CTL 0x400b02c0u
#define CYFLD_CRYPTO_BITSTREAM_SEL__OFFSET 0x00000000u
#define CYFLD_CRYPTO_BITSTREAM_SEL__SIZE 0x00000002u
#define CYREG_CRYPTO_TR_MON_CMD 0x400b02c8u
#define CYFLD_CRYPTO_START_AP__OFFSET 0x00000000u
#define CYFLD_CRYPTO_START_AP__SIZE 0x00000001u
#define CYFLD_CRYPTO_START_RC__OFFSET 0x00000001u
#define CYFLD_CRYPTO_START_RC__SIZE 0x00000001u
#define CYREG_CRYPTO_TR_MON_RC_CTL 0x400b02d0u
#define CYFLD_CRYPTO_CUTOFF_COUNT8__OFFSET 0x00000000u
#define CYFLD_CRYPTO_CUTOFF_COUNT8__SIZE 0x00000008u
#define CYREG_CRYPTO_TR_MON_RC_STATUS0 0x400b02d8u
#define CYFLD_CRYPTO_BIT__OFFSET 0x00000000u
#define CYFLD_CRYPTO_BIT__SIZE 0x00000001u
#define CYREG_CRYPTO_TR_MON_RC_STATUS1 0x400b02dcu
#define CYFLD_CRYPTO_REP_COUNT__OFFSET 0x00000000u
#define CYFLD_CRYPTO_REP_COUNT__SIZE 0x00000008u
#define CYREG_CRYPTO_TR_MON_AP_CTL 0x400b02e0u
#define CYFLD_CRYPTO_CUTOFF_COUNT16__OFFSET 0x00000000u
#define CYFLD_CRYPTO_CUTOFF_COUNT16__SIZE 0x00000010u
#define CYFLD_CRYPTO_WINDOW_SIZE__OFFSET 0x00000010u
#define CYFLD_CRYPTO_WINDOW_SIZE__SIZE 0x00000010u
#define CYREG_CRYPTO_TR_MON_AP_STATUS0 0x400b02e8u
#define CYREG_CRYPTO_TR_MON_AP_STATUS1 0x400b02ecu
#define CYFLD_CRYPTO_OCC_COUNT__OFFSET 0x00000000u
#define CYFLD_CRYPTO_OCC_COUNT__SIZE 0x00000010u
#define CYFLD_CRYPTO_WINDOW_INDEX__OFFSET 0x00000010u
#define CYFLD_CRYPTO_WINDOW_INDEX__SIZE 0x00000010u
#define CYREG_CRYPTO_SHA_CTL 0x400b0300u
#define CYFLD_CRYPTO_MODE__OFFSET 0x00000000u
#define CYFLD_CRYPTO_MODE__SIZE 0x00000003u
#define CYREG_CRYPTO_CRC_DATA_CTL0 0x400b0400u
#define CYFLD_CRYPTO_DATA_REVERSE__OFFSET 0x00000000u
#define CYFLD_CRYPTO_DATA_REVERSE__SIZE 0x00000001u
#define CYFLD_CRYPTO_DATA_SIZE__OFFSET 0x00000010u
#define CYFLD_CRYPTO_DATA_SIZE__SIZE 0x00000010u
#define CYREG_CRYPTO_CRC_DATA_CTL1 0x400b0404u
#define CYFLD_CRYPTO_DATA_XOR__OFFSET 0x00000000u
#define CYFLD_CRYPTO_DATA_XOR__SIZE 0x00000008u
#define CYREG_CRYPTO_CRC_POL_CTL 0x400b0410u
#define CYFLD_CRYPTO_POLYNOMIAL__OFFSET 0x00000000u
#define CYFLD_CRYPTO_POLYNOMIAL__SIZE 0x00000020u
#define CYREG_CRYPTO_CRC_LFSR_CTL 0x400b0414u
#define CYREG_CRYPTO_CRC_REM_CTL0 0x400b0420u
#define CYFLD_CRYPTO_REM_REVERSE__OFFSET 0x00000000u
#define CYFLD_CRYPTO_REM_REVERSE__SIZE 0x00000001u
#define CYREG_CRYPTO_CRC_REM_CTL1 0x400b0424u
#define CYFLD_CRYPTO_REM_XOR__OFFSET 0x00000000u
#define CYFLD_CRYPTO_REM_XOR__SIZE 0x00000020u
#define CYREG_CRYPTO_CRC_REM 0x400b0428u
#define CYFLD_CRYPTO_REM__OFFSET 0x00000000u
#define CYFLD_CRYPTO_REM__SIZE 0x00000020u
#define CYREG_CRYPTO_INTR 0x400b07c0u
#define CYFLD_CRYPTO_DONE__OFFSET 0x00000000u
#define CYFLD_CRYPTO_DONE__SIZE 0x00000001u
#define CYFLD_CRYPTO_ACCESS_ERROR__OFFSET 0x00000001u
#define CYFLD_CRYPTO_ACCESS_ERROR__SIZE 0x00000001u
#define CYFLD_CRYPTO_TR_INITIALIZED__OFFSET 0x00000006u
#define CYFLD_CRYPTO_TR_INITIALIZED__SIZE 0x00000001u
#define CYFLD_CRYPTO_TR_DATA_AVAILABLE__OFFSET 0x00000007u
#define CYFLD_CRYPTO_TR_DATA_AVAILABLE__SIZE 0x00000001u
#define CYFLD_CRYPTO_TR_AP_DETECT__OFFSET 0x00000008u
#define CYFLD_CRYPTO_TR_AP_DETECT__SIZE 0x00000001u
#define CYFLD_CRYPTO_TR_RC_DETECT__OFFSET 0x00000009u
#define CYFLD_CRYPTO_TR_RC_DETECT__SIZE 0x00000001u
#define CYREG_CRYPTO_INTR_SET 0x400b07c4u
#define CYREG_CRYPTO_INTR_MASK 0x400b07c8u
#define CYREG_CRYPTO_INTR_MASKED 0x400b07ccu
#define CYREG_CRYPTO_MEM_BUFF0 0x400b0800u
#define CYREG_CRYPTO_MEM_BUFF1 0x400b0804u
#define CYREG_CRYPTO_MEM_BUFF2 0x400b0808u
#define CYREG_CRYPTO_MEM_BUFF3 0x400b080cu
#define CYREG_CRYPTO_MEM_BUFF4 0x400b0810u
#define CYREG_CRYPTO_MEM_BUFF5 0x400b0814u
#define CYREG_CRYPTO_MEM_BUFF6 0x400b0818u
#define CYREG_CRYPTO_MEM_BUFF7 0x400b081cu
#define CYREG_CRYPTO_MEM_BUFF8 0x400b0820u
#define CYREG_CRYPTO_MEM_BUFF9 0x400b0824u
#define CYREG_CRYPTO_MEM_BUFF10 0x400b0828u
#define CYREG_CRYPTO_MEM_BUFF11 0x400b082cu
#define CYREG_CRYPTO_MEM_BUFF12 0x400b0830u
#define CYREG_CRYPTO_MEM_BUFF13 0x400b0834u
#define CYREG_CRYPTO_MEM_BUFF14 0x400b0838u
#define CYREG_CRYPTO_MEM_BUFF15 0x400b083cu
#define CYREG_CRYPTO_MEM_BUFF16 0x400b0840u
#define CYREG_CRYPTO_MEM_BUFF17 0x400b0844u
#define CYREG_CRYPTO_MEM_BUFF18 0x400b0848u
#define CYREG_CRYPTO_MEM_BUFF19 0x400b084cu
#define CYREG_CRYPTO_MEM_BUFF20 0x400b0850u
#define CYREG_CRYPTO_MEM_BUFF21 0x400b0854u
#define CYREG_CRYPTO_MEM_BUFF22 0x400b0858u
#define CYREG_CRYPTO_MEM_BUFF23 0x400b085cu
#define CYREG_CRYPTO_MEM_BUFF24 0x400b0860u
#define CYREG_CRYPTO_MEM_BUFF25 0x400b0864u
#define CYREG_CRYPTO_MEM_BUFF26 0x400b0868u
#define CYREG_CRYPTO_MEM_BUFF27 0x400b086cu
#define CYREG_CRYPTO_MEM_BUFF28 0x400b0870u
#define CYREG_CRYPTO_MEM_BUFF29 0x400b0874u
#define CYREG_CRYPTO_MEM_BUFF30 0x400b0878u
#define CYREG_CRYPTO_MEM_BUFF31 0x400b087cu
#define CYREG_CRYPTO_MEM_BUFF32 0x400b0880u
#define CYREG_CRYPTO_MEM_BUFF33 0x400b0884u
#define CYREG_CRYPTO_MEM_BUFF34 0x400b0888u
#define CYREG_CRYPTO_MEM_BUFF35 0x400b088cu
#define CYREG_CRYPTO_MEM_BUFF36 0x400b0890u
#define CYREG_CRYPTO_MEM_BUFF37 0x400b0894u
#define CYREG_CRYPTO_MEM_BUFF38 0x400b0898u
#define CYREG_CRYPTO_MEM_BUFF39 0x400b089cu
#define CYREG_CRYPTO_MEM_BUFF40 0x400b08a0u
#define CYREG_CRYPTO_MEM_BUFF41 0x400b08a4u
#define CYREG_CRYPTO_MEM_BUFF42 0x400b08a8u
#define CYREG_CRYPTO_MEM_BUFF43 0x400b08acu
#define CYREG_CRYPTO_MEM_BUFF44 0x400b08b0u
#define CYREG_CRYPTO_MEM_BUFF45 0x400b08b4u
#define CYREG_CRYPTO_MEM_BUFF46 0x400b08b8u
#define CYREG_CRYPTO_MEM_BUFF47 0x400b08bcu
#define CYREG_CRYPTO_MEM_BUFF48 0x400b08c0u
#define CYREG_CRYPTO_MEM_BUFF49 0x400b08c4u
#define CYREG_CRYPTO_MEM_BUFF50 0x400b08c8u
#define CYREG_CRYPTO_MEM_BUFF51 0x400b08ccu
#define CYREG_CRYPTO_MEM_BUFF52 0x400b08d0u
#define CYREG_CRYPTO_MEM_BUFF53 0x400b08d4u
#define CYREG_CRYPTO_MEM_BUFF54 0x400b08d8u
#define CYREG_CRYPTO_MEM_BUFF55 0x400b08dcu
#define CYREG_CRYPTO_MEM_BUFF56 0x400b08e0u
#define CYREG_CRYPTO_MEM_BUFF57 0x400b08e4u
#define CYREG_CRYPTO_MEM_BUFF58 0x400b08e8u
#define CYREG_CRYPTO_MEM_BUFF59 0x400b08ecu
#define CYREG_CRYPTO_MEM_BUFF60 0x400b08f0u
#define CYREG_CRYPTO_MEM_BUFF61 0x400b08f4u
#define CYREG_CRYPTO_MEM_BUFF62 0x400b08f8u
#define CYREG_CRYPTO_MEM_BUFF63 0x400b08fcu
#define CYREG_CRYPTO_MEM_BUFF64 0x400b0900u
#define CYREG_CRYPTO_MEM_BUFF65 0x400b0904u
#define CYREG_CRYPTO_MEM_BUFF66 0x400b0908u
#define CYREG_CRYPTO_MEM_BUFF67 0x400b090cu
#define CYREG_CRYPTO_MEM_BUFF68 0x400b0910u
#define CYREG_CRYPTO_MEM_BUFF69 0x400b0914u
#define CYREG_CRYPTO_MEM_BUFF70 0x400b0918u
#define CYREG_CRYPTO_MEM_BUFF71 0x400b091cu
#define CYREG_CRYPTO_MEM_BUFF72 0x400b0920u
#define CYREG_CRYPTO_MEM_BUFF73 0x400b0924u
#define CYREG_CRYPTO_MEM_BUFF74 0x400b0928u
#define CYREG_CRYPTO_MEM_BUFF75 0x400b092cu
#define CYREG_CRYPTO_MEM_BUFF76 0x400b0930u
#define CYREG_CRYPTO_MEM_BUFF77 0x400b0934u
#define CYREG_CRYPTO_MEM_BUFF78 0x400b0938u
#define CYREG_CRYPTO_MEM_BUFF79 0x400b093cu
#define CYREG_CRYPTO_MEM_BUFF80 0x400b0940u
#define CYREG_CRYPTO_MEM_BUFF81 0x400b0944u
#define CYREG_CRYPTO_MEM_BUFF82 0x400b0948u
#define CYREG_CRYPTO_MEM_BUFF83 0x400b094cu
#define CYREG_CRYPTO_MEM_BUFF84 0x400b0950u
#define CYREG_CRYPTO_MEM_BUFF85 0x400b0954u
#define CYREG_CRYPTO_MEM_BUFF86 0x400b0958u
#define CYREG_CRYPTO_MEM_BUFF87 0x400b095cu
#define CYREG_CRYPTO_MEM_BUFF88 0x400b0960u
#define CYREG_CRYPTO_MEM_BUFF89 0x400b0964u
#define CYREG_CRYPTO_MEM_BUFF90 0x400b0968u
#define CYREG_CRYPTO_MEM_BUFF91 0x400b096cu
#define CYREG_CRYPTO_MEM_BUFF92 0x400b0970u
#define CYREG_CRYPTO_MEM_BUFF93 0x400b0974u
#define CYREG_CRYPTO_MEM_BUFF94 0x400b0978u
#define CYREG_CRYPTO_MEM_BUFF95 0x400b097cu
#define CYREG_CRYPTO_MEM_BUFF96 0x400b0980u
#define CYREG_CRYPTO_MEM_BUFF97 0x400b0984u
#define CYREG_CRYPTO_MEM_BUFF98 0x400b0988u
#define CYREG_CRYPTO_MEM_BUFF99 0x400b098cu
#define CYREG_CRYPTO_MEM_BUFF100 0x400b0990u
#define CYREG_CRYPTO_MEM_BUFF101 0x400b0994u
#define CYREG_CRYPTO_MEM_BUFF102 0x400b0998u
#define CYREG_CRYPTO_MEM_BUFF103 0x400b099cu
#define CYREG_CRYPTO_MEM_BUFF104 0x400b09a0u
#define CYREG_CRYPTO_MEM_BUFF105 0x400b09a4u
#define CYREG_CRYPTO_MEM_BUFF106 0x400b09a8u
#define CYREG_CRYPTO_MEM_BUFF107 0x400b09acu
#define CYREG_CRYPTO_MEM_BUFF108 0x400b09b0u
#define CYREG_CRYPTO_MEM_BUFF109 0x400b09b4u
#define CYREG_CRYPTO_MEM_BUFF110 0x400b09b8u
#define CYREG_CRYPTO_MEM_BUFF111 0x400b09bcu
#define CYREG_CRYPTO_MEM_BUFF112 0x400b09c0u
#define CYREG_CRYPTO_MEM_BUFF113 0x400b09c4u
#define CYREG_CRYPTO_MEM_BUFF114 0x400b09c8u
#define CYREG_CRYPTO_MEM_BUFF115 0x400b09ccu
#define CYREG_CRYPTO_MEM_BUFF116 0x400b09d0u
#define CYREG_CRYPTO_MEM_BUFF117 0x400b09d4u
#define CYREG_CRYPTO_MEM_BUFF118 0x400b09d8u
#define CYREG_CRYPTO_MEM_BUFF119 0x400b09dcu
#define CYREG_CRYPTO_MEM_BUFF120 0x400b09e0u
#define CYREG_CRYPTO_MEM_BUFF121 0x400b09e4u
#define CYREG_CRYPTO_MEM_BUFF122 0x400b09e8u
#define CYREG_CRYPTO_MEM_BUFF123 0x400b09ecu
#define CYREG_CRYPTO_MEM_BUFF124 0x400b09f0u
#define CYREG_CRYPTO_MEM_BUFF125 0x400b09f4u
#define CYREG_CRYPTO_MEM_BUFF126 0x400b09f8u
#define CYREG_CRYPTO_MEM_BUFF127 0x400b09fcu
#define CYREG_CRYPTO_MEM_BUFF128 0x400b0a00u
#define CYREG_CRYPTO_MEM_BUFF129 0x400b0a04u
#define CYREG_CRYPTO_MEM_BUFF130 0x400b0a08u
#define CYREG_CRYPTO_MEM_BUFF131 0x400b0a0cu
#define CYREG_CRYPTO_MEM_BUFF132 0x400b0a10u
#define CYREG_CRYPTO_MEM_BUFF133 0x400b0a14u
#define CYREG_CRYPTO_MEM_BUFF134 0x400b0a18u
#define CYREG_CRYPTO_MEM_BUFF135 0x400b0a1cu
#define CYREG_CRYPTO_MEM_BUFF136 0x400b0a20u
#define CYREG_CRYPTO_MEM_BUFF137 0x400b0a24u
#define CYREG_CRYPTO_MEM_BUFF138 0x400b0a28u
#define CYREG_CRYPTO_MEM_BUFF139 0x400b0a2cu
#define CYREG_CRYPTO_MEM_BUFF140 0x400b0a30u
#define CYREG_CRYPTO_MEM_BUFF141 0x400b0a34u
#define CYREG_CRYPTO_MEM_BUFF142 0x400b0a38u
#define CYREG_CRYPTO_MEM_BUFF143 0x400b0a3cu
#define CYREG_CRYPTO_MEM_BUFF144 0x400b0a40u
#define CYREG_CRYPTO_MEM_BUFF145 0x400b0a44u
#define CYREG_CRYPTO_MEM_BUFF146 0x400b0a48u
#define CYREG_CRYPTO_MEM_BUFF147 0x400b0a4cu
#define CYREG_CRYPTO_MEM_BUFF148 0x400b0a50u
#define CYREG_CRYPTO_MEM_BUFF149 0x400b0a54u
#define CYREG_CRYPTO_MEM_BUFF150 0x400b0a58u
#define CYREG_CRYPTO_MEM_BUFF151 0x400b0a5cu
#define CYREG_CRYPTO_MEM_BUFF152 0x400b0a60u
#define CYREG_CRYPTO_MEM_BUFF153 0x400b0a64u
#define CYREG_CRYPTO_MEM_BUFF154 0x400b0a68u
#define CYREG_CRYPTO_MEM_BUFF155 0x400b0a6cu
#define CYREG_CRYPTO_MEM_BUFF156 0x400b0a70u
#define CYREG_CRYPTO_MEM_BUFF157 0x400b0a74u
#define CYREG_CRYPTO_MEM_BUFF158 0x400b0a78u
#define CYREG_CRYPTO_MEM_BUFF159 0x400b0a7cu
#define CYREG_CRYPTO_MEM_BUFF160 0x400b0a80u
#define CYREG_CRYPTO_MEM_BUFF161 0x400b0a84u
#define CYREG_CRYPTO_MEM_BUFF162 0x400b0a88u
#define CYREG_CRYPTO_MEM_BUFF163 0x400b0a8cu
#define CYREG_CRYPTO_MEM_BUFF164 0x400b0a90u
#define CYREG_CRYPTO_MEM_BUFF165 0x400b0a94u
#define CYREG_CRYPTO_MEM_BUFF166 0x400b0a98u
#define CYREG_CRYPTO_MEM_BUFF167 0x400b0a9cu
#define CYREG_CRYPTO_MEM_BUFF168 0x400b0aa0u
#define CYREG_CRYPTO_MEM_BUFF169 0x400b0aa4u
#define CYREG_CRYPTO_MEM_BUFF170 0x400b0aa8u
#define CYREG_CRYPTO_MEM_BUFF171 0x400b0aacu
#define CYREG_CRYPTO_MEM_BUFF172 0x400b0ab0u
#define CYREG_CRYPTO_MEM_BUFF173 0x400b0ab4u
#define CYREG_CRYPTO_MEM_BUFF174 0x400b0ab8u
#define CYREG_CRYPTO_MEM_BUFF175 0x400b0abcu
#define CYREG_CRYPTO_MEM_BUFF176 0x400b0ac0u
#define CYREG_CRYPTO_MEM_BUFF177 0x400b0ac4u
#define CYREG_CRYPTO_MEM_BUFF178 0x400b0ac8u
#define CYREG_CRYPTO_MEM_BUFF179 0x400b0accu
#define CYREG_CRYPTO_MEM_BUFF180 0x400b0ad0u
#define CYREG_CRYPTO_MEM_BUFF181 0x400b0ad4u
#define CYREG_CRYPTO_MEM_BUFF182 0x400b0ad8u
#define CYREG_CRYPTO_MEM_BUFF183 0x400b0adcu
#define CYREG_CRYPTO_MEM_BUFF184 0x400b0ae0u
#define CYREG_CRYPTO_MEM_BUFF185 0x400b0ae4u
#define CYREG_CRYPTO_MEM_BUFF186 0x400b0ae8u
#define CYREG_CRYPTO_MEM_BUFF187 0x400b0aecu
#define CYREG_CRYPTO_MEM_BUFF188 0x400b0af0u
#define CYREG_CRYPTO_MEM_BUFF189 0x400b0af4u
#define CYREG_CRYPTO_MEM_BUFF190 0x400b0af8u
#define CYREG_CRYPTO_MEM_BUFF191 0x400b0afcu
#define CYREG_CRYPTO_MEM_BUFF192 0x400b0b00u
#define CYREG_CRYPTO_MEM_BUFF193 0x400b0b04u
#define CYREG_CRYPTO_MEM_BUFF194 0x400b0b08u
#define CYREG_CRYPTO_MEM_BUFF195 0x400b0b0cu
#define CYREG_CRYPTO_MEM_BUFF196 0x400b0b10u
#define CYREG_CRYPTO_MEM_BUFF197 0x400b0b14u
#define CYREG_CRYPTO_MEM_BUFF198 0x400b0b18u
#define CYREG_CRYPTO_MEM_BUFF199 0x400b0b1cu
#define CYREG_CRYPTO_MEM_BUFF200 0x400b0b20u
#define CYREG_CRYPTO_MEM_BUFF201 0x400b0b24u
#define CYREG_CRYPTO_MEM_BUFF202 0x400b0b28u
#define CYREG_CRYPTO_MEM_BUFF203 0x400b0b2cu
#define CYREG_CRYPTO_MEM_BUFF204 0x400b0b30u
#define CYREG_CRYPTO_MEM_BUFF205 0x400b0b34u
#define CYREG_CRYPTO_MEM_BUFF206 0x400b0b38u
#define CYREG_CRYPTO_MEM_BUFF207 0x400b0b3cu
#define CYREG_CRYPTO_MEM_BUFF208 0x400b0b40u
#define CYREG_CRYPTO_MEM_BUFF209 0x400b0b44u
#define CYREG_CRYPTO_MEM_BUFF210 0x400b0b48u
#define CYREG_CRYPTO_MEM_BUFF211 0x400b0b4cu
#define CYREG_CRYPTO_MEM_BUFF212 0x400b0b50u
#define CYREG_CRYPTO_MEM_BUFF213 0x400b0b54u
#define CYREG_CRYPTO_MEM_BUFF214 0x400b0b58u
#define CYREG_CRYPTO_MEM_BUFF215 0x400b0b5cu
#define CYREG_CRYPTO_MEM_BUFF216 0x400b0b60u
#define CYREG_CRYPTO_MEM_BUFF217 0x400b0b64u
#define CYREG_CRYPTO_MEM_BUFF218 0x400b0b68u
#define CYREG_CRYPTO_MEM_BUFF219 0x400b0b6cu
#define CYREG_CRYPTO_MEM_BUFF220 0x400b0b70u
#define CYREG_CRYPTO_MEM_BUFF221 0x400b0b74u
#define CYREG_CRYPTO_MEM_BUFF222 0x400b0b78u
#define CYREG_CRYPTO_MEM_BUFF223 0x400b0b7cu
#define CYREG_CRYPTO_MEM_BUFF224 0x400b0b80u
#define CYREG_CRYPTO_MEM_BUFF225 0x400b0b84u
#define CYREG_CRYPTO_MEM_BUFF226 0x400b0b88u
#define CYREG_CRYPTO_MEM_BUFF227 0x400b0b8cu
#define CYREG_CRYPTO_MEM_BUFF228 0x400b0b90u
#define CYREG_CRYPTO_MEM_BUFF229 0x400b0b94u
#define CYREG_CRYPTO_MEM_BUFF230 0x400b0b98u
#define CYREG_CRYPTO_MEM_BUFF231 0x400b0b9cu
#define CYREG_CRYPTO_MEM_BUFF232 0x400b0ba0u
#define CYREG_CRYPTO_MEM_BUFF233 0x400b0ba4u
#define CYREG_CRYPTO_MEM_BUFF234 0x400b0ba8u
#define CYREG_CRYPTO_MEM_BUFF235 0x400b0bacu
#define CYREG_CRYPTO_MEM_BUFF236 0x400b0bb0u
#define CYREG_CRYPTO_MEM_BUFF237 0x400b0bb4u
#define CYREG_CRYPTO_MEM_BUFF238 0x400b0bb8u
#define CYREG_CRYPTO_MEM_BUFF239 0x400b0bbcu
#define CYREG_CRYPTO_MEM_BUFF240 0x400b0bc0u
#define CYREG_CRYPTO_MEM_BUFF241 0x400b0bc4u
#define CYREG_CRYPTO_MEM_BUFF242 0x400b0bc8u
#define CYREG_CRYPTO_MEM_BUFF243 0x400b0bccu
#define CYREG_CRYPTO_MEM_BUFF244 0x400b0bd0u
#define CYREG_CRYPTO_MEM_BUFF245 0x400b0bd4u
#define CYREG_CRYPTO_MEM_BUFF246 0x400b0bd8u
#define CYREG_CRYPTO_MEM_BUFF247 0x400b0bdcu
#define CYREG_CRYPTO_MEM_BUFF248 0x400b0be0u
#define CYREG_CRYPTO_MEM_BUFF249 0x400b0be4u
#define CYREG_CRYPTO_MEM_BUFF250 0x400b0be8u
#define CYREG_CRYPTO_MEM_BUFF251 0x400b0becu
#define CYREG_CRYPTO_MEM_BUFF252 0x400b0bf0u
#define CYREG_CRYPTO_MEM_BUFF253 0x400b0bf4u
#define CYREG_CRYPTO_MEM_BUFF254 0x400b0bf8u
#define CYREG_CRYPTO_MEM_BUFF255 0x400b0bfcu
#define CYREG_CRYPTO_MEM_BUFF256 0x400b0c00u
#define CYREG_CRYPTO_MEM_BUFF257 0x400b0c04u
#define CYREG_CRYPTO_MEM_BUFF258 0x400b0c08u
#define CYREG_CRYPTO_MEM_BUFF259 0x400b0c0cu
#define CYREG_CRYPTO_MEM_BUFF260 0x400b0c10u
#define CYREG_CRYPTO_MEM_BUFF261 0x400b0c14u
#define CYREG_CRYPTO_MEM_BUFF262 0x400b0c18u
#define CYREG_CRYPTO_MEM_BUFF263 0x400b0c1cu
#define CYREG_CRYPTO_MEM_BUFF264 0x400b0c20u
#define CYREG_CRYPTO_MEM_BUFF265 0x400b0c24u
#define CYREG_CRYPTO_MEM_BUFF266 0x400b0c28u
#define CYREG_CRYPTO_MEM_BUFF267 0x400b0c2cu
#define CYREG_CRYPTO_MEM_BUFF268 0x400b0c30u
#define CYREG_CRYPTO_MEM_BUFF269 0x400b0c34u
#define CYREG_CRYPTO_MEM_BUFF270 0x400b0c38u
#define CYREG_CRYPTO_MEM_BUFF271 0x400b0c3cu
#define CYREG_CRYPTO_MEM_BUFF272 0x400b0c40u
#define CYREG_CRYPTO_MEM_BUFF273 0x400b0c44u
#define CYREG_CRYPTO_MEM_BUFF274 0x400b0c48u
#define CYREG_CRYPTO_MEM_BUFF275 0x400b0c4cu
#define CYREG_CRYPTO_MEM_BUFF276 0x400b0c50u
#define CYREG_CRYPTO_MEM_BUFF277 0x400b0c54u
#define CYREG_CRYPTO_MEM_BUFF278 0x400b0c58u
#define CYREG_CRYPTO_MEM_BUFF279 0x400b0c5cu
#define CYREG_CRYPTO_MEM_BUFF280 0x400b0c60u
#define CYREG_CRYPTO_MEM_BUFF281 0x400b0c64u
#define CYREG_CRYPTO_MEM_BUFF282 0x400b0c68u
#define CYREG_CRYPTO_MEM_BUFF283 0x400b0c6cu
#define CYREG_CRYPTO_MEM_BUFF284 0x400b0c70u
#define CYREG_CRYPTO_MEM_BUFF285 0x400b0c74u
#define CYREG_CRYPTO_MEM_BUFF286 0x400b0c78u
#define CYREG_CRYPTO_MEM_BUFF287 0x400b0c7cu
#define CYREG_CRYPTO_MEM_BUFF288 0x400b0c80u
#define CYREG_CRYPTO_MEM_BUFF289 0x400b0c84u
#define CYREG_CRYPTO_MEM_BUFF290 0x400b0c88u
#define CYREG_CRYPTO_MEM_BUFF291 0x400b0c8cu
#define CYREG_CRYPTO_MEM_BUFF292 0x400b0c90u
#define CYREG_CRYPTO_MEM_BUFF293 0x400b0c94u
#define CYREG_CRYPTO_MEM_BUFF294 0x400b0c98u
#define CYREG_CRYPTO_MEM_BUFF295 0x400b0c9cu
#define CYREG_CRYPTO_MEM_BUFF296 0x400b0ca0u
#define CYREG_CRYPTO_MEM_BUFF297 0x400b0ca4u
#define CYREG_CRYPTO_MEM_BUFF298 0x400b0ca8u
#define CYREG_CRYPTO_MEM_BUFF299 0x400b0cacu
#define CYREG_CRYPTO_MEM_BUFF300 0x400b0cb0u
#define CYREG_CRYPTO_MEM_BUFF301 0x400b0cb4u
#define CYREG_CRYPTO_MEM_BUFF302 0x400b0cb8u
#define CYREG_CRYPTO_MEM_BUFF303 0x400b0cbcu
#define CYREG_CRYPTO_MEM_BUFF304 0x400b0cc0u
#define CYREG_CRYPTO_MEM_BUFF305 0x400b0cc4u
#define CYREG_CRYPTO_MEM_BUFF306 0x400b0cc8u
#define CYREG_CRYPTO_MEM_BUFF307 0x400b0cccu
#define CYREG_CRYPTO_MEM_BUFF308 0x400b0cd0u
#define CYREG_CRYPTO_MEM_BUFF309 0x400b0cd4u
#define CYREG_CRYPTO_MEM_BUFF310 0x400b0cd8u
#define CYREG_CRYPTO_MEM_BUFF311 0x400b0cdcu
#define CYREG_CRYPTO_MEM_BUFF312 0x400b0ce0u
#define CYREG_CRYPTO_MEM_BUFF313 0x400b0ce4u
#define CYREG_CRYPTO_MEM_BUFF314 0x400b0ce8u
#define CYREG_CRYPTO_MEM_BUFF315 0x400b0cecu
#define CYREG_CRYPTO_MEM_BUFF316 0x400b0cf0u
#define CYREG_CRYPTO_MEM_BUFF317 0x400b0cf4u
#define CYREG_CRYPTO_MEM_BUFF318 0x400b0cf8u
#define CYREG_CRYPTO_MEM_BUFF319 0x400b0cfcu
#define CYREG_CRYPTO_MEM_BUFF320 0x400b0d00u
#define CYREG_CRYPTO_MEM_BUFF321 0x400b0d04u
#define CYREG_CRYPTO_MEM_BUFF322 0x400b0d08u
#define CYREG_CRYPTO_MEM_BUFF323 0x400b0d0cu
#define CYREG_CRYPTO_MEM_BUFF324 0x400b0d10u
#define CYREG_CRYPTO_MEM_BUFF325 0x400b0d14u
#define CYREG_CRYPTO_MEM_BUFF326 0x400b0d18u
#define CYREG_CRYPTO_MEM_BUFF327 0x400b0d1cu
#define CYREG_CRYPTO_MEM_BUFF328 0x400b0d20u
#define CYREG_CRYPTO_MEM_BUFF329 0x400b0d24u
#define CYREG_CRYPTO_MEM_BUFF330 0x400b0d28u
#define CYREG_CRYPTO_MEM_BUFF331 0x400b0d2cu
#define CYREG_CRYPTO_MEM_BUFF332 0x400b0d30u
#define CYREG_CRYPTO_MEM_BUFF333 0x400b0d34u
#define CYREG_CRYPTO_MEM_BUFF334 0x400b0d38u
#define CYREG_CRYPTO_MEM_BUFF335 0x400b0d3cu
#define CYREG_CRYPTO_MEM_BUFF336 0x400b0d40u
#define CYREG_CRYPTO_MEM_BUFF337 0x400b0d44u
#define CYREG_CRYPTO_MEM_BUFF338 0x400b0d48u
#define CYREG_CRYPTO_MEM_BUFF339 0x400b0d4cu
#define CYREG_CRYPTO_MEM_BUFF340 0x400b0d50u
#define CYREG_CRYPTO_MEM_BUFF341 0x400b0d54u
#define CYREG_CRYPTO_MEM_BUFF342 0x400b0d58u
#define CYREG_CRYPTO_MEM_BUFF343 0x400b0d5cu
#define CYREG_CRYPTO_MEM_BUFF344 0x400b0d60u
#define CYREG_CRYPTO_MEM_BUFF345 0x400b0d64u
#define CYREG_CRYPTO_MEM_BUFF346 0x400b0d68u
#define CYREG_CRYPTO_MEM_BUFF347 0x400b0d6cu
#define CYREG_CRYPTO_MEM_BUFF348 0x400b0d70u
#define CYREG_CRYPTO_MEM_BUFF349 0x400b0d74u
#define CYREG_CRYPTO_MEM_BUFF350 0x400b0d78u
#define CYREG_CRYPTO_MEM_BUFF351 0x400b0d7cu
#define CYREG_CRYPTO_MEM_BUFF352 0x400b0d80u
#define CYREG_CRYPTO_MEM_BUFF353 0x400b0d84u
#define CYREG_CRYPTO_MEM_BUFF354 0x400b0d88u
#define CYREG_CRYPTO_MEM_BUFF355 0x400b0d8cu
#define CYREG_CRYPTO_MEM_BUFF356 0x400b0d90u
#define CYREG_CRYPTO_MEM_BUFF357 0x400b0d94u
#define CYREG_CRYPTO_MEM_BUFF358 0x400b0d98u
#define CYREG_CRYPTO_MEM_BUFF359 0x400b0d9cu
#define CYREG_CRYPTO_MEM_BUFF360 0x400b0da0u
#define CYREG_CRYPTO_MEM_BUFF361 0x400b0da4u
#define CYREG_CRYPTO_MEM_BUFF362 0x400b0da8u
#define CYREG_CRYPTO_MEM_BUFF363 0x400b0dacu
#define CYREG_CRYPTO_MEM_BUFF364 0x400b0db0u
#define CYREG_CRYPTO_MEM_BUFF365 0x400b0db4u
#define CYREG_CRYPTO_MEM_BUFF366 0x400b0db8u
#define CYREG_CRYPTO_MEM_BUFF367 0x400b0dbcu
#define CYREG_CRYPTO_MEM_BUFF368 0x400b0dc0u
#define CYREG_CRYPTO_MEM_BUFF369 0x400b0dc4u
#define CYREG_CRYPTO_MEM_BUFF370 0x400b0dc8u
#define CYREG_CRYPTO_MEM_BUFF371 0x400b0dccu
#define CYREG_CRYPTO_MEM_BUFF372 0x400b0dd0u
#define CYREG_CRYPTO_MEM_BUFF373 0x400b0dd4u
#define CYREG_CRYPTO_MEM_BUFF374 0x400b0dd8u
#define CYREG_CRYPTO_MEM_BUFF375 0x400b0ddcu
#define CYREG_CRYPTO_MEM_BUFF376 0x400b0de0u
#define CYREG_CRYPTO_MEM_BUFF377 0x400b0de4u
#define CYREG_CRYPTO_MEM_BUFF378 0x400b0de8u
#define CYREG_CRYPTO_MEM_BUFF379 0x400b0decu
#define CYREG_CRYPTO_MEM_BUFF380 0x400b0df0u
#define CYREG_CRYPTO_MEM_BUFF381 0x400b0df4u
#define CYREG_CRYPTO_MEM_BUFF382 0x400b0df8u
#define CYREG_CRYPTO_MEM_BUFF383 0x400b0dfcu
#define CYREG_CRYPTO_MEM_BUFF384 0x400b0e00u
#define CYREG_CRYPTO_MEM_BUFF385 0x400b0e04u
#define CYREG_CRYPTO_MEM_BUFF386 0x400b0e08u
#define CYREG_CRYPTO_MEM_BUFF387 0x400b0e0cu
#define CYREG_CRYPTO_MEM_BUFF388 0x400b0e10u
#define CYREG_CRYPTO_MEM_BUFF389 0x400b0e14u
#define CYREG_CRYPTO_MEM_BUFF390 0x400b0e18u
#define CYREG_CRYPTO_MEM_BUFF391 0x400b0e1cu
#define CYREG_CRYPTO_MEM_BUFF392 0x400b0e20u
#define CYREG_CRYPTO_MEM_BUFF393 0x400b0e24u
#define CYREG_CRYPTO_MEM_BUFF394 0x400b0e28u
#define CYREG_CRYPTO_MEM_BUFF395 0x400b0e2cu
#define CYREG_CRYPTO_MEM_BUFF396 0x400b0e30u
#define CYREG_CRYPTO_MEM_BUFF397 0x400b0e34u
#define CYREG_CRYPTO_MEM_BUFF398 0x400b0e38u
#define CYREG_CRYPTO_MEM_BUFF399 0x400b0e3cu
#define CYREG_CRYPTO_MEM_BUFF400 0x400b0e40u
#define CYREG_CRYPTO_MEM_BUFF401 0x400b0e44u
#define CYREG_CRYPTO_MEM_BUFF402 0x400b0e48u
#define CYREG_CRYPTO_MEM_BUFF403 0x400b0e4cu
#define CYREG_CRYPTO_MEM_BUFF404 0x400b0e50u
#define CYREG_CRYPTO_MEM_BUFF405 0x400b0e54u
#define CYREG_CRYPTO_MEM_BUFF406 0x400b0e58u
#define CYREG_CRYPTO_MEM_BUFF407 0x400b0e5cu
#define CYREG_CRYPTO_MEM_BUFF408 0x400b0e60u
#define CYREG_CRYPTO_MEM_BUFF409 0x400b0e64u
#define CYREG_CRYPTO_MEM_BUFF410 0x400b0e68u
#define CYREG_CRYPTO_MEM_BUFF411 0x400b0e6cu
#define CYREG_CRYPTO_MEM_BUFF412 0x400b0e70u
#define CYREG_CRYPTO_MEM_BUFF413 0x400b0e74u
#define CYREG_CRYPTO_MEM_BUFF414 0x400b0e78u
#define CYREG_CRYPTO_MEM_BUFF415 0x400b0e7cu
#define CYREG_CRYPTO_MEM_BUFF416 0x400b0e80u
#define CYREG_CRYPTO_MEM_BUFF417 0x400b0e84u
#define CYREG_CRYPTO_MEM_BUFF418 0x400b0e88u
#define CYREG_CRYPTO_MEM_BUFF419 0x400b0e8cu
#define CYREG_CRYPTO_MEM_BUFF420 0x400b0e90u
#define CYREG_CRYPTO_MEM_BUFF421 0x400b0e94u
#define CYREG_CRYPTO_MEM_BUFF422 0x400b0e98u
#define CYREG_CRYPTO_MEM_BUFF423 0x400b0e9cu
#define CYREG_CRYPTO_MEM_BUFF424 0x400b0ea0u
#define CYREG_CRYPTO_MEM_BUFF425 0x400b0ea4u
#define CYREG_CRYPTO_MEM_BUFF426 0x400b0ea8u
#define CYREG_CRYPTO_MEM_BUFF427 0x400b0eacu
#define CYREG_CRYPTO_MEM_BUFF428 0x400b0eb0u
#define CYREG_CRYPTO_MEM_BUFF429 0x400b0eb4u
#define CYREG_CRYPTO_MEM_BUFF430 0x400b0eb8u
#define CYREG_CRYPTO_MEM_BUFF431 0x400b0ebcu
#define CYREG_CRYPTO_MEM_BUFF432 0x400b0ec0u
#define CYREG_CRYPTO_MEM_BUFF433 0x400b0ec4u
#define CYREG_CRYPTO_MEM_BUFF434 0x400b0ec8u
#define CYREG_CRYPTO_MEM_BUFF435 0x400b0eccu
#define CYREG_CRYPTO_MEM_BUFF436 0x400b0ed0u
#define CYREG_CRYPTO_MEM_BUFF437 0x400b0ed4u
#define CYREG_CRYPTO_MEM_BUFF438 0x400b0ed8u
#define CYREG_CRYPTO_MEM_BUFF439 0x400b0edcu
#define CYREG_CRYPTO_MEM_BUFF440 0x400b0ee0u
#define CYREG_CRYPTO_MEM_BUFF441 0x400b0ee4u
#define CYREG_CRYPTO_MEM_BUFF442 0x400b0ee8u
#define CYREG_CRYPTO_MEM_BUFF443 0x400b0eecu
#define CYREG_CRYPTO_MEM_BUFF444 0x400b0ef0u
#define CYREG_CRYPTO_MEM_BUFF445 0x400b0ef4u
#define CYREG_CRYPTO_MEM_BUFF446 0x400b0ef8u
#define CYREG_CRYPTO_MEM_BUFF447 0x400b0efcu
#define CYREG_CRYPTO_MEM_BUFF448 0x400b0f00u
#define CYREG_CRYPTO_MEM_BUFF449 0x400b0f04u
#define CYREG_CRYPTO_MEM_BUFF450 0x400b0f08u
#define CYREG_CRYPTO_MEM_BUFF451 0x400b0f0cu
#define CYREG_CRYPTO_MEM_BUFF452 0x400b0f10u
#define CYREG_CRYPTO_MEM_BUFF453 0x400b0f14u
#define CYREG_CRYPTO_MEM_BUFF454 0x400b0f18u
#define CYREG_CRYPTO_MEM_BUFF455 0x400b0f1cu
#define CYREG_CRYPTO_MEM_BUFF456 0x400b0f20u
#define CYREG_CRYPTO_MEM_BUFF457 0x400b0f24u
#define CYREG_CRYPTO_MEM_BUFF458 0x400b0f28u
#define CYREG_CRYPTO_MEM_BUFF459 0x400b0f2cu
#define CYREG_CRYPTO_MEM_BUFF460 0x400b0f30u
#define CYREG_CRYPTO_MEM_BUFF461 0x400b0f34u
#define CYREG_CRYPTO_MEM_BUFF462 0x400b0f38u
#define CYREG_CRYPTO_MEM_BUFF463 0x400b0f3cu
#define CYREG_CRYPTO_MEM_BUFF464 0x400b0f40u
#define CYREG_CRYPTO_MEM_BUFF465 0x400b0f44u
#define CYREG_CRYPTO_MEM_BUFF466 0x400b0f48u
#define CYREG_CRYPTO_MEM_BUFF467 0x400b0f4cu
#define CYREG_CRYPTO_MEM_BUFF468 0x400b0f50u
#define CYREG_CRYPTO_MEM_BUFF469 0x400b0f54u
#define CYREG_CRYPTO_MEM_BUFF470 0x400b0f58u
#define CYREG_CRYPTO_MEM_BUFF471 0x400b0f5cu
#define CYREG_CRYPTO_MEM_BUFF472 0x400b0f60u
#define CYREG_CRYPTO_MEM_BUFF473 0x400b0f64u
#define CYREG_CRYPTO_MEM_BUFF474 0x400b0f68u
#define CYREG_CRYPTO_MEM_BUFF475 0x400b0f6cu
#define CYREG_CRYPTO_MEM_BUFF476 0x400b0f70u
#define CYREG_CRYPTO_MEM_BUFF477 0x400b0f74u
#define CYREG_CRYPTO_MEM_BUFF478 0x400b0f78u
#define CYREG_CRYPTO_MEM_BUFF479 0x400b0f7cu
#define CYREG_CRYPTO_MEM_BUFF480 0x400b0f80u
#define CYREG_CRYPTO_MEM_BUFF481 0x400b0f84u
#define CYREG_CRYPTO_MEM_BUFF482 0x400b0f88u
#define CYREG_CRYPTO_MEM_BUFF483 0x400b0f8cu
#define CYREG_CRYPTO_MEM_BUFF484 0x400b0f90u
#define CYREG_CRYPTO_MEM_BUFF485 0x400b0f94u
#define CYREG_CRYPTO_MEM_BUFF486 0x400b0f98u
#define CYREG_CRYPTO_MEM_BUFF487 0x400b0f9cu
#define CYREG_CRYPTO_MEM_BUFF488 0x400b0fa0u
#define CYREG_CRYPTO_MEM_BUFF489 0x400b0fa4u
#define CYREG_CRYPTO_MEM_BUFF490 0x400b0fa8u
#define CYREG_CRYPTO_MEM_BUFF491 0x400b0facu
#define CYREG_CRYPTO_MEM_BUFF492 0x400b0fb0u
#define CYREG_CRYPTO_MEM_BUFF493 0x400b0fb4u
#define CYREG_CRYPTO_MEM_BUFF494 0x400b0fb8u
#define CYREG_CRYPTO_MEM_BUFF495 0x400b0fbcu
#define CYREG_CRYPTO_MEM_BUFF496 0x400b0fc0u
#define CYREG_CRYPTO_MEM_BUFF497 0x400b0fc4u
#define CYREG_CRYPTO_MEM_BUFF498 0x400b0fc8u
#define CYREG_CRYPTO_MEM_BUFF499 0x400b0fccu
#define CYREG_CRYPTO_MEM_BUFF500 0x400b0fd0u
#define CYREG_CRYPTO_MEM_BUFF501 0x400b0fd4u
#define CYREG_CRYPTO_MEM_BUFF502 0x400b0fd8u
#define CYREG_CRYPTO_MEM_BUFF503 0x400b0fdcu
#define CYREG_CRYPTO_MEM_BUFF504 0x400b0fe0u
#define CYREG_CRYPTO_MEM_BUFF505 0x400b0fe4u
#define CYREG_CRYPTO_MEM_BUFF506 0x400b0fe8u
#define CYREG_CRYPTO_MEM_BUFF507 0x400b0fecu
#define CYREG_CRYPTO_MEM_BUFF508 0x400b0ff0u
#define CYREG_CRYPTO_MEM_BUFF509 0x400b0ff4u
#define CYREG_CRYPTO_MEM_BUFF510 0x400b0ff8u
#define CYREG_CRYPTO_MEM_BUFF511 0x400b0ffcu
#define CYREG_CRYPTO_PRIV_BUF 0x400bff00u
#define CYFLD_CRYPTO_BUF_PRIV_LIMIT__OFFSET 0x00000000u
#define CYFLD_CRYPTO_BUF_PRIV_LIMIT__SIZE 0x00000003u
#define CYDEV_USBDEVv2_BASE 0x400c0000u
#define CYDEV_USBDEVv2_SIZE 0x00010000u
#define CYREG_USBDEVv2_EP0_DR0 0x400c0000u
#define CYFLD_USBDEVv2_DATA_BYTE__OFFSET 0x00000000u
#define CYFLD_USBDEVv2_DATA_BYTE__SIZE 0x00000008u
#define CYREG_USBDEVv2_EP0_DR1 0x400c0004u
#define CYREG_USBDEVv2_EP0_DR2 0x400c0008u
#define CYREG_USBDEVv2_EP0_DR3 0x400c000cu
#define CYREG_USBDEVv2_EP0_DR4 0x400c0010u
#define CYREG_USBDEVv2_EP0_DR5 0x400c0014u
#define CYREG_USBDEVv2_EP0_DR6 0x400c0018u
#define CYREG_USBDEVv2_EP0_DR7 0x400c001cu
#define CYREG_USBDEVv2_CR0 0x400c0020u
#define CYFLD_USBDEVv2_DEVICE_ADDRESS__OFFSET 0x00000000u
#define CYFLD_USBDEVv2_DEVICE_ADDRESS__SIZE 0x00000007u
#define CYFLD_USBDEVv2_USB_ENABLE__OFFSET 0x00000007u
#define CYFLD_USBDEVv2_USB_ENABLE__SIZE 0x00000001u
#define CYREG_USBDEVv2_CR1 0x400c0024u
#define CYFLD_USBDEVv2_REG_ENABLE__OFFSET 0x00000000u
#define CYFLD_USBDEVv2_REG_ENABLE__SIZE 0x00000001u
#define CYFLD_USBDEVv2_ENABLE_LOCK__OFFSET 0x00000001u
#define CYFLD_USBDEVv2_ENABLE_LOCK__SIZE 0x00000001u
#define CYFLD_USBDEVv2_BUS_ACTIVITY__OFFSET 0x00000002u
#define CYFLD_USBDEVv2_BUS_ACTIVITY__SIZE 0x00000001u
#define CYFLD_USBDEVv2_TRIM_OFFSET_MSB__OFFSET 0x00000003u
#define CYFLD_USBDEVv2_TRIM_OFFSET_MSB__SIZE 0x00000001u
#define CYREG_USBDEVv2_SIE_EP_INT_EN 0x400c0028u
#define CYFLD_USBDEVv2_EP1_INTR_EN__OFFSET 0x00000000u
#define CYFLD_USBDEVv2_EP1_INTR_EN__SIZE 0x00000001u
#define CYFLD_USBDEVv2_EP2_INTR_EN__OFFSET 0x00000001u
#define CYFLD_USBDEVv2_EP2_INTR_EN__SIZE 0x00000001u
#define CYFLD_USBDEVv2_EP3_INTR_EN__OFFSET 0x00000002u
#define CYFLD_USBDEVv2_EP3_INTR_EN__SIZE 0x00000001u
#define CYFLD_USBDEVv2_EP4_INTR_EN__OFFSET 0x00000003u
#define CYFLD_USBDEVv2_EP4_INTR_EN__SIZE 0x00000001u
#define CYFLD_USBDEVv2_EP5_INTR_EN__OFFSET 0x00000004u
#define CYFLD_USBDEVv2_EP5_INTR_EN__SIZE 0x00000001u
#define CYFLD_USBDEVv2_EP6_INTR_EN__OFFSET 0x00000005u
#define CYFLD_USBDEVv2_EP6_INTR_EN__SIZE 0x00000001u
#define CYFLD_USBDEVv2_EP7_INTR_EN__OFFSET 0x00000006u
#define CYFLD_USBDEVv2_EP7_INTR_EN__SIZE 0x00000001u
#define CYFLD_USBDEVv2_EP8_INTR_EN__OFFSET 0x00000007u
#define CYFLD_USBDEVv2_EP8_INTR_EN__SIZE 0x00000001u
#define CYREG_USBDEVv2_SIE_EP_INT_SR 0x400c002cu
#define CYFLD_USBDEVv2_EP1_INTR__OFFSET 0x00000000u
#define CYFLD_USBDEVv2_EP1_INTR__SIZE 0x00000001u
#define CYFLD_USBDEVv2_EP2_INTR__OFFSET 0x00000001u
#define CYFLD_USBDEVv2_EP2_INTR__SIZE 0x00000001u
#define CYFLD_USBDEVv2_EP3_INTR__OFFSET 0x00000002u
#define CYFLD_USBDEVv2_EP3_INTR__SIZE 0x00000001u
#define CYFLD_USBDEVv2_EP4_INTR__OFFSET 0x00000003u
#define CYFLD_USBDEVv2_EP4_INTR__SIZE 0x00000001u
#define CYFLD_USBDEVv2_EP5_INTR__OFFSET 0x00000004u
#define CYFLD_USBDEVv2_EP5_INTR__SIZE 0x00000001u
#define CYFLD_USBDEVv2_EP6_INTR__OFFSET 0x00000005u
#define CYFLD_USBDEVv2_EP6_INTR__SIZE 0x00000001u
#define CYFLD_USBDEVv2_EP7_INTR__OFFSET 0x00000006u
#define CYFLD_USBDEVv2_EP7_INTR__SIZE 0x00000001u
#define CYFLD_USBDEVv2_EP8_INTR__OFFSET 0x00000007u
#define CYFLD_USBDEVv2_EP8_INTR__SIZE 0x00000001u
#define CYREG_USBDEVv2_SIE_EP1_CNT0 0x400c0030u
#define CYFLD_USBDEVv2_DATA_COUNT_MSB__OFFSET 0x00000000u
#define CYFLD_USBDEVv2_DATA_COUNT_MSB__SIZE 0x00000003u
#define CYFLD_USBDEVv2_DATA_VALID__OFFSET 0x00000006u
#define CYFLD_USBDEVv2_DATA_VALID__SIZE 0x00000001u
#define CYVAL_USBDEVv2_DATA_VALID_DATA_ERROR 0x00000000u
#define CYVAL_USBDEVv2_DATA_VALID_DATA_VALID 0x00000001u
#define CYFLD_USBDEVv2_DATA_TOGGLE__OFFSET 0x00000007u
#define CYFLD_USBDEVv2_DATA_TOGGLE__SIZE 0x00000001u
#define CYREG_USBDEVv2_SIE_EP1_CNT1 0x400c0034u
#define CYFLD_USBDEVv2_DATA_COUNT__OFFSET 0x00000000u
#define CYFLD_USBDEVv2_DATA_COUNT__SIZE 0x00000008u
#define CYREG_USBDEVv2_SIE_EP1_CR0 0x400c0038u
#define CYFLD_USBDEVv2_MODE__OFFSET 0x00000000u
#define CYFLD_USBDEVv2_MODE__SIZE 0x00000004u
#define CYVAL_USBDEVv2_MODE_DISABLE 0x00000000u
#define CYVAL_USBDEVv2_MODE_NAK_INOUT 0x00000001u
#define CYVAL_USBDEVv2_MODE_STATUS_OUT_ONLY 0x00000002u
#define CYVAL_USBDEVv2_MODE_STALL_INOUT 0x00000003u
#define CYVAL_USBDEVv2_MODE_ISO_OUT 0x00000005u
#define CYVAL_USBDEVv2_MODE_STATUS_IN_ONLY 0x00000006u
#define CYVAL_USBDEVv2_MODE_ISO_IN 0x00000007u
#define CYVAL_USBDEVv2_MODE_NAK_OUT 0x00000008u
#define CYVAL_USBDEVv2_MODE_ACK_OUT 0x00000009u
#define CYVAL_USBDEVv2_MODE_ACK_OUT_STATUS_IN 0x0000000bu
#define CYVAL_USBDEVv2_MODE_NAK_IN 0x0000000cu
#define CYVAL_USBDEVv2_MODE_ACK_IN 0x0000000du
#define CYVAL_USBDEVv2_MODE_ACK_IN_STATUS_OUT 0x0000000fu
#define CYFLD_USBDEVv2_ACKED_TXN__OFFSET 0x00000004u
#define CYFLD_USBDEVv2_ACKED_TXN__SIZE 0x00000001u
#define CYVAL_USBDEVv2_ACKED_TXN_ACKED_NO 0x00000000u
#define CYVAL_USBDEVv2_ACKED_TXN_ACKED_YES 0x00000001u
#define CYFLD_USBDEVv2_NAK_INT_EN__OFFSET 0x00000005u
#define CYFLD_USBDEVv2_NAK_INT_EN__SIZE 0x00000001u
#define CYFLD_USBDEVv2_ERR_IN_TXN__OFFSET 0x00000006u
#define CYFLD_USBDEVv2_ERR_IN_TXN__SIZE 0x00000001u
#define CYFLD_USBDEVv2_STALL__OFFSET 0x00000007u
#define CYFLD_USBDEVv2_STALL__SIZE 0x00000001u
#define CYREG_USBDEVv2_USBIO_CR0 0x400c0040u
#define CYFLD_USBDEVv2_RD__OFFSET 0x00000000u
#define CYFLD_USBDEVv2_RD__SIZE 0x00000001u
#define CYVAL_USBDEVv2_RD_DIFF_LOW 0x00000000u
#define CYVAL_USBDEVv2_RD_DIFF_HIGH 0x00000001u
#define CYFLD_USBDEVv2_TD__OFFSET 0x00000005u
#define CYFLD_USBDEVv2_TD__SIZE 0x00000001u
#define CYVAL_USBDEVv2_TD_DIFF_K 0x00000000u
#define CYVAL_USBDEVv2_TD_DIFF_J 0x00000001u
#define CYFLD_USBDEVv2_TSE0__OFFSET 0x00000006u
#define CYFLD_USBDEVv2_TSE0__SIZE 0x00000001u
#define CYFLD_USBDEVv2_TEN__OFFSET 0x00000007u
#define CYFLD_USBDEVv2_TEN__SIZE 0x00000001u
#define CYREG_USBDEVv2_USBIO_CR2 0x400c0044u
#define CYFLD_USBDEVv2_Reserved__OFFSET 0x00000000u
#define CYFLD_USBDEVv2_Reserved__SIZE 0x00000006u
#define CYFLD_USBDEVv2_TEST_PKT__OFFSET 0x00000006u
#define CYFLD_USBDEVv2_TEST_PKT__SIZE 0x00000001u
#define CYFLD_USBDEVv2_TEST_RES__OFFSET 0x00000007u
#define CYFLD_USBDEVv2_TEST_RES__SIZE 0x00000001u
#define CYREG_USBDEVv2_USBIO_CR1 0x400c0048u
#define CYFLD_USBDEVv2_DMO__OFFSET 0x00000000u
#define CYFLD_USBDEVv2_DMO__SIZE 0x00000001u
#define CYFLD_USBDEVv2_DPO__OFFSET 0x00000001u
#define CYFLD_USBDEVv2_DPO__SIZE 0x00000001u
#define CYFLD_USBDEVv2_USBPUEN__OFFSET 0x00000002u
#define CYFLD_USBDEVv2_USBPUEN__SIZE 0x00000001u
#define CYFLD_USBDEVv2_IOMODE__OFFSET 0x00000005u
#define CYFLD_USBDEVv2_IOMODE__SIZE 0x00000001u
#define CYREG_USBDEVv2_DYN_RECONFIG 0x400c0050u
#define CYFLD_USBDEVv2_DYN_CONFIG_EN__OFFSET 0x00000000u
#define CYFLD_USBDEVv2_DYN_CONFIG_EN__SIZE 0x00000001u
#define CYFLD_USBDEVv2_DYN_RECONFIG_EPNO__OFFSET 0x00000001u
#define CYFLD_USBDEVv2_DYN_RECONFIG_EPNO__SIZE 0x00000003u
#define CYFLD_USBDEVv2_DYN_RECONFIG_RDY_STS__OFFSET 0x00000004u
#define CYFLD_USBDEVv2_DYN_RECONFIG_RDY_STS__SIZE 0x00000001u
#define CYREG_USBDEVv2_SOF0 0x400c0060u
#define CYFLD_USBDEVv2_FRAME_NUMBER__OFFSET 0x00000000u
#define CYFLD_USBDEVv2_FRAME_NUMBER__SIZE 0x00000008u
#define CYREG_USBDEVv2_SOF1 0x400c0064u
#define CYFLD_USBDEVv2_FRAME_NUMBER_MSB__OFFSET 0x00000000u
#define CYFLD_USBDEVv2_FRAME_NUMBER_MSB__SIZE 0x00000003u
#define CYREG_USBDEVv2_SIE_EP2_CNT0 0x400c0070u
#define CYREG_USBDEVv2_SIE_EP2_CNT1 0x400c0074u
#define CYREG_USBDEVv2_SIE_EP2_CR0 0x400c0078u
#define CYREG_USBDEVv2_OSCLK_DR0 0x400c0080u
#define CYFLD_USBDEVv2_ADDER__OFFSET 0x00000000u
#define CYFLD_USBDEVv2_ADDER__SIZE 0x00000008u
#define CYREG_USBDEVv2_OSCLK_DR1 0x400c0084u
#define CYFLD_USBDEVv2_ADDER_MSB__OFFSET 0x00000000u
#define CYFLD_USBDEVv2_ADDER_MSB__SIZE 0x00000007u
#define CYREG_USBDEVv2_EP0_CR 0x400c00a0u
#define CYFLD_USBDEVv2_OUT_RCVD__OFFSET 0x00000005u
#define CYFLD_USBDEVv2_OUT_RCVD__SIZE 0x00000001u
#define CYFLD_USBDEVv2_IN_RCVD__OFFSET 0x00000006u
#define CYFLD_USBDEVv2_IN_RCVD__SIZE 0x00000001u
#define CYFLD_USBDEVv2_SETUP_RCVD__OFFSET 0x00000007u
#define CYFLD_USBDEVv2_SETUP_RCVD__SIZE 0x00000001u
#define CYREG_USBDEVv2_EP0_CNT 0x400c00a4u
#define CYFLD_USBDEVv2_BYTE_COUNT__OFFSET 0x00000000u
#define CYFLD_USBDEVv2_BYTE_COUNT__SIZE 0x00000004u
#define CYREG_USBDEVv2_SIE_EP3_CNT0 0x400c00b0u
#define CYREG_USBDEVv2_SIE_EP3_CNT1 0x400c00b4u
#define CYREG_USBDEVv2_SIE_EP3_CR0 0x400c00b8u
#define CYREG_USBDEVv2_SIE_EP4_CNT0 0x400c00f0u
#define CYREG_USBDEVv2_SIE_EP4_CNT1 0x400c00f4u
#define CYREG_USBDEVv2_SIE_EP4_CR0 0x400c00f8u
#define CYREG_USBDEVv2_SIE_EP5_CNT0 0x400c0130u
#define CYREG_USBDEVv2_SIE_EP5_CNT1 0x400c0134u
#define CYREG_USBDEVv2_SIE_EP5_CR0 0x400c0138u
#define CYREG_USBDEVv2_SIE_EP6_CNT0 0x400c0170u
#define CYREG_USBDEVv2_SIE_EP6_CNT1 0x400c0174u
#define CYREG_USBDEVv2_SIE_EP6_CR0 0x400c0178u
#define CYREG_USBDEVv2_SIE_EP7_CNT0 0x400c01b0u
#define CYREG_USBDEVv2_SIE_EP7_CNT1 0x400c01b4u
#define CYREG_USBDEVv2_SIE_EP7_CR0 0x400c01b8u
#define CYREG_USBDEVv2_SIE_EP8_CNT0 0x400c01f0u
#define CYREG_USBDEVv2_SIE_EP8_CNT1 0x400c01f4u
#define CYREG_USBDEVv2_SIE_EP8_CR0 0x400c01f8u
#define CYREG_USBDEVv2_ARB_EP1_CFG 0x400c0200u
#define CYFLD_USBDEVv2_IN_DATA_RDY__OFFSET 0x00000000u
#define CYFLD_USBDEVv2_IN_DATA_RDY__SIZE 0x00000001u
#define CYFLD_USBDEVv2_DMA_REQ__OFFSET 0x00000001u
#define CYFLD_USBDEVv2_DMA_REQ__SIZE 0x00000001u
#define CYFLD_USBDEVv2_CRC_BYPASS__OFFSET 0x00000002u
#define CYFLD_USBDEVv2_CRC_BYPASS__SIZE 0x00000001u
#define CYVAL_USBDEVv2_CRC_BYPASS_CRC_NORMAL 0x00000000u
#define CYVAL_USBDEVv2_CRC_BYPASS_CRC_BYPASS 0x00000001u
#define CYFLD_USBDEVv2_RESET_PTR__OFFSET 0x00000003u
#define CYFLD_USBDEVv2_RESET_PTR__SIZE 0x00000001u
#define CYVAL_USBDEVv2_RESET_PTR_RESET_KRYPTON 0x00000000u
#define CYVAL_USBDEVv2_RESET_PTR_RESET_NORMAL 0x00000001u
#define CYREG_USBDEVv2_ARB_EP1_INT_EN 0x400c0204u
#define CYFLD_USBDEVv2_IN_BUF_FULL_EN__OFFSET 0x00000000u
#define CYFLD_USBDEVv2_IN_BUF_FULL_EN__SIZE 0x00000001u
#define CYFLD_USBDEVv2_DMA_GNT_EN__OFFSET 0x00000001u
#define CYFLD_USBDEVv2_DMA_GNT_EN__SIZE 0x00000001u
#define CYFLD_USBDEVv2_BUF_OVER_EN__OFFSET 0x00000002u
#define CYFLD_USBDEVv2_BUF_OVER_EN__SIZE 0x00000001u
#define CYFLD_USBDEVv2_BUF_UNDER_EN__OFFSET 0x00000003u
#define CYFLD_USBDEVv2_BUF_UNDER_EN__SIZE 0x00000001u
#define CYFLD_USBDEVv2_ERR_INT_EN__OFFSET 0x00000004u
#define CYFLD_USBDEVv2_ERR_INT_EN__SIZE 0x00000001u
#define CYFLD_USBDEVv2_DMA_TERMIN_EN__OFFSET 0x00000005u
#define CYFLD_USBDEVv2_DMA_TERMIN_EN__SIZE 0x00000001u
#define CYREG_USBDEVv2_ARB_EP1_SR 0x400c0208u
#define CYFLD_USBDEVv2_IN_BUF_FULL__OFFSET 0x00000000u
#define CYFLD_USBDEVv2_IN_BUF_FULL__SIZE 0x00000001u
#define CYFLD_USBDEVv2_DMA_GNT__OFFSET 0x00000001u
#define CYFLD_USBDEVv2_DMA_GNT__SIZE 0x00000001u
#define CYFLD_USBDEVv2_BUF_OVER__OFFSET 0x00000002u
#define CYFLD_USBDEVv2_BUF_OVER__SIZE 0x00000001u
#define CYFLD_USBDEVv2_BUF_UNDER__OFFSET 0x00000003u
#define CYFLD_USBDEVv2_BUF_UNDER__SIZE 0x00000001u
#define CYFLD_USBDEVv2_DMA_TERMIN__OFFSET 0x00000005u
#define CYFLD_USBDEVv2_DMA_TERMIN__SIZE 0x00000001u
#define CYREG_USBDEVv2_ARB_RW1_WA 0x400c0210u
#define CYFLD_USBDEVv2_WA__OFFSET 0x00000000u
#define CYFLD_USBDEVv2_WA__SIZE 0x00000008u
#define CYREG_USBDEVv2_ARB_RW1_WA_MSB 0x400c0214u
#define CYFLD_USBDEVv2_WA_MSB__OFFSET 0x00000000u
#define CYFLD_USBDEVv2_WA_MSB__SIZE 0x00000001u
#define CYREG_USBDEVv2_ARB_RW1_RA 0x400c0218u
#define CYFLD_USBDEVv2_RA__OFFSET 0x00000000u
#define CYFLD_USBDEVv2_RA__SIZE 0x00000008u
#define CYREG_USBDEVv2_ARB_RW1_RA_MSB 0x400c021cu
#define CYFLD_USBDEVv2_RA_MSB__OFFSET 0x00000000u
#define CYFLD_USBDEVv2_RA_MSB__SIZE 0x00000001u
#define CYREG_USBDEVv2_ARB_RW1_DR 0x400c0220u
#define CYFLD_USBDEVv2_DR__OFFSET 0x00000000u
#define CYFLD_USBDEVv2_DR__SIZE 0x00000008u
#define CYREG_USBDEVv2_BUF_SIZE 0x400c0230u
#define CYFLD_USBDEVv2_IN_BUF__OFFSET 0x00000000u
#define CYFLD_USBDEVv2_IN_BUF__SIZE 0x00000004u
#define CYFLD_USBDEVv2_OUT_BUF__OFFSET 0x00000004u
#define CYFLD_USBDEVv2_OUT_BUF__SIZE 0x00000004u
#define CYREG_USBDEVv2_EP_ACTIVE 0x400c0238u
#define CYFLD_USBDEVv2_EP1_ACT__OFFSET 0x00000000u
#define CYFLD_USBDEVv2_EP1_ACT__SIZE 0x00000001u
#define CYFLD_USBDEVv2_EP2_ACT__OFFSET 0x00000001u
#define CYFLD_USBDEVv2_EP2_ACT__SIZE 0x00000001u
#define CYFLD_USBDEVv2_EP3_ACT__OFFSET 0x00000002u
#define CYFLD_USBDEVv2_EP3_ACT__SIZE 0x00000001u
#define CYFLD_USBDEVv2_EP4_ACT__OFFSET 0x00000003u
#define CYFLD_USBDEVv2_EP4_ACT__SIZE 0x00000001u
#define CYFLD_USBDEVv2_EP5_ACT__OFFSET 0x00000004u
#define CYFLD_USBDEVv2_EP5_ACT__SIZE 0x00000001u
#define CYFLD_USBDEVv2_EP6_ACT__OFFSET 0x00000005u
#define CYFLD_USBDEVv2_EP6_ACT__SIZE 0x00000001u
#define CYFLD_USBDEVv2_EP7_ACT__OFFSET 0x00000006u
#define CYFLD_USBDEVv2_EP7_ACT__SIZE 0x00000001u
#define CYFLD_USBDEVv2_EP8_ACT__OFFSET 0x00000007u
#define CYFLD_USBDEVv2_EP8_ACT__SIZE 0x00000001u
#define CYREG_USBDEVv2_EP_TYPE 0x400c023cu
#define CYFLD_USBDEVv2_EP1_TYP__OFFSET 0x00000000u
#define CYFLD_USBDEVv2_EP1_TYP__SIZE 0x00000001u
#define CYVAL_USBDEVv2_EP1_TYP_EP_IN 0x00000000u
#define CYVAL_USBDEVv2_EP1_TYP_EP_OUT 0x00000001u
#define CYFLD_USBDEVv2_EP2_TYP__OFFSET 0x00000001u
#define CYFLD_USBDEVv2_EP2_TYP__SIZE 0x00000001u
#define CYVAL_USBDEVv2_EP2_TYP_EP_IN 0x00000000u
#define CYVAL_USBDEVv2_EP2_TYP_EP_OUT 0x00000001u
#define CYFLD_USBDEVv2_EP3_TYP__OFFSET 0x00000002u
#define CYFLD_USBDEVv2_EP3_TYP__SIZE 0x00000001u
#define CYVAL_USBDEVv2_EP3_TYP_EP_IN 0x00000000u
#define CYVAL_USBDEVv2_EP3_TYP_EP_OUT 0x00000001u
#define CYFLD_USBDEVv2_EP4_TYP__OFFSET 0x00000003u
#define CYFLD_USBDEVv2_EP4_TYP__SIZE 0x00000001u
#define CYVAL_USBDEVv2_EP4_TYP_EP_IN 0x00000000u
#define CYVAL_USBDEVv2_EP4_TYP_EP_OUT 0x00000001u
#define CYFLD_USBDEVv2_EP5_TYP__OFFSET 0x00000004u
#define CYFLD_USBDEVv2_EP5_TYP__SIZE 0x00000001u
#define CYVAL_USBDEVv2_EP5_TYP_EP_IN 0x00000000u
#define CYVAL_USBDEVv2_EP5_TYP_EP_OUT 0x00000001u
#define CYFLD_USBDEVv2_EP6_TYP__OFFSET 0x00000005u
#define CYFLD_USBDEVv2_EP6_TYP__SIZE 0x00000001u
#define CYVAL_USBDEVv2_EP6_TYP_EP_IN 0x00000000u
#define CYVAL_USBDEVv2_EP6_TYP_EP_OUT 0x00000001u
#define CYFLD_USBDEVv2_EP7_TYP__OFFSET 0x00000006u
#define CYFLD_USBDEVv2_EP7_TYP__SIZE 0x00000001u
#define CYVAL_USBDEVv2_EP7_TYP_EP_IN 0x00000000u
#define CYVAL_USBDEVv2_EP7_TYP_EP_OUT 0x00000001u
#define CYFLD_USBDEVv2_EP8_TYP__OFFSET 0x00000007u
#define CYFLD_USBDEVv2_EP8_TYP__SIZE 0x00000001u
#define CYVAL_USBDEVv2_EP8_TYP_EP_IN 0x00000000u
#define CYVAL_USBDEVv2_EP8_TYP_EP_OUT 0x00000001u
#define CYREG_USBDEVv2_ARB_EP2_CFG 0x400c0240u
#define CYREG_USBDEVv2_ARB_EP2_INT_EN 0x400c0244u
#define CYREG_USBDEVv2_ARB_EP2_SR 0x400c0248u
#define CYREG_USBDEVv2_ARB_RW2_WA 0x400c0250u
#define CYREG_USBDEVv2_ARB_RW2_WA_MSB 0x400c0254u
#define CYREG_USBDEVv2_ARB_RW2_RA 0x400c0258u
#define CYREG_USBDEVv2_ARB_RW2_RA_MSB 0x400c025cu
#define CYREG_USBDEVv2_ARB_RW2_DR 0x400c0260u
#define CYREG_USBDEVv2_ARB_CFG 0x400c0270u
#define CYFLD_USBDEVv2_AUTO_MEM__OFFSET 0x00000004u
#define CYFLD_USBDEVv2_AUTO_MEM__SIZE 0x00000001u
#define CYFLD_USBDEVv2_DMA_CFG__OFFSET 0x00000005u
#define CYFLD_USBDEVv2_DMA_CFG__SIZE 0x00000002u
#define CYVAL_USBDEVv2_DMA_CFG_DMA_NONE 0x00000000u
#define CYVAL_USBDEVv2_DMA_CFG_DMA_MANUAL 0x00000001u
#define CYVAL_USBDEVv2_DMA_CFG_DMA_AUTO 0x00000002u
#define CYFLD_USBDEVv2_CFG_CMP__OFFSET 0x00000007u
#define CYFLD_USBDEVv2_CFG_CMP__SIZE 0x00000001u
#define CYREG_USBDEVv2_USB_CLK_EN 0x400c0274u
#define CYFLD_USBDEVv2_CSR_CLK_EN__OFFSET 0x00000000u
#define CYFLD_USBDEVv2_CSR_CLK_EN__SIZE 0x00000001u
#define CYREG_USBDEVv2_ARB_INT_EN 0x400c0278u
#define CYREG_USBDEVv2_ARB_INT_SR 0x400c027cu
#define CYREG_USBDEVv2_ARB_EP3_CFG 0x400c0280u
#define CYREG_USBDEVv2_ARB_EP3_INT_EN 0x400c0284u
#define CYREG_USBDEVv2_ARB_EP3_SR 0x400c0288u
#define CYREG_USBDEVv2_ARB_RW3_WA 0x400c0290u
#define CYREG_USBDEVv2_ARB_RW3_WA_MSB 0x400c0294u
#define CYREG_USBDEVv2_ARB_RW3_RA 0x400c0298u
#define CYREG_USBDEVv2_ARB_RW3_RA_MSB 0x400c029cu
#define CYREG_USBDEVv2_ARB_RW3_DR 0x400c02a0u
#define CYREG_USBDEVv2_CWA 0x400c02b0u
#define CYFLD_USBDEVv2_CWA__OFFSET 0x00000000u
#define CYFLD_USBDEVv2_CWA__SIZE 0x00000008u
#define CYREG_USBDEVv2_CWA_MSB 0x400c02b4u
#define CYFLD_USBDEVv2_CWA_MSB__OFFSET 0x00000000u
#define CYFLD_USBDEVv2_CWA_MSB__SIZE 0x00000001u
#define CYREG_USBDEVv2_ARB_EP4_CFG 0x400c02c0u
#define CYREG_USBDEVv2_ARB_EP4_INT_EN 0x400c02c4u
#define CYREG_USBDEVv2_ARB_EP4_SR 0x400c02c8u
#define CYREG_USBDEVv2_ARB_RW4_WA 0x400c02d0u
#define CYREG_USBDEVv2_ARB_RW4_WA_MSB 0x400c02d4u
#define CYREG_USBDEVv2_ARB_RW4_RA 0x400c02d8u
#define CYREG_USBDEVv2_ARB_RW4_RA_MSB 0x400c02dcu
#define CYREG_USBDEVv2_ARB_RW4_DR 0x400c02e0u
#define CYREG_USBDEVv2_DMA_THRES 0x400c02f0u
#define CYFLD_USBDEVv2_DMA_THS__OFFSET 0x00000000u
#define CYFLD_USBDEVv2_DMA_THS__SIZE 0x00000008u
#define CYREG_USBDEVv2_DMA_THRES_MSB 0x400c02f4u
#define CYFLD_USBDEVv2_DMA_THS_MSB__OFFSET 0x00000000u
#define CYFLD_USBDEVv2_DMA_THS_MSB__SIZE 0x00000001u
#define CYREG_USBDEVv2_ARB_EP5_CFG 0x400c0300u
#define CYREG_USBDEVv2_ARB_EP5_INT_EN 0x400c0304u
#define CYREG_USBDEVv2_ARB_EP5_SR 0x400c0308u
#define CYREG_USBDEVv2_ARB_RW5_WA 0x400c0310u
#define CYREG_USBDEVv2_ARB_RW5_WA_MSB 0x400c0314u
#define CYREG_USBDEVv2_ARB_RW5_RA 0x400c0318u
#define CYREG_USBDEVv2_ARB_RW5_RA_MSB 0x400c031cu
#define CYREG_USBDEVv2_ARB_RW5_DR 0x400c0320u
#define CYREG_USBDEVv2_BUS_RST_CNT 0x400c0330u
#define CYFLD_USBDEVv2_bus_rst_cnt__OFFSET 0x00000000u
#define CYFLD_USBDEVv2_bus_rst_cnt__SIZE 0x00000004u
#define CYREG_USBDEVv2_ARB_EP6_CFG 0x400c0340u
#define CYREG_USBDEVv2_ARB_EP6_INT_EN 0x400c0344u
#define CYREG_USBDEVv2_ARB_EP6_SR 0x400c0348u
#define CYREG_USBDEVv2_ARB_RW6_WA 0x400c0350u
#define CYREG_USBDEVv2_ARB_RW6_WA_MSB 0x400c0354u
#define CYREG_USBDEVv2_ARB_RW6_RA 0x400c0358u
#define CYREG_USBDEVv2_ARB_RW6_RA_MSB 0x400c035cu
#define CYREG_USBDEVv2_ARB_RW6_DR 0x400c0360u
#define CYREG_USBDEVv2_ARB_EP7_CFG 0x400c0380u
#define CYREG_USBDEVv2_ARB_EP7_INT_EN 0x400c0384u
#define CYREG_USBDEVv2_ARB_EP7_SR 0x400c0388u
#define CYREG_USBDEVv2_ARB_RW7_WA 0x400c0390u
#define CYREG_USBDEVv2_ARB_RW7_WA_MSB 0x400c0394u
#define CYREG_USBDEVv2_ARB_RW7_RA 0x400c0398u
#define CYREG_USBDEVv2_ARB_RW7_RA_MSB 0x400c039cu
#define CYREG_USBDEVv2_ARB_RW7_DR 0x400c03a0u
#define CYREG_USBDEVv2_ARB_EP8_CFG 0x400c03c0u
#define CYREG_USBDEVv2_ARB_EP8_INT_EN 0x400c03c4u
#define CYREG_USBDEVv2_ARB_EP8_SR 0x400c03c8u
#define CYREG_USBDEVv2_ARB_RW8_WA 0x400c03d0u
#define CYREG_USBDEVv2_ARB_RW8_WA_MSB 0x400c03d4u
#define CYREG_USBDEVv2_ARB_RW8_RA 0x400c03d8u
#define CYREG_USBDEVv2_ARB_RW8_RA_MSB 0x400c03dcu
#define CYREG_USBDEVv2_ARB_RW8_DR 0x400c03e0u
#define CYREG_USBDEVv2_MEM_DATA0 0x400c0400u
#define CYREG_USBDEVv2_MEM_DATA1 0x400c0404u
#define CYREG_USBDEVv2_MEM_DATA2 0x400c0408u
#define CYREG_USBDEVv2_MEM_DATA3 0x400c040cu
#define CYREG_USBDEVv2_MEM_DATA4 0x400c0410u
#define CYREG_USBDEVv2_MEM_DATA5 0x400c0414u
#define CYREG_USBDEVv2_MEM_DATA6 0x400c0418u
#define CYREG_USBDEVv2_MEM_DATA7 0x400c041cu
#define CYREG_USBDEVv2_MEM_DATA8 0x400c0420u
#define CYREG_USBDEVv2_MEM_DATA9 0x400c0424u
#define CYREG_USBDEVv2_MEM_DATA10 0x400c0428u
#define CYREG_USBDEVv2_MEM_DATA11 0x400c042cu
#define CYREG_USBDEVv2_MEM_DATA12 0x400c0430u
#define CYREG_USBDEVv2_MEM_DATA13 0x400c0434u
#define CYREG_USBDEVv2_MEM_DATA14 0x400c0438u
#define CYREG_USBDEVv2_MEM_DATA15 0x400c043cu
#define CYREG_USBDEVv2_MEM_DATA16 0x400c0440u
#define CYREG_USBDEVv2_MEM_DATA17 0x400c0444u
#define CYREG_USBDEVv2_MEM_DATA18 0x400c0448u
#define CYREG_USBDEVv2_MEM_DATA19 0x400c044cu
#define CYREG_USBDEVv2_MEM_DATA20 0x400c0450u
#define CYREG_USBDEVv2_MEM_DATA21 0x400c0454u
#define CYREG_USBDEVv2_MEM_DATA22 0x400c0458u
#define CYREG_USBDEVv2_MEM_DATA23 0x400c045cu
#define CYREG_USBDEVv2_MEM_DATA24 0x400c0460u
#define CYREG_USBDEVv2_MEM_DATA25 0x400c0464u
#define CYREG_USBDEVv2_MEM_DATA26 0x400c0468u
#define CYREG_USBDEVv2_MEM_DATA27 0x400c046cu
#define CYREG_USBDEVv2_MEM_DATA28 0x400c0470u
#define CYREG_USBDEVv2_MEM_DATA29 0x400c0474u
#define CYREG_USBDEVv2_MEM_DATA30 0x400c0478u
#define CYREG_USBDEVv2_MEM_DATA31 0x400c047cu
#define CYREG_USBDEVv2_MEM_DATA32 0x400c0480u
#define CYREG_USBDEVv2_MEM_DATA33 0x400c0484u
#define CYREG_USBDEVv2_MEM_DATA34 0x400c0488u
#define CYREG_USBDEVv2_MEM_DATA35 0x400c048cu
#define CYREG_USBDEVv2_MEM_DATA36 0x400c0490u
#define CYREG_USBDEVv2_MEM_DATA37 0x400c0494u
#define CYREG_USBDEVv2_MEM_DATA38 0x400c0498u
#define CYREG_USBDEVv2_MEM_DATA39 0x400c049cu
#define CYREG_USBDEVv2_MEM_DATA40 0x400c04a0u
#define CYREG_USBDEVv2_MEM_DATA41 0x400c04a4u
#define CYREG_USBDEVv2_MEM_DATA42 0x400c04a8u
#define CYREG_USBDEVv2_MEM_DATA43 0x400c04acu
#define CYREG_USBDEVv2_MEM_DATA44 0x400c04b0u
#define CYREG_USBDEVv2_MEM_DATA45 0x400c04b4u
#define CYREG_USBDEVv2_MEM_DATA46 0x400c04b8u
#define CYREG_USBDEVv2_MEM_DATA47 0x400c04bcu
#define CYREG_USBDEVv2_MEM_DATA48 0x400c04c0u
#define CYREG_USBDEVv2_MEM_DATA49 0x400c04c4u
#define CYREG_USBDEVv2_MEM_DATA50 0x400c04c8u
#define CYREG_USBDEVv2_MEM_DATA51 0x400c04ccu
#define CYREG_USBDEVv2_MEM_DATA52 0x400c04d0u
#define CYREG_USBDEVv2_MEM_DATA53 0x400c04d4u
#define CYREG_USBDEVv2_MEM_DATA54 0x400c04d8u
#define CYREG_USBDEVv2_MEM_DATA55 0x400c04dcu
#define CYREG_USBDEVv2_MEM_DATA56 0x400c04e0u
#define CYREG_USBDEVv2_MEM_DATA57 0x400c04e4u
#define CYREG_USBDEVv2_MEM_DATA58 0x400c04e8u
#define CYREG_USBDEVv2_MEM_DATA59 0x400c04ecu
#define CYREG_USBDEVv2_MEM_DATA60 0x400c04f0u
#define CYREG_USBDEVv2_MEM_DATA61 0x400c04f4u
#define CYREG_USBDEVv2_MEM_DATA62 0x400c04f8u
#define CYREG_USBDEVv2_MEM_DATA63 0x400c04fcu
#define CYREG_USBDEVv2_MEM_DATA64 0x400c0500u
#define CYREG_USBDEVv2_MEM_DATA65 0x400c0504u
#define CYREG_USBDEVv2_MEM_DATA66 0x400c0508u
#define CYREG_USBDEVv2_MEM_DATA67 0x400c050cu
#define CYREG_USBDEVv2_MEM_DATA68 0x400c0510u
#define CYREG_USBDEVv2_MEM_DATA69 0x400c0514u
#define CYREG_USBDEVv2_MEM_DATA70 0x400c0518u
#define CYREG_USBDEVv2_MEM_DATA71 0x400c051cu
#define CYREG_USBDEVv2_MEM_DATA72 0x400c0520u
#define CYREG_USBDEVv2_MEM_DATA73 0x400c0524u
#define CYREG_USBDEVv2_MEM_DATA74 0x400c0528u
#define CYREG_USBDEVv2_MEM_DATA75 0x400c052cu
#define CYREG_USBDEVv2_MEM_DATA76 0x400c0530u
#define CYREG_USBDEVv2_MEM_DATA77 0x400c0534u
#define CYREG_USBDEVv2_MEM_DATA78 0x400c0538u
#define CYREG_USBDEVv2_MEM_DATA79 0x400c053cu
#define CYREG_USBDEVv2_MEM_DATA80 0x400c0540u
#define CYREG_USBDEVv2_MEM_DATA81 0x400c0544u
#define CYREG_USBDEVv2_MEM_DATA82 0x400c0548u
#define CYREG_USBDEVv2_MEM_DATA83 0x400c054cu
#define CYREG_USBDEVv2_MEM_DATA84 0x400c0550u
#define CYREG_USBDEVv2_MEM_DATA85 0x400c0554u
#define CYREG_USBDEVv2_MEM_DATA86 0x400c0558u
#define CYREG_USBDEVv2_MEM_DATA87 0x400c055cu
#define CYREG_USBDEVv2_MEM_DATA88 0x400c0560u
#define CYREG_USBDEVv2_MEM_DATA89 0x400c0564u
#define CYREG_USBDEVv2_MEM_DATA90 0x400c0568u
#define CYREG_USBDEVv2_MEM_DATA91 0x400c056cu
#define CYREG_USBDEVv2_MEM_DATA92 0x400c0570u
#define CYREG_USBDEVv2_MEM_DATA93 0x400c0574u
#define CYREG_USBDEVv2_MEM_DATA94 0x400c0578u
#define CYREG_USBDEVv2_MEM_DATA95 0x400c057cu
#define CYREG_USBDEVv2_MEM_DATA96 0x400c0580u
#define CYREG_USBDEVv2_MEM_DATA97 0x400c0584u
#define CYREG_USBDEVv2_MEM_DATA98 0x400c0588u
#define CYREG_USBDEVv2_MEM_DATA99 0x400c058cu
#define CYREG_USBDEVv2_MEM_DATA100 0x400c0590u
#define CYREG_USBDEVv2_MEM_DATA101 0x400c0594u
#define CYREG_USBDEVv2_MEM_DATA102 0x400c0598u
#define CYREG_USBDEVv2_MEM_DATA103 0x400c059cu
#define CYREG_USBDEVv2_MEM_DATA104 0x400c05a0u
#define CYREG_USBDEVv2_MEM_DATA105 0x400c05a4u
#define CYREG_USBDEVv2_MEM_DATA106 0x400c05a8u
#define CYREG_USBDEVv2_MEM_DATA107 0x400c05acu
#define CYREG_USBDEVv2_MEM_DATA108 0x400c05b0u
#define CYREG_USBDEVv2_MEM_DATA109 0x400c05b4u
#define CYREG_USBDEVv2_MEM_DATA110 0x400c05b8u
#define CYREG_USBDEVv2_MEM_DATA111 0x400c05bcu
#define CYREG_USBDEVv2_MEM_DATA112 0x400c05c0u
#define CYREG_USBDEVv2_MEM_DATA113 0x400c05c4u
#define CYREG_USBDEVv2_MEM_DATA114 0x400c05c8u
#define CYREG_USBDEVv2_MEM_DATA115 0x400c05ccu
#define CYREG_USBDEVv2_MEM_DATA116 0x400c05d0u
#define CYREG_USBDEVv2_MEM_DATA117 0x400c05d4u
#define CYREG_USBDEVv2_MEM_DATA118 0x400c05d8u
#define CYREG_USBDEVv2_MEM_DATA119 0x400c05dcu
#define CYREG_USBDEVv2_MEM_DATA120 0x400c05e0u
#define CYREG_USBDEVv2_MEM_DATA121 0x400c05e4u
#define CYREG_USBDEVv2_MEM_DATA122 0x400c05e8u
#define CYREG_USBDEVv2_MEM_DATA123 0x400c05ecu
#define CYREG_USBDEVv2_MEM_DATA124 0x400c05f0u
#define CYREG_USBDEVv2_MEM_DATA125 0x400c05f4u
#define CYREG_USBDEVv2_MEM_DATA126 0x400c05f8u
#define CYREG_USBDEVv2_MEM_DATA127 0x400c05fcu
#define CYREG_USBDEVv2_MEM_DATA128 0x400c0600u
#define CYREG_USBDEVv2_MEM_DATA129 0x400c0604u
#define CYREG_USBDEVv2_MEM_DATA130 0x400c0608u
#define CYREG_USBDEVv2_MEM_DATA131 0x400c060cu
#define CYREG_USBDEVv2_MEM_DATA132 0x400c0610u
#define CYREG_USBDEVv2_MEM_DATA133 0x400c0614u
#define CYREG_USBDEVv2_MEM_DATA134 0x400c0618u
#define CYREG_USBDEVv2_MEM_DATA135 0x400c061cu
#define CYREG_USBDEVv2_MEM_DATA136 0x400c0620u
#define CYREG_USBDEVv2_MEM_DATA137 0x400c0624u
#define CYREG_USBDEVv2_MEM_DATA138 0x400c0628u
#define CYREG_USBDEVv2_MEM_DATA139 0x400c062cu
#define CYREG_USBDEVv2_MEM_DATA140 0x400c0630u
#define CYREG_USBDEVv2_MEM_DATA141 0x400c0634u
#define CYREG_USBDEVv2_MEM_DATA142 0x400c0638u
#define CYREG_USBDEVv2_MEM_DATA143 0x400c063cu
#define CYREG_USBDEVv2_MEM_DATA144 0x400c0640u
#define CYREG_USBDEVv2_MEM_DATA145 0x400c0644u
#define CYREG_USBDEVv2_MEM_DATA146 0x400c0648u
#define CYREG_USBDEVv2_MEM_DATA147 0x400c064cu
#define CYREG_USBDEVv2_MEM_DATA148 0x400c0650u
#define CYREG_USBDEVv2_MEM_DATA149 0x400c0654u
#define CYREG_USBDEVv2_MEM_DATA150 0x400c0658u
#define CYREG_USBDEVv2_MEM_DATA151 0x400c065cu
#define CYREG_USBDEVv2_MEM_DATA152 0x400c0660u
#define CYREG_USBDEVv2_MEM_DATA153 0x400c0664u
#define CYREG_USBDEVv2_MEM_DATA154 0x400c0668u
#define CYREG_USBDEVv2_MEM_DATA155 0x400c066cu
#define CYREG_USBDEVv2_MEM_DATA156 0x400c0670u
#define CYREG_USBDEVv2_MEM_DATA157 0x400c0674u
#define CYREG_USBDEVv2_MEM_DATA158 0x400c0678u
#define CYREG_USBDEVv2_MEM_DATA159 0x400c067cu
#define CYREG_USBDEVv2_MEM_DATA160 0x400c0680u
#define CYREG_USBDEVv2_MEM_DATA161 0x400c0684u
#define CYREG_USBDEVv2_MEM_DATA162 0x400c0688u
#define CYREG_USBDEVv2_MEM_DATA163 0x400c068cu
#define CYREG_USBDEVv2_MEM_DATA164 0x400c0690u
#define CYREG_USBDEVv2_MEM_DATA165 0x400c0694u
#define CYREG_USBDEVv2_MEM_DATA166 0x400c0698u
#define CYREG_USBDEVv2_MEM_DATA167 0x400c069cu
#define CYREG_USBDEVv2_MEM_DATA168 0x400c06a0u
#define CYREG_USBDEVv2_MEM_DATA169 0x400c06a4u
#define CYREG_USBDEVv2_MEM_DATA170 0x400c06a8u
#define CYREG_USBDEVv2_MEM_DATA171 0x400c06acu
#define CYREG_USBDEVv2_MEM_DATA172 0x400c06b0u
#define CYREG_USBDEVv2_MEM_DATA173 0x400c06b4u
#define CYREG_USBDEVv2_MEM_DATA174 0x400c06b8u
#define CYREG_USBDEVv2_MEM_DATA175 0x400c06bcu
#define CYREG_USBDEVv2_MEM_DATA176 0x400c06c0u
#define CYREG_USBDEVv2_MEM_DATA177 0x400c06c4u
#define CYREG_USBDEVv2_MEM_DATA178 0x400c06c8u
#define CYREG_USBDEVv2_MEM_DATA179 0x400c06ccu
#define CYREG_USBDEVv2_MEM_DATA180 0x400c06d0u
#define CYREG_USBDEVv2_MEM_DATA181 0x400c06d4u
#define CYREG_USBDEVv2_MEM_DATA182 0x400c06d8u
#define CYREG_USBDEVv2_MEM_DATA183 0x400c06dcu
#define CYREG_USBDEVv2_MEM_DATA184 0x400c06e0u
#define CYREG_USBDEVv2_MEM_DATA185 0x400c06e4u
#define CYREG_USBDEVv2_MEM_DATA186 0x400c06e8u
#define CYREG_USBDEVv2_MEM_DATA187 0x400c06ecu
#define CYREG_USBDEVv2_MEM_DATA188 0x400c06f0u
#define CYREG_USBDEVv2_MEM_DATA189 0x400c06f4u
#define CYREG_USBDEVv2_MEM_DATA190 0x400c06f8u
#define CYREG_USBDEVv2_MEM_DATA191 0x400c06fcu
#define CYREG_USBDEVv2_MEM_DATA192 0x400c0700u
#define CYREG_USBDEVv2_MEM_DATA193 0x400c0704u
#define CYREG_USBDEVv2_MEM_DATA194 0x400c0708u
#define CYREG_USBDEVv2_MEM_DATA195 0x400c070cu
#define CYREG_USBDEVv2_MEM_DATA196 0x400c0710u
#define CYREG_USBDEVv2_MEM_DATA197 0x400c0714u
#define CYREG_USBDEVv2_MEM_DATA198 0x400c0718u
#define CYREG_USBDEVv2_MEM_DATA199 0x400c071cu
#define CYREG_USBDEVv2_MEM_DATA200 0x400c0720u
#define CYREG_USBDEVv2_MEM_DATA201 0x400c0724u
#define CYREG_USBDEVv2_MEM_DATA202 0x400c0728u
#define CYREG_USBDEVv2_MEM_DATA203 0x400c072cu
#define CYREG_USBDEVv2_MEM_DATA204 0x400c0730u
#define CYREG_USBDEVv2_MEM_DATA205 0x400c0734u
#define CYREG_USBDEVv2_MEM_DATA206 0x400c0738u
#define CYREG_USBDEVv2_MEM_DATA207 0x400c073cu
#define CYREG_USBDEVv2_MEM_DATA208 0x400c0740u
#define CYREG_USBDEVv2_MEM_DATA209 0x400c0744u
#define CYREG_USBDEVv2_MEM_DATA210 0x400c0748u
#define CYREG_USBDEVv2_MEM_DATA211 0x400c074cu
#define CYREG_USBDEVv2_MEM_DATA212 0x400c0750u
#define CYREG_USBDEVv2_MEM_DATA213 0x400c0754u
#define CYREG_USBDEVv2_MEM_DATA214 0x400c0758u
#define CYREG_USBDEVv2_MEM_DATA215 0x400c075cu
#define CYREG_USBDEVv2_MEM_DATA216 0x400c0760u
#define CYREG_USBDEVv2_MEM_DATA217 0x400c0764u
#define CYREG_USBDEVv2_MEM_DATA218 0x400c0768u
#define CYREG_USBDEVv2_MEM_DATA219 0x400c076cu
#define CYREG_USBDEVv2_MEM_DATA220 0x400c0770u
#define CYREG_USBDEVv2_MEM_DATA221 0x400c0774u
#define CYREG_USBDEVv2_MEM_DATA222 0x400c0778u
#define CYREG_USBDEVv2_MEM_DATA223 0x400c077cu
#define CYREG_USBDEVv2_MEM_DATA224 0x400c0780u
#define CYREG_USBDEVv2_MEM_DATA225 0x400c0784u
#define CYREG_USBDEVv2_MEM_DATA226 0x400c0788u
#define CYREG_USBDEVv2_MEM_DATA227 0x400c078cu
#define CYREG_USBDEVv2_MEM_DATA228 0x400c0790u
#define CYREG_USBDEVv2_MEM_DATA229 0x400c0794u
#define CYREG_USBDEVv2_MEM_DATA230 0x400c0798u
#define CYREG_USBDEVv2_MEM_DATA231 0x400c079cu
#define CYREG_USBDEVv2_MEM_DATA232 0x400c07a0u
#define CYREG_USBDEVv2_MEM_DATA233 0x400c07a4u
#define CYREG_USBDEVv2_MEM_DATA234 0x400c07a8u
#define CYREG_USBDEVv2_MEM_DATA235 0x400c07acu
#define CYREG_USBDEVv2_MEM_DATA236 0x400c07b0u
#define CYREG_USBDEVv2_MEM_DATA237 0x400c07b4u
#define CYREG_USBDEVv2_MEM_DATA238 0x400c07b8u
#define CYREG_USBDEVv2_MEM_DATA239 0x400c07bcu
#define CYREG_USBDEVv2_MEM_DATA240 0x400c07c0u
#define CYREG_USBDEVv2_MEM_DATA241 0x400c07c4u
#define CYREG_USBDEVv2_MEM_DATA242 0x400c07c8u
#define CYREG_USBDEVv2_MEM_DATA243 0x400c07ccu
#define CYREG_USBDEVv2_MEM_DATA244 0x400c07d0u
#define CYREG_USBDEVv2_MEM_DATA245 0x400c07d4u
#define CYREG_USBDEVv2_MEM_DATA246 0x400c07d8u
#define CYREG_USBDEVv2_MEM_DATA247 0x400c07dcu
#define CYREG_USBDEVv2_MEM_DATA248 0x400c07e0u
#define CYREG_USBDEVv2_MEM_DATA249 0x400c07e4u
#define CYREG_USBDEVv2_MEM_DATA250 0x400c07e8u
#define CYREG_USBDEVv2_MEM_DATA251 0x400c07ecu
#define CYREG_USBDEVv2_MEM_DATA252 0x400c07f0u
#define CYREG_USBDEVv2_MEM_DATA253 0x400c07f4u
#define CYREG_USBDEVv2_MEM_DATA254 0x400c07f8u
#define CYREG_USBDEVv2_MEM_DATA255 0x400c07fcu
#define CYREG_USBDEVv2_MEM_DATA256 0x400c0800u
#define CYREG_USBDEVv2_MEM_DATA257 0x400c0804u
#define CYREG_USBDEVv2_MEM_DATA258 0x400c0808u
#define CYREG_USBDEVv2_MEM_DATA259 0x400c080cu
#define CYREG_USBDEVv2_MEM_DATA260 0x400c0810u
#define CYREG_USBDEVv2_MEM_DATA261 0x400c0814u
#define CYREG_USBDEVv2_MEM_DATA262 0x400c0818u
#define CYREG_USBDEVv2_MEM_DATA263 0x400c081cu
#define CYREG_USBDEVv2_MEM_DATA264 0x400c0820u
#define CYREG_USBDEVv2_MEM_DATA265 0x400c0824u
#define CYREG_USBDEVv2_MEM_DATA266 0x400c0828u
#define CYREG_USBDEVv2_MEM_DATA267 0x400c082cu
#define CYREG_USBDEVv2_MEM_DATA268 0x400c0830u
#define CYREG_USBDEVv2_MEM_DATA269 0x400c0834u
#define CYREG_USBDEVv2_MEM_DATA270 0x400c0838u
#define CYREG_USBDEVv2_MEM_DATA271 0x400c083cu
#define CYREG_USBDEVv2_MEM_DATA272 0x400c0840u
#define CYREG_USBDEVv2_MEM_DATA273 0x400c0844u
#define CYREG_USBDEVv2_MEM_DATA274 0x400c0848u
#define CYREG_USBDEVv2_MEM_DATA275 0x400c084cu
#define CYREG_USBDEVv2_MEM_DATA276 0x400c0850u
#define CYREG_USBDEVv2_MEM_DATA277 0x400c0854u
#define CYREG_USBDEVv2_MEM_DATA278 0x400c0858u
#define CYREG_USBDEVv2_MEM_DATA279 0x400c085cu
#define CYREG_USBDEVv2_MEM_DATA280 0x400c0860u
#define CYREG_USBDEVv2_MEM_DATA281 0x400c0864u
#define CYREG_USBDEVv2_MEM_DATA282 0x400c0868u
#define CYREG_USBDEVv2_MEM_DATA283 0x400c086cu
#define CYREG_USBDEVv2_MEM_DATA284 0x400c0870u
#define CYREG_USBDEVv2_MEM_DATA285 0x400c0874u
#define CYREG_USBDEVv2_MEM_DATA286 0x400c0878u
#define CYREG_USBDEVv2_MEM_DATA287 0x400c087cu
#define CYREG_USBDEVv2_MEM_DATA288 0x400c0880u
#define CYREG_USBDEVv2_MEM_DATA289 0x400c0884u
#define CYREG_USBDEVv2_MEM_DATA290 0x400c0888u
#define CYREG_USBDEVv2_MEM_DATA291 0x400c088cu
#define CYREG_USBDEVv2_MEM_DATA292 0x400c0890u
#define CYREG_USBDEVv2_MEM_DATA293 0x400c0894u
#define CYREG_USBDEVv2_MEM_DATA294 0x400c0898u
#define CYREG_USBDEVv2_MEM_DATA295 0x400c089cu
#define CYREG_USBDEVv2_MEM_DATA296 0x400c08a0u
#define CYREG_USBDEVv2_MEM_DATA297 0x400c08a4u
#define CYREG_USBDEVv2_MEM_DATA298 0x400c08a8u
#define CYREG_USBDEVv2_MEM_DATA299 0x400c08acu
#define CYREG_USBDEVv2_MEM_DATA300 0x400c08b0u
#define CYREG_USBDEVv2_MEM_DATA301 0x400c08b4u
#define CYREG_USBDEVv2_MEM_DATA302 0x400c08b8u
#define CYREG_USBDEVv2_MEM_DATA303 0x400c08bcu
#define CYREG_USBDEVv2_MEM_DATA304 0x400c08c0u
#define CYREG_USBDEVv2_MEM_DATA305 0x400c08c4u
#define CYREG_USBDEVv2_MEM_DATA306 0x400c08c8u
#define CYREG_USBDEVv2_MEM_DATA307 0x400c08ccu
#define CYREG_USBDEVv2_MEM_DATA308 0x400c08d0u
#define CYREG_USBDEVv2_MEM_DATA309 0x400c08d4u
#define CYREG_USBDEVv2_MEM_DATA310 0x400c08d8u
#define CYREG_USBDEVv2_MEM_DATA311 0x400c08dcu
#define CYREG_USBDEVv2_MEM_DATA312 0x400c08e0u
#define CYREG_USBDEVv2_MEM_DATA313 0x400c08e4u
#define CYREG_USBDEVv2_MEM_DATA314 0x400c08e8u
#define CYREG_USBDEVv2_MEM_DATA315 0x400c08ecu
#define CYREG_USBDEVv2_MEM_DATA316 0x400c08f0u
#define CYREG_USBDEVv2_MEM_DATA317 0x400c08f4u
#define CYREG_USBDEVv2_MEM_DATA318 0x400c08f8u
#define CYREG_USBDEVv2_MEM_DATA319 0x400c08fcu
#define CYREG_USBDEVv2_MEM_DATA320 0x400c0900u
#define CYREG_USBDEVv2_MEM_DATA321 0x400c0904u
#define CYREG_USBDEVv2_MEM_DATA322 0x400c0908u
#define CYREG_USBDEVv2_MEM_DATA323 0x400c090cu
#define CYREG_USBDEVv2_MEM_DATA324 0x400c0910u
#define CYREG_USBDEVv2_MEM_DATA325 0x400c0914u
#define CYREG_USBDEVv2_MEM_DATA326 0x400c0918u
#define CYREG_USBDEVv2_MEM_DATA327 0x400c091cu
#define CYREG_USBDEVv2_MEM_DATA328 0x400c0920u
#define CYREG_USBDEVv2_MEM_DATA329 0x400c0924u
#define CYREG_USBDEVv2_MEM_DATA330 0x400c0928u
#define CYREG_USBDEVv2_MEM_DATA331 0x400c092cu
#define CYREG_USBDEVv2_MEM_DATA332 0x400c0930u
#define CYREG_USBDEVv2_MEM_DATA333 0x400c0934u
#define CYREG_USBDEVv2_MEM_DATA334 0x400c0938u
#define CYREG_USBDEVv2_MEM_DATA335 0x400c093cu
#define CYREG_USBDEVv2_MEM_DATA336 0x400c0940u
#define CYREG_USBDEVv2_MEM_DATA337 0x400c0944u
#define CYREG_USBDEVv2_MEM_DATA338 0x400c0948u
#define CYREG_USBDEVv2_MEM_DATA339 0x400c094cu
#define CYREG_USBDEVv2_MEM_DATA340 0x400c0950u
#define CYREG_USBDEVv2_MEM_DATA341 0x400c0954u
#define CYREG_USBDEVv2_MEM_DATA342 0x400c0958u
#define CYREG_USBDEVv2_MEM_DATA343 0x400c095cu
#define CYREG_USBDEVv2_MEM_DATA344 0x400c0960u
#define CYREG_USBDEVv2_MEM_DATA345 0x400c0964u
#define CYREG_USBDEVv2_MEM_DATA346 0x400c0968u
#define CYREG_USBDEVv2_MEM_DATA347 0x400c096cu
#define CYREG_USBDEVv2_MEM_DATA348 0x400c0970u
#define CYREG_USBDEVv2_MEM_DATA349 0x400c0974u
#define CYREG_USBDEVv2_MEM_DATA350 0x400c0978u
#define CYREG_USBDEVv2_MEM_DATA351 0x400c097cu
#define CYREG_USBDEVv2_MEM_DATA352 0x400c0980u
#define CYREG_USBDEVv2_MEM_DATA353 0x400c0984u
#define CYREG_USBDEVv2_MEM_DATA354 0x400c0988u
#define CYREG_USBDEVv2_MEM_DATA355 0x400c098cu
#define CYREG_USBDEVv2_MEM_DATA356 0x400c0990u
#define CYREG_USBDEVv2_MEM_DATA357 0x400c0994u
#define CYREG_USBDEVv2_MEM_DATA358 0x400c0998u
#define CYREG_USBDEVv2_MEM_DATA359 0x400c099cu
#define CYREG_USBDEVv2_MEM_DATA360 0x400c09a0u
#define CYREG_USBDEVv2_MEM_DATA361 0x400c09a4u
#define CYREG_USBDEVv2_MEM_DATA362 0x400c09a8u
#define CYREG_USBDEVv2_MEM_DATA363 0x400c09acu
#define CYREG_USBDEVv2_MEM_DATA364 0x400c09b0u
#define CYREG_USBDEVv2_MEM_DATA365 0x400c09b4u
#define CYREG_USBDEVv2_MEM_DATA366 0x400c09b8u
#define CYREG_USBDEVv2_MEM_DATA367 0x400c09bcu
#define CYREG_USBDEVv2_MEM_DATA368 0x400c09c0u
#define CYREG_USBDEVv2_MEM_DATA369 0x400c09c4u
#define CYREG_USBDEVv2_MEM_DATA370 0x400c09c8u
#define CYREG_USBDEVv2_MEM_DATA371 0x400c09ccu
#define CYREG_USBDEVv2_MEM_DATA372 0x400c09d0u
#define CYREG_USBDEVv2_MEM_DATA373 0x400c09d4u
#define CYREG_USBDEVv2_MEM_DATA374 0x400c09d8u
#define CYREG_USBDEVv2_MEM_DATA375 0x400c09dcu
#define CYREG_USBDEVv2_MEM_DATA376 0x400c09e0u
#define CYREG_USBDEVv2_MEM_DATA377 0x400c09e4u
#define CYREG_USBDEVv2_MEM_DATA378 0x400c09e8u
#define CYREG_USBDEVv2_MEM_DATA379 0x400c09ecu
#define CYREG_USBDEVv2_MEM_DATA380 0x400c09f0u
#define CYREG_USBDEVv2_MEM_DATA381 0x400c09f4u
#define CYREG_USBDEVv2_MEM_DATA382 0x400c09f8u
#define CYREG_USBDEVv2_MEM_DATA383 0x400c09fcu
#define CYREG_USBDEVv2_MEM_DATA384 0x400c0a00u
#define CYREG_USBDEVv2_MEM_DATA385 0x400c0a04u
#define CYREG_USBDEVv2_MEM_DATA386 0x400c0a08u
#define CYREG_USBDEVv2_MEM_DATA387 0x400c0a0cu
#define CYREG_USBDEVv2_MEM_DATA388 0x400c0a10u
#define CYREG_USBDEVv2_MEM_DATA389 0x400c0a14u
#define CYREG_USBDEVv2_MEM_DATA390 0x400c0a18u
#define CYREG_USBDEVv2_MEM_DATA391 0x400c0a1cu
#define CYREG_USBDEVv2_MEM_DATA392 0x400c0a20u
#define CYREG_USBDEVv2_MEM_DATA393 0x400c0a24u
#define CYREG_USBDEVv2_MEM_DATA394 0x400c0a28u
#define CYREG_USBDEVv2_MEM_DATA395 0x400c0a2cu
#define CYREG_USBDEVv2_MEM_DATA396 0x400c0a30u
#define CYREG_USBDEVv2_MEM_DATA397 0x400c0a34u
#define CYREG_USBDEVv2_MEM_DATA398 0x400c0a38u
#define CYREG_USBDEVv2_MEM_DATA399 0x400c0a3cu
#define CYREG_USBDEVv2_MEM_DATA400 0x400c0a40u
#define CYREG_USBDEVv2_MEM_DATA401 0x400c0a44u
#define CYREG_USBDEVv2_MEM_DATA402 0x400c0a48u
#define CYREG_USBDEVv2_MEM_DATA403 0x400c0a4cu
#define CYREG_USBDEVv2_MEM_DATA404 0x400c0a50u
#define CYREG_USBDEVv2_MEM_DATA405 0x400c0a54u
#define CYREG_USBDEVv2_MEM_DATA406 0x400c0a58u
#define CYREG_USBDEVv2_MEM_DATA407 0x400c0a5cu
#define CYREG_USBDEVv2_MEM_DATA408 0x400c0a60u
#define CYREG_USBDEVv2_MEM_DATA409 0x400c0a64u
#define CYREG_USBDEVv2_MEM_DATA410 0x400c0a68u
#define CYREG_USBDEVv2_MEM_DATA411 0x400c0a6cu
#define CYREG_USBDEVv2_MEM_DATA412 0x400c0a70u
#define CYREG_USBDEVv2_MEM_DATA413 0x400c0a74u
#define CYREG_USBDEVv2_MEM_DATA414 0x400c0a78u
#define CYREG_USBDEVv2_MEM_DATA415 0x400c0a7cu
#define CYREG_USBDEVv2_MEM_DATA416 0x400c0a80u
#define CYREG_USBDEVv2_MEM_DATA417 0x400c0a84u
#define CYREG_USBDEVv2_MEM_DATA418 0x400c0a88u
#define CYREG_USBDEVv2_MEM_DATA419 0x400c0a8cu
#define CYREG_USBDEVv2_MEM_DATA420 0x400c0a90u
#define CYREG_USBDEVv2_MEM_DATA421 0x400c0a94u
#define CYREG_USBDEVv2_MEM_DATA422 0x400c0a98u
#define CYREG_USBDEVv2_MEM_DATA423 0x400c0a9cu
#define CYREG_USBDEVv2_MEM_DATA424 0x400c0aa0u
#define CYREG_USBDEVv2_MEM_DATA425 0x400c0aa4u
#define CYREG_USBDEVv2_MEM_DATA426 0x400c0aa8u
#define CYREG_USBDEVv2_MEM_DATA427 0x400c0aacu
#define CYREG_USBDEVv2_MEM_DATA428 0x400c0ab0u
#define CYREG_USBDEVv2_MEM_DATA429 0x400c0ab4u
#define CYREG_USBDEVv2_MEM_DATA430 0x400c0ab8u
#define CYREG_USBDEVv2_MEM_DATA431 0x400c0abcu
#define CYREG_USBDEVv2_MEM_DATA432 0x400c0ac0u
#define CYREG_USBDEVv2_MEM_DATA433 0x400c0ac4u
#define CYREG_USBDEVv2_MEM_DATA434 0x400c0ac8u
#define CYREG_USBDEVv2_MEM_DATA435 0x400c0accu
#define CYREG_USBDEVv2_MEM_DATA436 0x400c0ad0u
#define CYREG_USBDEVv2_MEM_DATA437 0x400c0ad4u
#define CYREG_USBDEVv2_MEM_DATA438 0x400c0ad8u
#define CYREG_USBDEVv2_MEM_DATA439 0x400c0adcu
#define CYREG_USBDEVv2_MEM_DATA440 0x400c0ae0u
#define CYREG_USBDEVv2_MEM_DATA441 0x400c0ae4u
#define CYREG_USBDEVv2_MEM_DATA442 0x400c0ae8u
#define CYREG_USBDEVv2_MEM_DATA443 0x400c0aecu
#define CYREG_USBDEVv2_MEM_DATA444 0x400c0af0u
#define CYREG_USBDEVv2_MEM_DATA445 0x400c0af4u
#define CYREG_USBDEVv2_MEM_DATA446 0x400c0af8u
#define CYREG_USBDEVv2_MEM_DATA447 0x400c0afcu
#define CYREG_USBDEVv2_MEM_DATA448 0x400c0b00u
#define CYREG_USBDEVv2_MEM_DATA449 0x400c0b04u
#define CYREG_USBDEVv2_MEM_DATA450 0x400c0b08u
#define CYREG_USBDEVv2_MEM_DATA451 0x400c0b0cu
#define CYREG_USBDEVv2_MEM_DATA452 0x400c0b10u
#define CYREG_USBDEVv2_MEM_DATA453 0x400c0b14u
#define CYREG_USBDEVv2_MEM_DATA454 0x400c0b18u
#define CYREG_USBDEVv2_MEM_DATA455 0x400c0b1cu
#define CYREG_USBDEVv2_MEM_DATA456 0x400c0b20u
#define CYREG_USBDEVv2_MEM_DATA457 0x400c0b24u
#define CYREG_USBDEVv2_MEM_DATA458 0x400c0b28u
#define CYREG_USBDEVv2_MEM_DATA459 0x400c0b2cu
#define CYREG_USBDEVv2_MEM_DATA460 0x400c0b30u
#define CYREG_USBDEVv2_MEM_DATA461 0x400c0b34u
#define CYREG_USBDEVv2_MEM_DATA462 0x400c0b38u
#define CYREG_USBDEVv2_MEM_DATA463 0x400c0b3cu
#define CYREG_USBDEVv2_MEM_DATA464 0x400c0b40u
#define CYREG_USBDEVv2_MEM_DATA465 0x400c0b44u
#define CYREG_USBDEVv2_MEM_DATA466 0x400c0b48u
#define CYREG_USBDEVv2_MEM_DATA467 0x400c0b4cu
#define CYREG_USBDEVv2_MEM_DATA468 0x400c0b50u
#define CYREG_USBDEVv2_MEM_DATA469 0x400c0b54u
#define CYREG_USBDEVv2_MEM_DATA470 0x400c0b58u
#define CYREG_USBDEVv2_MEM_DATA471 0x400c0b5cu
#define CYREG_USBDEVv2_MEM_DATA472 0x400c0b60u
#define CYREG_USBDEVv2_MEM_DATA473 0x400c0b64u
#define CYREG_USBDEVv2_MEM_DATA474 0x400c0b68u
#define CYREG_USBDEVv2_MEM_DATA475 0x400c0b6cu
#define CYREG_USBDEVv2_MEM_DATA476 0x400c0b70u
#define CYREG_USBDEVv2_MEM_DATA477 0x400c0b74u
#define CYREG_USBDEVv2_MEM_DATA478 0x400c0b78u
#define CYREG_USBDEVv2_MEM_DATA479 0x400c0b7cu
#define CYREG_USBDEVv2_MEM_DATA480 0x400c0b80u
#define CYREG_USBDEVv2_MEM_DATA481 0x400c0b84u
#define CYREG_USBDEVv2_MEM_DATA482 0x400c0b88u
#define CYREG_USBDEVv2_MEM_DATA483 0x400c0b8cu
#define CYREG_USBDEVv2_MEM_DATA484 0x400c0b90u
#define CYREG_USBDEVv2_MEM_DATA485 0x400c0b94u
#define CYREG_USBDEVv2_MEM_DATA486 0x400c0b98u
#define CYREG_USBDEVv2_MEM_DATA487 0x400c0b9cu
#define CYREG_USBDEVv2_MEM_DATA488 0x400c0ba0u
#define CYREG_USBDEVv2_MEM_DATA489 0x400c0ba4u
#define CYREG_USBDEVv2_MEM_DATA490 0x400c0ba8u
#define CYREG_USBDEVv2_MEM_DATA491 0x400c0bacu
#define CYREG_USBDEVv2_MEM_DATA492 0x400c0bb0u
#define CYREG_USBDEVv2_MEM_DATA493 0x400c0bb4u
#define CYREG_USBDEVv2_MEM_DATA494 0x400c0bb8u
#define CYREG_USBDEVv2_MEM_DATA495 0x400c0bbcu
#define CYREG_USBDEVv2_MEM_DATA496 0x400c0bc0u
#define CYREG_USBDEVv2_MEM_DATA497 0x400c0bc4u
#define CYREG_USBDEVv2_MEM_DATA498 0x400c0bc8u
#define CYREG_USBDEVv2_MEM_DATA499 0x400c0bccu
#define CYREG_USBDEVv2_MEM_DATA500 0x400c0bd0u
#define CYREG_USBDEVv2_MEM_DATA501 0x400c0bd4u
#define CYREG_USBDEVv2_MEM_DATA502 0x400c0bd8u
#define CYREG_USBDEVv2_MEM_DATA503 0x400c0bdcu
#define CYREG_USBDEVv2_MEM_DATA504 0x400c0be0u
#define CYREG_USBDEVv2_MEM_DATA505 0x400c0be4u
#define CYREG_USBDEVv2_MEM_DATA506 0x400c0be8u
#define CYREG_USBDEVv2_MEM_DATA507 0x400c0becu
#define CYREG_USBDEVv2_MEM_DATA508 0x400c0bf0u
#define CYREG_USBDEVv2_MEM_DATA509 0x400c0bf4u
#define CYREG_USBDEVv2_MEM_DATA510 0x400c0bf8u
#define CYREG_USBDEVv2_MEM_DATA511 0x400c0bfcu
#define CYREG_USBDEVv2_SOF16 0x400c1060u
#define CYFLD_USBDEVv2_FRAME_NUMBER16__OFFSET 0x00000000u
#define CYFLD_USBDEVv2_FRAME_NUMBER16__SIZE 0x0000000bu
#define CYREG_USBDEVv2_OSCLK_DR16 0x400c1080u
#define CYFLD_USBDEVv2_ADDER16__OFFSET 0x00000000u
#define CYFLD_USBDEVv2_ADDER16__SIZE 0x0000000fu
#define CYREG_USBDEVv2_ARB_RW1_WA16 0x400c1210u
#define CYFLD_USBDEVv2_WA16__OFFSET 0x00000000u
#define CYFLD_USBDEVv2_WA16__SIZE 0x00000009u
#define CYREG_USBDEVv2_ARB_RW1_RA16 0x400c1218u
#define CYFLD_USBDEVv2_RA16__OFFSET 0x00000000u
#define CYFLD_USBDEVv2_RA16__SIZE 0x00000009u
#define CYREG_USBDEVv2_ARB_RW1_DR16 0x400c1220u
#define CYFLD_USBDEVv2_DR16__OFFSET 0x00000000u
#define CYFLD_USBDEVv2_DR16__SIZE 0x00000010u
#define CYREG_USBDEVv2_ARB_RW2_WA16 0x400c1250u
#define CYREG_USBDEVv2_ARB_RW2_RA16 0x400c1258u
#define CYREG_USBDEVv2_ARB_RW2_DR16 0x400c1260u
#define CYREG_USBDEVv2_ARB_RW3_WA16 0x400c1290u
#define CYREG_USBDEVv2_ARB_RW3_RA16 0x400c1298u
#define CYREG_USBDEVv2_ARB_RW3_DR16 0x400c12a0u
#define CYREG_USBDEVv2_CWA16 0x400c12b0u
#define CYFLD_USBDEVv2_CWA16__OFFSET 0x00000000u
#define CYFLD_USBDEVv2_CWA16__SIZE 0x00000009u
#define CYREG_USBDEVv2_ARB_RW4_WA16 0x400c12d0u
#define CYREG_USBDEVv2_ARB_RW4_RA16 0x400c12d8u
#define CYREG_USBDEVv2_ARB_RW4_DR16 0x400c12e0u
#define CYREG_USBDEVv2_DMA_THRES16 0x400c12f0u
#define CYFLD_USBDEVv2_DMA_THS16__OFFSET 0x00000000u
#define CYFLD_USBDEVv2_DMA_THS16__SIZE 0x00000009u
#define CYREG_USBDEVv2_ARB_RW5_WA16 0x400c1310u
#define CYREG_USBDEVv2_ARB_RW5_RA16 0x400c1318u
#define CYREG_USBDEVv2_ARB_RW5_DR16 0x400c1320u
#define CYREG_USBDEVv2_ARB_RW6_WA16 0x400c1350u
#define CYREG_USBDEVv2_ARB_RW6_RA16 0x400c1358u
#define CYREG_USBDEVv2_ARB_RW6_DR16 0x400c1360u
#define CYREG_USBDEVv2_ARB_RW7_WA16 0x400c1390u
#define CYREG_USBDEVv2_ARB_RW7_RA16 0x400c1398u
#define CYREG_USBDEVv2_ARB_RW7_DR16 0x400c13a0u
#define CYREG_USBDEVv2_ARB_RW8_WA16 0x400c13d0u
#define CYREG_USBDEVv2_ARB_RW8_RA16 0x400c13d8u
#define CYREG_USBDEVv2_ARB_RW8_DR16 0x400c13e0u
#define CYDEV_USBDEVv2_USB_BASE 0x400c2000u
#define CYDEV_USBDEVv2_USB_SIZE 0x00001000u
#define CYREG_USBDEVv2_USB_POWER_CTRL 0x400c2000u
#define CYFLD_USBDEVv2_USB_VBUS_VALID_OVR__OFFSET 0x00000000u
#define CYFLD_USBDEVv2_USB_VBUS_VALID_OVR__SIZE 0x00000002u
#define CYFLD_USBDEVv2_USB_SUSPEND__OFFSET 0x00000002u
#define CYFLD_USBDEVv2_USB_SUSPEND__SIZE 0x00000001u
#define CYFLD_USBDEVv2_USB_SUSPEND_DEL__OFFSET 0x00000003u
#define CYFLD_USBDEVv2_USB_SUSPEND_DEL__SIZE 0x00000001u
#define CYFLD_USBDEVv2_USB_ISOLATE__OFFSET 0x00000004u
#define CYFLD_USBDEVv2_USB_ISOLATE__SIZE 0x00000001u
#define CYFLD_USBDEVv2_USB_ENABLE_RCVR__OFFSET 0x0000001bu
#define CYFLD_USBDEVv2_USB_ENABLE_RCVR__SIZE 0x00000001u
#define CYFLD_USBDEVv2_USB_ENABLE_DPO__OFFSET 0x0000001cu
#define CYFLD_USBDEVv2_USB_ENABLE_DPO__SIZE 0x00000001u
#define CYFLD_USBDEVv2_USB_ENABLE_DMO__OFFSET 0x0000001du
#define CYFLD_USBDEVv2_USB_ENABLE_DMO__SIZE 0x00000001u
/* Duplicate field name in USBDEVv2_USB: ENABLE [31] (previous: [7]) */
#define CYREG_USBDEVv2_USB_USBIO_CTRL 0x400c2008u
#define CYFLD_USBDEVv2_USB_DM_P__OFFSET 0x00000000u
#define CYFLD_USBDEVv2_USB_DM_P__SIZE 0x00000003u
#define CYVAL_USBDEVv2_USB_DM_P_OFF 0x00000000u
#define CYVAL_USBDEVv2_USB_DM_P_INPUT 0x00000001u
#define CYVAL_USBDEVv2_USB_DM_P_0_PU 0x00000002u
#define CYVAL_USBDEVv2_USB_DM_P_0_Z 0x00000004u
#define CYVAL_USBDEVv2_USB_DM_P_0_1 0x00000006u
#define CYFLD_USBDEVv2_USB_DM_M__OFFSET 0x00000003u
#define CYFLD_USBDEVv2_USB_DM_M__SIZE 0x00000003u
#define CYREG_USBDEVv2_USB_FLOW_CTRL 0x400c200cu
#define CYFLD_USBDEVv2_USB_EP1_ERR_RESP__OFFSET 0x00000000u
#define CYFLD_USBDEVv2_USB_EP1_ERR_RESP__SIZE 0x00000001u
#define CYFLD_USBDEVv2_USB_EP2_ERR_RESP__OFFSET 0x00000001u
#define CYFLD_USBDEVv2_USB_EP2_ERR_RESP__SIZE 0x00000001u
#define CYFLD_USBDEVv2_USB_EP3_ERR_RESP__OFFSET 0x00000002u
#define CYFLD_USBDEVv2_USB_EP3_ERR_RESP__SIZE 0x00000001u
#define CYFLD_USBDEVv2_USB_EP4_ERR_RESP__OFFSET 0x00000003u
#define CYFLD_USBDEVv2_USB_EP4_ERR_RESP__SIZE 0x00000001u
#define CYFLD_USBDEVv2_USB_EP5_ERR_RESP__OFFSET 0x00000004u
#define CYFLD_USBDEVv2_USB_EP5_ERR_RESP__SIZE 0x00000001u
#define CYFLD_USBDEVv2_USB_EP6_ERR_RESP__OFFSET 0x00000005u
#define CYFLD_USBDEVv2_USB_EP6_ERR_RESP__SIZE 0x00000001u
#define CYFLD_USBDEVv2_USB_EP7_ERR_RESP__OFFSET 0x00000006u
#define CYFLD_USBDEVv2_USB_EP7_ERR_RESP__SIZE 0x00000001u
#define CYFLD_USBDEVv2_USB_EP8_ERR_RESP__OFFSET 0x00000007u
#define CYFLD_USBDEVv2_USB_EP8_ERR_RESP__SIZE 0x00000001u
#define CYREG_USBDEVv2_USB_LPM_CTRL 0x400c2010u
#define CYFLD_USBDEVv2_USB_LPM_EN__OFFSET 0x00000000u
#define CYFLD_USBDEVv2_USB_LPM_EN__SIZE 0x00000001u
#define CYFLD_USBDEVv2_USB_LPM_ACK_RESP__OFFSET 0x00000001u
#define CYFLD_USBDEVv2_USB_LPM_ACK_RESP__SIZE 0x00000001u
#define CYFLD_USBDEVv2_USB_NYET_EN__OFFSET 0x00000002u
#define CYFLD_USBDEVv2_USB_NYET_EN__SIZE 0x00000001u
#define CYFLD_USBDEVv2_USB_SUB_RESP__OFFSET 0x00000004u
#define CYFLD_USBDEVv2_USB_SUB_RESP__SIZE 0x00000001u
#define CYREG_USBDEVv2_USB_LPM_STAT 0x400c2014u
#define CYFLD_USBDEVv2_USB_LPM_BESL__OFFSET 0x00000000u
#define CYFLD_USBDEVv2_USB_LPM_BESL__SIZE 0x00000004u
#define CYFLD_USBDEVv2_USB_LPM_REMOTEWAKE__OFFSET 0x00000004u
#define CYFLD_USBDEVv2_USB_LPM_REMOTEWAKE__SIZE 0x00000001u
#define CYREG_USBDEVv2_USB_INTR_SIE 0x400c2020u
#define CYFLD_USBDEVv2_USB_SOF_INTR__OFFSET 0x00000000u
#define CYFLD_USBDEVv2_USB_SOF_INTR__SIZE 0x00000001u
#define CYFLD_USBDEVv2_USB_BUS_RESET_INTR__OFFSET 0x00000001u
#define CYFLD_USBDEVv2_USB_BUS_RESET_INTR__SIZE 0x00000001u
#define CYFLD_USBDEVv2_USB_EP0_INTR__OFFSET 0x00000002u
#define CYFLD_USBDEVv2_USB_EP0_INTR__SIZE 0x00000001u
#define CYFLD_USBDEVv2_USB_LPM_INTR__OFFSET 0x00000003u
#define CYFLD_USBDEVv2_USB_LPM_INTR__SIZE 0x00000001u
#define CYFLD_USBDEVv2_USB_RESUME_INTR__OFFSET 0x00000004u
#define CYFLD_USBDEVv2_USB_RESUME_INTR__SIZE 0x00000001u
#define CYREG_USBDEVv2_USB_INTR_SIE_SET 0x400c2024u
#define CYFLD_USBDEVv2_USB_SOF_INTR_SET__OFFSET 0x00000000u
#define CYFLD_USBDEVv2_USB_SOF_INTR_SET__SIZE 0x00000001u
#define CYFLD_USBDEVv2_USB_BUS_RESET_INTR_SET__OFFSET 0x00000001u
#define CYFLD_USBDEVv2_USB_BUS_RESET_INTR_SET__SIZE 0x00000001u
#define CYFLD_USBDEVv2_USB_EP0_INTR_SET__OFFSET 0x00000002u
#define CYFLD_USBDEVv2_USB_EP0_INTR_SET__SIZE 0x00000001u
#define CYFLD_USBDEVv2_USB_LPM_INTR_SET__OFFSET 0x00000003u
#define CYFLD_USBDEVv2_USB_LPM_INTR_SET__SIZE 0x00000001u
#define CYFLD_USBDEVv2_USB_RESUME_INTR_SET__OFFSET 0x00000004u
#define CYFLD_USBDEVv2_USB_RESUME_INTR_SET__SIZE 0x00000001u
#define CYREG_USBDEVv2_USB_INTR_SIE_MASK 0x400c2028u
#define CYFLD_USBDEVv2_USB_SOF_INTR_MASK__OFFSET 0x00000000u
#define CYFLD_USBDEVv2_USB_SOF_INTR_MASK__SIZE 0x00000001u
#define CYFLD_USBDEVv2_USB_BUS_RESET_INTR_MASK__OFFSET 0x00000001u
#define CYFLD_USBDEVv2_USB_BUS_RESET_INTR_MASK__SIZE 0x00000001u
#define CYFLD_USBDEVv2_USB_EP0_INTR_MASK__OFFSET 0x00000002u
#define CYFLD_USBDEVv2_USB_EP0_INTR_MASK__SIZE 0x00000001u
#define CYFLD_USBDEVv2_USB_LPM_INTR_MASK__OFFSET 0x00000003u
#define CYFLD_USBDEVv2_USB_LPM_INTR_MASK__SIZE 0x00000001u
#define CYFLD_USBDEVv2_USB_RESUME_INTR_MASK__OFFSET 0x00000004u
#define CYFLD_USBDEVv2_USB_RESUME_INTR_MASK__SIZE 0x00000001u
#define CYREG_USBDEVv2_USB_INTR_SIE_MASKED 0x400c202cu
#define CYFLD_USBDEVv2_USB_SOF_INTR_MASKED__OFFSET 0x00000000u
#define CYFLD_USBDEVv2_USB_SOF_INTR_MASKED__SIZE 0x00000001u
#define CYFLD_USBDEVv2_USB_BUS_RESET_INTR_MASKED__OFFSET 0x00000001u
#define CYFLD_USBDEVv2_USB_BUS_RESET_INTR_MASKED__SIZE 0x00000001u
#define CYFLD_USBDEVv2_USB_EP0_INTR_MASKED__OFFSET 0x00000002u
#define CYFLD_USBDEVv2_USB_EP0_INTR_MASKED__SIZE 0x00000001u
#define CYFLD_USBDEVv2_USB_LPM_INTR_MASKED__OFFSET 0x00000003u
#define CYFLD_USBDEVv2_USB_LPM_INTR_MASKED__SIZE 0x00000001u
#define CYFLD_USBDEVv2_USB_RESUME_INTR_MASKED__OFFSET 0x00000004u
#define CYFLD_USBDEVv2_USB_RESUME_INTR_MASKED__SIZE 0x00000001u
#define CYREG_USBDEVv2_USB_INTR_LVL_SEL 0x400c2030u
#define CYFLD_USBDEVv2_USB_SOF_LVL_SEL__OFFSET 0x00000000u
#define CYFLD_USBDEVv2_USB_SOF_LVL_SEL__SIZE 0x00000002u
#define CYVAL_USBDEVv2_USB_SOF_LVL_SEL_HI 0x00000000u
#define CYVAL_USBDEVv2_USB_SOF_LVL_SEL_MED 0x00000001u
#define CYVAL_USBDEVv2_USB_SOF_LVL_SEL_LO 0x00000002u
#define CYVAL_USBDEVv2_USB_SOF_LVL_SEL_RESERVED 0x00000003u
#define CYFLD_USBDEVv2_USB_BUS_RESET_LVL_SEL__OFFSET 0x00000002u
#define CYFLD_USBDEVv2_USB_BUS_RESET_LVL_SEL__SIZE 0x00000002u
#define CYFLD_USBDEVv2_USB_EP0_LVL_SEL__OFFSET 0x00000004u
#define CYFLD_USBDEVv2_USB_EP0_LVL_SEL__SIZE 0x00000002u
#define CYFLD_USBDEVv2_USB_LPM_LVL_SEL__OFFSET 0x00000006u
#define CYFLD_USBDEVv2_USB_LPM_LVL_SEL__SIZE 0x00000002u
#define CYFLD_USBDEVv2_USB_RESUME_LVL_SEL__OFFSET 0x00000008u
#define CYFLD_USBDEVv2_USB_RESUME_LVL_SEL__SIZE 0x00000002u
#define CYFLD_USBDEVv2_USB_ARB_EP_LVL_SEL__OFFSET 0x0000000eu
#define CYFLD_USBDEVv2_USB_ARB_EP_LVL_SEL__SIZE 0x00000002u
#define CYFLD_USBDEVv2_USB_EP1_LVL_SEL__OFFSET 0x00000010u
#define CYFLD_USBDEVv2_USB_EP1_LVL_SEL__SIZE 0x00000002u
#define CYFLD_USBDEVv2_USB_EP2_LVL_SEL__OFFSET 0x00000012u
#define CYFLD_USBDEVv2_USB_EP2_LVL_SEL__SIZE 0x00000002u
#define CYFLD_USBDEVv2_USB_EP3_LVL_SEL__OFFSET 0x00000014u
#define CYFLD_USBDEVv2_USB_EP3_LVL_SEL__SIZE 0x00000002u
#define CYFLD_USBDEVv2_USB_EP4_LVL_SEL__OFFSET 0x00000016u
#define CYFLD_USBDEVv2_USB_EP4_LVL_SEL__SIZE 0x00000002u
#define CYFLD_USBDEVv2_USB_EP5_LVL_SEL__OFFSET 0x00000018u
#define CYFLD_USBDEVv2_USB_EP5_LVL_SEL__SIZE 0x00000002u
#define CYFLD_USBDEVv2_USB_EP6_LVL_SEL__OFFSET 0x0000001au
#define CYFLD_USBDEVv2_USB_EP6_LVL_SEL__SIZE 0x00000002u
#define CYFLD_USBDEVv2_USB_EP7_LVL_SEL__OFFSET 0x0000001cu
#define CYFLD_USBDEVv2_USB_EP7_LVL_SEL__SIZE 0x00000002u
#define CYFLD_USBDEVv2_USB_EP8_LVL_SEL__OFFSET 0x0000001eu
#define CYFLD_USBDEVv2_USB_EP8_LVL_SEL__SIZE 0x00000002u
#define CYREG_USBDEVv2_USB_INTR_CAUSE_HI 0x400c2034u
#define CYFLD_USBDEVv2_USB_ARB_EP_INTR__OFFSET 0x00000007u
#define CYFLD_USBDEVv2_USB_ARB_EP_INTR__SIZE 0x00000001u
#define CYFLD_USBDEVv2_USB_EP1_INTR__OFFSET 0x00000008u
#define CYFLD_USBDEVv2_USB_EP1_INTR__SIZE 0x00000001u
#define CYFLD_USBDEVv2_USB_EP2_INTR__OFFSET 0x00000009u
#define CYFLD_USBDEVv2_USB_EP2_INTR__SIZE 0x00000001u
#define CYFLD_USBDEVv2_USB_EP3_INTR__OFFSET 0x0000000au
#define CYFLD_USBDEVv2_USB_EP3_INTR__SIZE 0x00000001u
#define CYFLD_USBDEVv2_USB_EP4_INTR__OFFSET 0x0000000bu
#define CYFLD_USBDEVv2_USB_EP4_INTR__SIZE 0x00000001u
#define CYFLD_USBDEVv2_USB_EP5_INTR__OFFSET 0x0000000cu
#define CYFLD_USBDEVv2_USB_EP5_INTR__SIZE 0x00000001u
#define CYFLD_USBDEVv2_USB_EP6_INTR__OFFSET 0x0000000du
#define CYFLD_USBDEVv2_USB_EP6_INTR__SIZE 0x00000001u
#define CYFLD_USBDEVv2_USB_EP7_INTR__OFFSET 0x0000000eu
#define CYFLD_USBDEVv2_USB_EP7_INTR__SIZE 0x00000001u
#define CYFLD_USBDEVv2_USB_EP8_INTR__OFFSET 0x0000000fu
#define CYFLD_USBDEVv2_USB_EP8_INTR__SIZE 0x00000001u
#define CYREG_USBDEVv2_USB_INTR_CAUSE_MED 0x400c2038u
#define CYREG_USBDEVv2_USB_INTR_CAUSE_LO 0x400c203cu
#define CYREG_USBDEVv2_USB_DFT_CTRL 0x400c2070u
#define CYFLD_USBDEVv2_USB_DDFT_SEL__OFFSET 0x00000000u
#define CYFLD_USBDEVv2_USB_DDFT_SEL__SIZE 0x00000003u
#define CYVAL_USBDEVv2_USB_DDFT_SEL_OFF 0x00000000u
#define CYVAL_USBDEVv2_USB_DDFT_SEL_DP_SE 0x00000001u
#define CYVAL_USBDEVv2_USB_DDFT_SEL_DM_SE 0x00000002u
#define CYVAL_USBDEVv2_USB_DDFT_SEL_RCV_DF 0x00000003u
#define CYVAL_USBDEVv2_USB_DDFT_SEL_CHRG_DET 0x00000004u
#define CYVAL_USBDEVv2_USB_DDFT_SEL_VBUS_DET 0x00000005u
#define CYFLD_USBDEVv2_USB_ADFT_VREFOUT_SEL__OFFSET 0x00000008u
#define CYFLD_USBDEVv2_USB_ADFT_VREFOUT_SEL__SIZE 0x00000002u
#define CYVAL_USBDEVv2_USB_ADFT_VREFOUT_SEL_OPEN 0x00000000u
#define CYVAL_USBDEVv2_USB_ADFT_VREFOUT_SEL_AMUXA 0x00000001u
#define CYVAL_USBDEVv2_USB_ADFT_VREFOUT_SEL_AMUXB 0x00000002u
#define CYVAL_USBDEVv2_USB_ADFT_VREFOUT_SEL_RSVD 0x00000003u
#define CYREG_USBDEVv2_USB_PHY_TRIM0 0x400c2f00u
#define CYFLD_USBDEVv2_USB_TRIM_DP_R_REG__OFFSET 0x00000000u
#define CYFLD_USBDEVv2_USB_TRIM_DP_R_REG__SIZE 0x00000006u
#define CYREG_USBDEVv2_USB_PHY_TRIM1 0x400c2f04u
#define CYFLD_USBDEVv2_USB_TRIM_DM_R_REG__OFFSET 0x00000000u
#define CYFLD_USBDEVv2_USB_TRIM_DM_R_REG__SIZE 0x00000006u
#define CYREG_USBDEVv2_USB_PHY_TRIM2 0x400c2f08u
#define CYFLD_USBDEVv2_USB_TRIM_DP_R_BYPASS__OFFSET 0x00000000u
#define CYFLD_USBDEVv2_USB_TRIM_DP_R_BYPASS__SIZE 0x00000006u
#define CYREG_USBDEVv2_USB_PHY_TRIM3 0x400c2f0cu
#define CYFLD_USBDEVv2_USB_TRIM_DM_R_BYPASS__OFFSET 0x00000000u
#define CYFLD_USBDEVv2_USB_TRIM_DM_R_BYPASS__SIZE 0x00000006u
#define CYREG_USBDEVv2_USB_CHGDET_TRIM 0x400c2f10u
#define CYFLD_USBDEVv2_USB_V325M_TRIM__OFFSET 0x00000000u
#define CYFLD_USBDEVv2_USB_V325M_TRIM__SIZE 0x00000002u
#define CYFLD_USBDEVv2_USB_V600M_TRIM__OFFSET 0x00000004u
#define CYFLD_USBDEVv2_USB_V600M_TRIM__SIZE 0x00000003u
#define CYREG_USBDEVv2_USB_TRIM 0x400c2f14u
#define CYFLD_USBDEVv2_USB_DM_PD_VAL__OFFSET 0x00000000u
#define CYFLD_USBDEVv2_USB_DM_PD_VAL__SIZE 0x00000002u
#define CYREG_USBDEVv2_USB_USBIO_TRIM 0x400c2f18u
#define CYFLD_USBDEVv2_USB_TRIM__OFFSET 0x00000000u
#define CYFLD_USBDEVv2_USB_TRIM__SIZE 0x00000002u
#define CYVAL_USBDEVv2_USB_TRIM_TRIM_NO 0x00000000u
#define CYVAL_USBDEVv2_USB_TRIM_TRIM_LOWER 0x00000001u
#define CYVAL_USBDEVv2_USB_TRIM_TRIM_HIGHER 0x00000002u
#define CYVAL_USBDEVv2_USB_TRIM_TRIM_DONT_USE 0x00000003u
#define CYFLD_USBDEVv2_USB_MDEC__OFFSET 0x00000002u
#define CYFLD_USBDEVv2_USB_MDEC__SIZE 0x00000001u
#define CYFLD_USBDEVv2_USB_MINC__OFFSET 0x00000003u
#define CYFLD_USBDEVv2_USB_MINC__SIZE 0x00000001u
#define CYFLD_USBDEVv2_USB_X_INC__OFFSET 0x00000004u
#define CYFLD_USBDEVv2_USB_X_INC__SIZE 0x00000001u
#define CYFLD_USBDEVv2_USB_X_DEC__OFFSET 0x00000005u
#define CYFLD_USBDEVv2_USB_X_DEC__SIZE 0x00000001u
#define CYDEV_CPUSS_BASE 0x40100000u
#define CYDEV_CPUSS_SIZE 0x00001000u
#define CYREG_CPUSS_CONFIG 0x40100000u
#define CYFLD_CPUSS_VECT_IN_RAM__OFFSET 0x00000000u
#define CYFLD_CPUSS_VECT_IN_RAM__SIZE 0x00000001u
#define CYREG_CPUSS_SYSREQ 0x40100004u
#define CYFLD_CPUSS_SYSCALL_COMMAND__OFFSET 0x00000000u
#define CYFLD_CPUSS_SYSCALL_COMMAND__SIZE 0x00000010u
#define CYFLD_CPUSS_DIS_RESET_VECT_REL__OFFSET 0x0000001bu
#define CYFLD_CPUSS_DIS_RESET_VECT_REL__SIZE 0x00000001u
#define CYFLD_CPUSS_PRIVILEGED__OFFSET 0x0000001cu
#define CYFLD_CPUSS_PRIVILEGED__SIZE 0x00000001u
#define CYFLD_CPUSS_ROM_ACCESS_EN__OFFSET 0x0000001du
#define CYFLD_CPUSS_ROM_ACCESS_EN__SIZE 0x00000001u
#define CYFLD_CPUSS_HMASTER_0__OFFSET 0x0000001eu
#define CYFLD_CPUSS_HMASTER_0__SIZE 0x00000001u
#define CYFLD_CPUSS_SYSCALL_REQ__OFFSET 0x0000001fu
#define CYFLD_CPUSS_SYSCALL_REQ__SIZE 0x00000001u
#define CYREG_CPUSS_SYSARG 0x40100008u
#define CYFLD_CPUSS_SYSCALL_ARG__OFFSET 0x00000000u
#define CYFLD_CPUSS_SYSCALL_ARG__SIZE 0x00000020u
#define CYREG_CPUSS_PROTECTION 0x4010000cu
#define CYFLD_CPUSS_PROTECTION_MODE__OFFSET 0x00000000u
#define CYFLD_CPUSS_PROTECTION_MODE__SIZE 0x00000004u
#define CYFLD_CPUSS_FLASH_LOCK__OFFSET 0x0000001eu
#define CYFLD_CPUSS_FLASH_LOCK__SIZE 0x00000001u
#define CYFLD_CPUSS_PROTECTION_LOCK__OFFSET 0x0000001fu
#define CYFLD_CPUSS_PROTECTION_LOCK__SIZE 0x00000001u
#define CYREG_CPUSS_PRIV_ROM 0x40100010u
#define CYFLD_CPUSS_BROM_PROT_LIMIT__OFFSET 0x00000000u
#define CYFLD_CPUSS_BROM_PROT_LIMIT__SIZE 0x00000008u
#define CYREG_CPUSS_PRIV_RAM 0x40100014u
#define CYFLD_CPUSS_RAM_PROT_LIMIT__OFFSET 0x00000000u
#define CYFLD_CPUSS_RAM_PROT_LIMIT__SIZE 0x00000009u
#define CYREG_CPUSS_PRIV_FLASH 0x40100018u
#define CYFLD_CPUSS_FLASH_PROT_LIMIT__OFFSET 0x00000000u
#define CYFLD_CPUSS_FLASH_PROT_LIMIT__SIZE 0x0000000cu
#define CYREG_CPUSS_WOUNDING 0x4010001cu
#define CYFLD_CPUSS_RAM_WOUND__OFFSET 0x00000010u
#define CYFLD_CPUSS_RAM_WOUND__SIZE 0x00000003u
#define CYFLD_CPUSS_FLASH_WOUND__OFFSET 0x00000014u
#define CYFLD_CPUSS_FLASH_WOUND__SIZE 0x00000003u
#define CYREG_CPUSS_FLASH_CTL 0x40100030u
#define CYFLD_CPUSS_FLASH_WS__OFFSET 0x00000000u
#define CYFLD_CPUSS_FLASH_WS__SIZE 0x00000002u
#define CYFLD_CPUSS_PREF_EN__OFFSET 0x00000004u
#define CYFLD_CPUSS_PREF_EN__SIZE 0x00000001u
#define CYFLD_CPUSS_FLASH_INVALIDATE__OFFSET 0x00000008u
#define CYFLD_CPUSS_FLASH_INVALIDATE__SIZE 0x00000001u
#define CYREG_CPUSS_ROM_CTL 0x40100034u
#define CYFLD_CPUSS_ROM_WS__OFFSET 0x00000000u
#define CYFLD_CPUSS_ROM_WS__SIZE 0x00000001u
#define CYDEV_SPCIF_BASE 0x40110000u
#define CYDEV_SPCIF_SIZE 0x00010000u
#define CYREG_SPCIF_GEOMETRY 0x40110000u
#define CYFLD_SPCIF_FLASH__OFFSET 0x00000000u
#define CYFLD_SPCIF_FLASH__SIZE 0x0000000eu
#define CYFLD_SPCIF_SFLASH__OFFSET 0x0000000eu
#define CYFLD_SPCIF_SFLASH__SIZE 0x00000006u
#define CYFLD_SPCIF_NUM_FLASH__OFFSET 0x00000014u
#define CYFLD_SPCIF_NUM_FLASH__SIZE 0x00000002u
#define CYFLD_SPCIF_FLASH_ROW__OFFSET 0x00000016u
#define CYFLD_SPCIF_FLASH_ROW__SIZE 0x00000002u
#define CYFLD_SPCIF_DE_CPD_LP__OFFSET 0x0000001fu
#define CYFLD_SPCIF_DE_CPD_LP__SIZE 0x00000001u
#define CYREG_SPCIF_INTR 0x401107f0u
#define CYFLD_SPCIF_TIMER__OFFSET 0x00000000u
#define CYFLD_SPCIF_TIMER__SIZE 0x00000001u
#define CYREG_SPCIF_INTR_SET 0x401107f4u
#define CYREG_SPCIF_INTR_MASK 0x401107f8u
#define CYREG_SPCIF_INTR_MASKED 0x401107fcu
#define CYDEV_CM0_BASE 0xe0000000u
#define CYDEV_CM0_SIZE 0x00100000u
#define CYREG_CM0_DWT_PID4 0xe0001fd0u
#define CYFLD_CM0_VALUE__OFFSET 0x00000000u
#define CYFLD_CM0_VALUE__SIZE 0x00000020u
#define CYREG_CM0_DWT_PID0 0xe0001fe0u
#define CYREG_CM0_DWT_PID1 0xe0001fe4u
#define CYREG_CM0_DWT_PID2 0xe0001fe8u
#define CYREG_CM0_DWT_PID3 0xe0001fecu
#define CYREG_CM0_DWT_CID0 0xe0001ff0u
#define CYREG_CM0_DWT_CID1 0xe0001ff4u
#define CYREG_CM0_DWT_CID2 0xe0001ff8u
#define CYREG_CM0_DWT_CID3 0xe0001ffcu
#define CYREG_CM0_BP_PID4 0xe0002fd0u
#define CYREG_CM0_BP_PID0 0xe0002fe0u
#define CYREG_CM0_BP_PID1 0xe0002fe4u
#define CYREG_CM0_BP_PID2 0xe0002fe8u
#define CYREG_CM0_BP_PID3 0xe0002fecu
#define CYREG_CM0_BP_CID0 0xe0002ff0u
#define CYREG_CM0_BP_CID1 0xe0002ff4u
#define CYREG_CM0_BP_CID2 0xe0002ff8u
#define CYREG_CM0_BP_CID3 0xe0002ffcu
#define CYREG_CM0_SYST_CSR 0xe000e010u
#define CYFLD_CM0_ENABLE__OFFSET 0x00000000u
#define CYFLD_CM0_ENABLE__SIZE 0x00000001u
#define CYFLD_CM0_TICKINT__OFFSET 0x00000001u
#define CYFLD_CM0_TICKINT__SIZE 0x00000001u
#define CYFLD_CM0_CLKSOURCE__OFFSET 0x00000002u
#define CYFLD_CM0_CLKSOURCE__SIZE 0x00000001u
#define CYFLD_CM0_COUNTFLAG__OFFSET 0x00000010u
#define CYFLD_CM0_COUNTFLAG__SIZE 0x00000001u
#define CYREG_CM0_SYST_RVR 0xe000e014u
#define CYFLD_CM0_RELOAD__OFFSET 0x00000000u
#define CYFLD_CM0_RELOAD__SIZE 0x00000018u
#define CYREG_CM0_SYST_CVR 0xe000e018u
#define CYFLD_CM0_CURRENT__OFFSET 0x00000000u
#define CYFLD_CM0_CURRENT__SIZE 0x00000018u
#define CYREG_CM0_SYST_CALIB 0xe000e01cu
#define CYFLD_CM0_TENMS__OFFSET 0x00000000u
#define CYFLD_CM0_TENMS__SIZE 0x00000018u
#define CYFLD_CM0_SKEW__OFFSET 0x0000001eu
#define CYFLD_CM0_SKEW__SIZE 0x00000001u
#define CYFLD_CM0_NOREF__OFFSET 0x0000001fu
#define CYFLD_CM0_NOREF__SIZE 0x00000001u
#define CYREG_CM0_ISER 0xe000e100u
#define CYFLD_CM0_SETENA__OFFSET 0x00000000u
#define CYFLD_CM0_SETENA__SIZE 0x00000020u
#define CYREG_CM0_ICER 0xe000e180u
#define CYFLD_CM0_CLRENA__OFFSET 0x00000000u
#define CYFLD_CM0_CLRENA__SIZE 0x00000020u
#define CYREG_CM0_ISPR 0xe000e200u
#define CYFLD_CM0_SETPEND__OFFSET 0x00000000u
#define CYFLD_CM0_SETPEND__SIZE 0x00000020u
#define CYREG_CM0_ICPR 0xe000e280u
#define CYFLD_CM0_CLRPEND__OFFSET 0x00000000u
#define CYFLD_CM0_CLRPEND__SIZE 0x00000020u
#define CYREG_CM0_IPR0 0xe000e400u
#define CYFLD_CM0_PRI_N0__OFFSET 0x00000006u
#define CYFLD_CM0_PRI_N0__SIZE 0x00000002u
#define CYFLD_CM0_PRI_N1__OFFSET 0x0000000eu
#define CYFLD_CM0_PRI_N1__SIZE 0x00000002u
#define CYFLD_CM0_PRI_N2__OFFSET 0x00000016u
#define CYFLD_CM0_PRI_N2__SIZE 0x00000002u
#define CYFLD_CM0_PRI_N3__OFFSET 0x0000001eu
#define CYFLD_CM0_PRI_N3__SIZE 0x00000002u
#define CYREG_CM0_IPR1 0xe000e404u
#define CYREG_CM0_IPR2 0xe000e408u
#define CYREG_CM0_IPR3 0xe000e40cu
#define CYREG_CM0_IPR4 0xe000e410u
#define CYREG_CM0_IPR5 0xe000e414u
#define CYREG_CM0_IPR6 0xe000e418u
#define CYREG_CM0_IPR7 0xe000e41cu
#define CYREG_CM0_CPUID 0xe000ed00u
#define CYFLD_CM0_REVISION__OFFSET 0x00000000u
#define CYFLD_CM0_REVISION__SIZE 0x00000004u
#define CYFLD_CM0_PARTNO__OFFSET 0x00000004u
#define CYFLD_CM0_PARTNO__SIZE 0x0000000cu
#define CYFLD_CM0_CONSTANT__OFFSET 0x00000010u
#define CYFLD_CM0_CONSTANT__SIZE 0x00000004u
#define CYFLD_CM0_VARIANT__OFFSET 0x00000014u
#define CYFLD_CM0_VARIANT__SIZE 0x00000004u
#define CYFLD_CM0_IMPLEMENTER__OFFSET 0x00000018u
#define CYFLD_CM0_IMPLEMENTER__SIZE 0x00000008u
#define CYREG_CM0_ICSR 0xe000ed04u
#define CYFLD_CM0_VECTACTIVE__OFFSET 0x00000000u
#define CYFLD_CM0_VECTACTIVE__SIZE 0x00000009u
#define CYFLD_CM0_VECTPENDING__OFFSET 0x0000000cu
#define CYFLD_CM0_VECTPENDING__SIZE 0x00000009u
#define CYFLD_CM0_ISRPENDING__OFFSET 0x00000016u
#define CYFLD_CM0_ISRPENDING__SIZE 0x00000001u
#define CYFLD_CM0_ISRPREEMPT__OFFSET 0x00000017u
#define CYFLD_CM0_ISRPREEMPT__SIZE 0x00000001u
#define CYFLD_CM0_PENDSTCLR__OFFSET 0x00000019u
#define CYFLD_CM0_PENDSTCLR__SIZE 0x00000001u
#define CYFLD_CM0_PENDSTSETb__OFFSET 0x0000001au
#define CYFLD_CM0_PENDSTSETb__SIZE 0x00000001u
#define CYFLD_CM0_PENDSVCLR__OFFSET 0x0000001bu
#define CYFLD_CM0_PENDSVCLR__SIZE 0x00000001u
#define CYFLD_CM0_PENDSVSET__OFFSET 0x0000001cu
#define CYFLD_CM0_PENDSVSET__SIZE 0x00000001u
#define CYFLD_CM0_NMIPENDSET__OFFSET 0x0000001fu
#define CYFLD_CM0_NMIPENDSET__SIZE 0x00000001u
#define CYREG_CM0_AIRCR 0xe000ed0cu
#define CYFLD_CM0_VECTCLRACTIVE__OFFSET 0x00000001u
#define CYFLD_CM0_VECTCLRACTIVE__SIZE 0x00000001u
#define CYFLD_CM0_SYSRESETREQ__OFFSET 0x00000002u
#define CYFLD_CM0_SYSRESETREQ__SIZE 0x00000001u
#define CYFLD_CM0_ENDIANNESS__OFFSET 0x0000000fu
#define CYFLD_CM0_ENDIANNESS__SIZE 0x00000001u
#define CYFLD_CM0_VECTKEY__OFFSET 0x00000010u
#define CYFLD_CM0_VECTKEY__SIZE 0x00000010u
#define CYREG_CM0_SCR 0xe000ed10u
#define CYFLD_CM0_SLEEPONEXIT__OFFSET 0x00000001u
#define CYFLD_CM0_SLEEPONEXIT__SIZE 0x00000001u
#define CYFLD_CM0_SLEEPDEEP__OFFSET 0x00000002u
#define CYFLD_CM0_SLEEPDEEP__SIZE 0x00000001u
#define CYFLD_CM0_SEVONPEND__OFFSET 0x00000004u
#define CYFLD_CM0_SEVONPEND__SIZE 0x00000001u
#define CYREG_CM0_CCR 0xe000ed14u
#define CYFLD_CM0_UNALIGN_TRP__OFFSET 0x00000003u
#define CYFLD_CM0_UNALIGN_TRP__SIZE 0x00000001u
#define CYFLD_CM0_STKALIGN__OFFSET 0x00000009u
#define CYFLD_CM0_STKALIGN__SIZE 0x00000001u
#define CYREG_CM0_SHPR2 0xe000ed1cu
#define CYFLD_CM0_PRI_11__OFFSET 0x0000001eu
#define CYFLD_CM0_PRI_11__SIZE 0x00000002u
#define CYREG_CM0_SHPR3 0xe000ed20u
#define CYFLD_CM0_PRI_14__OFFSET 0x00000016u
#define CYFLD_CM0_PRI_14__SIZE 0x00000002u
#define CYFLD_CM0_PRI_15__OFFSET 0x0000001eu
#define CYFLD_CM0_PRI_15__SIZE 0x00000002u
#define CYREG_CM0_SHCSR 0xe000ed24u
#define CYFLD_CM0_SVCALLPENDED__OFFSET 0x0000000fu
#define CYFLD_CM0_SVCALLPENDED__SIZE 0x00000001u
#define CYREG_CM0_SCS_PID4 0xe000efd0u
#define CYREG_CM0_SCS_PID0 0xe000efe0u
#define CYREG_CM0_SCS_PID1 0xe000efe4u
#define CYREG_CM0_SCS_PID2 0xe000efe8u
#define CYREG_CM0_SCS_PID3 0xe000efecu
#define CYREG_CM0_SCS_CID0 0xe000eff0u
#define CYREG_CM0_SCS_CID1 0xe000eff4u
#define CYREG_CM0_SCS_CID2 0xe000eff8u
#define CYREG_CM0_SCS_CID3 0xe000effcu
#define CYREG_CM0_ROM_SCS 0xe00ff000u
#define CYREG_CM0_ROM_DWT 0xe00ff004u
#define CYREG_CM0_ROM_BPU 0xe00ff008u
#define CYREG_CM0_ROM_END 0xe00ff00cu
#define CYREG_CM0_ROM_CSMT 0xe00fffccu
#define CYREG_CM0_ROM_PID4 0xe00fffd0u
#define CYREG_CM0_ROM_PID0 0xe00fffe0u
#define CYREG_CM0_ROM_PID1 0xe00fffe4u
#define CYREG_CM0_ROM_PID2 0xe00fffe8u
#define CYREG_CM0_ROM_PID3 0xe00fffecu
#define CYREG_CM0_ROM_CID0 0xe00ffff0u
#define CYREG_CM0_ROM_CID1 0xe00ffff4u
#define CYREG_CM0_ROM_CID2 0xe00ffff8u
#define CYREG_CM0_ROM_CID3 0xe00ffffcu
#define CYDEV_ROMTABLE_BASE 0xf0000000u
#define CYDEV_ROMTABLE_SIZE 0x00001000u
#define CYREG_ROMTABLE_ADDR 0xf0000000u
#define CYFLD_ROMTABLE_PRESENT__OFFSET 0x00000000u
#define CYFLD_ROMTABLE_PRESENT__SIZE 0x00000001u
#define CYFLD_ROMTABLE_FORMAT_32BIT__OFFSET 0x00000001u
#define CYFLD_ROMTABLE_FORMAT_32BIT__SIZE 0x00000001u
#define CYFLD_ROMTABLE_ADDR_OFFSET__OFFSET 0x0000000cu
#define CYFLD_ROMTABLE_ADDR_OFFSET__SIZE 0x00000014u
#define CYREG_ROMTABLE_DID 0xf0000fccu
#define CYFLD_ROMTABLE_VALUE__OFFSET 0x00000000u
#define CYFLD_ROMTABLE_VALUE__SIZE 0x00000020u
#define CYREG_ROMTABLE_PID4 0xf0000fd0u
#define CYFLD_ROMTABLE_JEP_CONTINUATION__OFFSET 0x00000000u
#define CYFLD_ROMTABLE_JEP_CONTINUATION__SIZE 0x00000004u
#define CYFLD_ROMTABLE_COUNT__OFFSET 0x00000004u
#define CYFLD_ROMTABLE_COUNT__SIZE 0x00000004u
#define CYREG_ROMTABLE_PID5 0xf0000fd4u
#define CYREG_ROMTABLE_PID6 0xf0000fd8u
#define CYREG_ROMTABLE_PID7 0xf0000fdcu
#define CYREG_ROMTABLE_PID0 0xf0000fe0u
#define CYFLD_ROMTABLE_PN_MIN__OFFSET 0x00000000u
#define CYFLD_ROMTABLE_PN_MIN__SIZE 0x00000008u
#define CYREG_ROMTABLE_PID1 0xf0000fe4u
#define CYFLD_ROMTABLE_PN_MAJ__OFFSET 0x00000000u
#define CYFLD_ROMTABLE_PN_MAJ__SIZE 0x00000004u
#define CYFLD_ROMTABLE_JEPID_MIN__OFFSET 0x00000004u
#define CYFLD_ROMTABLE_JEPID_MIN__SIZE 0x00000004u
#define CYREG_ROMTABLE_PID2 0xf0000fe8u
#define CYFLD_ROMTABLE_JEPID_MAJ__OFFSET 0x00000000u
#define CYFLD_ROMTABLE_JEPID_MAJ__SIZE 0x00000003u
#define CYFLD_ROMTABLE_REV__OFFSET 0x00000004u
#define CYFLD_ROMTABLE_REV__SIZE 0x00000004u
#define CYREG_ROMTABLE_PID3 0xf0000fecu
#define CYFLD_ROMTABLE_CM__OFFSET 0x00000000u
#define CYFLD_ROMTABLE_CM__SIZE 0x00000004u
#define CYFLD_ROMTABLE_REV_AND__OFFSET 0x00000004u
#define CYFLD_ROMTABLE_REV_AND__SIZE 0x00000004u
#define CYREG_ROMTABLE_CID0 0xf0000ff0u
#define CYREG_ROMTABLE_CID1 0xf0000ff4u
#define CYREG_ROMTABLE_CID2 0xf0000ff8u
#define CYREG_ROMTABLE_CID3 0xf0000ffcu
#define CYDEV_FLS_SECTOR_SIZE 0x00020000u
#define CYDEV_FLS_ROW_SIZE 0x00000080u
#endif /* CYDEVICE_TRM_H */
