# ########## TX2 STREAM ###########

# Set INT_TX_ENABLE bit high attached to delay enable with zero delay
STREAM      0
WRMASK      ADDR_SPI_TX2_CORE_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_TX_INT_DELAY_ENABLE 01 01
RETURN


# Set INT_TX_ENABLE bit low attached to delay enable with enableHold delay
STREAM      1
WRMASK      ADDR_SPI_TX2_CORE_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_TX_INT_DELAY_ENABLE 00 01
RETURN


# DMA Power up Config A (Pre-VCO Cal)
STREAM      2
# Reset status register
WR          ADDR_SPI_TX2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_17 00
# Write Byte 0 of starting Address
WR          ADDR_SPI_CORE_1_GENERAL_DMA_1_REGISTERS_GENERAL_DMA_1_START_TABLE_ADDR_BYTE0 CC
# Enable DMA
WR          ADDR_SPI_CORE_1_GENERAL_DMA_1_REGISTERS_GENERAL_DMA_1_CONTROL0 01
# Write Next_TX bit
WRMASK      ADDR_SPI_CORE_1_GENERAL_DMA_1_REGISTERS_GENERAL_DMA_1_CONTROL1 01 01
# Wait for Completion
RDWAIT      ADDR_SPI_TX2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_17 07 07
# Disable DMA
WRMASK      ADDR_SPI_CORE_1_GENERAL_DMA_1_REGISTERS_GENERAL_DMA_1_CONTROL0 00 01
# Wait for PLL lock
WAIT        $Pll1LockWait$
RETURN


# DMA Power up Config B (Post-VCO Cal and PLL Path Config and Power Up)
STREAM      3
# Calculate byte 0 of DMA address. Checks HOP_1_TOGGLE_READBACK. If frequency hopping mode is disabled 
# this register always reads back as 0
LD          R1 02
# Default address of DMA table
LD          R2 D0
RD          R0 ADDR_SPI_CORE_2_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_MAIN_HOP_TOGGLE_READBACK
AND         R0 R1
# Since hop read back for channel 2 now reads back 0x2, rather than 0x1 for channel 1, we can multiple
# the read back by 0x2, rather than 0x4, to get the appropriate DMA start address offset.
# R1 already contain 0x2
MUL         R0 R1
ADD         R0 R2       # R0 will be D0 (non-FH) or D4 (FH)
WRA         R0 ADDR_SPI_CORE_1_GENERAL_DMA_1_REGISTERS_GENERAL_DMA_1_START_TABLE_ADDR_BYTE0
# Reset status register
WR          ADDR_SPI_TX2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_17 00
# Enable DMA
WR          ADDR_SPI_CORE_1_GENERAL_DMA_1_REGISTERS_GENERAL_DMA_1_CONTROL0 01
# Write Next_TX bit
WRMASK      ADDR_SPI_CORE_1_GENERAL_DMA_1_REGISTERS_GENERAL_DMA_1_CONTROL1 01 01
# Wait for Completion
RDWAIT      ADDR_SPI_TX2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_17 07 07
# Disable DMA
WRMASK      ADDR_SPI_CORE_1_GENERAL_DMA_1_REGISTERS_GENERAL_DMA_1_CONTROL0 00 01
RETURN


# DMA Power Down Config (PLL path power down)    
STREAM      4
# Calculate byte 0 of DMA address. Checks HOP_1_TOGGLE_READBACK. If frequency hopping mode is disabled 
# this register always reads back as 0
LD          R1 02
# Default address of DMA table
LD          R2 D8
RD          R0 ADDR_SPI_CORE_2_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_MAIN_HOP_TOGGLE_READBACK
AND         R0 R1
# Since hop read back for channel 2 is now 0x2, rather than 0x1 for channel 1, we can multiple
# the read back by 0x2, rather than 0x4, to get the appropriate DMA start address offset.
# R1 already contain 0x2
MUL         R0 R1
ADD         R0 R2       # R0 will be D8 (non-FH) or DC (FH)
WRA         R0 ADDR_SPI_CORE_1_GENERAL_DMA_1_REGISTERS_GENERAL_DMA_1_START_TABLE_ADDR_BYTE0
# Reset status register
WR          ADDR_SPI_TX2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_17 00
# Enable DMA
WR          ADDR_SPI_CORE_1_GENERAL_DMA_1_REGISTERS_GENERAL_DMA_1_CONTROL0 01
# Write Next_TX bit
WRMASK      ADDR_SPI_CORE_1_GENERAL_DMA_1_REGISTERS_GENERAL_DMA_1_CONTROL1 01 01
# Wait for Completion
RDWAIT      ADDR_SPI_TX2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_17 07 07
# Disable DMA
WRMASK      ADDR_SPI_CORE_1_GENERAL_DMA_1_REGISTERS_GENERAL_DMA_1_CONTROL0 00 01
RETURN


# TX Hop Edge
STREAM      5
TIMEOUT     FFFF
############# Partial power down Tx each hop ############
# Mask DAC output
WRMASK      ADDR_SPI_TX2_CORE_TX_SSI_CONFIG_REGISTERS_TXDP_INTF_CONTROL C0 C0
# Save TX attenuation/mode, change to SPI mode, ramp down
CALL        1F
# Power down TX LO mux buf
WR          ADDR_SPI_CORE_1_ANALOG_REGISTERS_TX2_LO_REG 07
#########################################################

# SOFTWARE_SPARE_10: =0 in LO Mux FH modes (1 frame delay), =2 or 3 in LO Retune FH modes (0 frame delay).
# We can use bit 1 to indentify LO Mux FH mode (0) or LO Retune FH mode (1).
# Run this stream ONLY in LO Mux FH modes.
RD          R0 ADDR_SPI_TX2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_10
LD          R1 02
AND         R0 R1
# Trigger stream 0F "NCO LO SYNC 0 RISE" in LO Retune mode
CONDCALL    38
XOR         R0 R1
CONDCALL    35

# Mark next frame as none TX frame
WR          ADDR_SPI_TX2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_7 00
RETURN


# TX Hop Edge During TX High
STREAM      6
WR          ADDR_SPI_TX2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_7 01
RETURN


# TX Enable Rise
STREAM      7
TIMEOUT     FFFF
# Bypass stream 00 in Frequency Hopping mode
RD          R0 ADDR_SPI_TX2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_13
LD          R1 01
XOR         R0 R1
CONDCALL    00              # Set INT_TX_ENABLE bit high
RETURN


# TX Enable Rise During Hop Mode
STREAM      8
# SOFTWARE_SPARE_10: =0 in LO Mux FH modes (1 frame delay), =2 or 3 in LO Retune FH modes (0 frame delay).
# We can use bit 1 to indentify LO Mux FH mode (0) or LO Retune FH mode (1).
# Run this stream ONLY in FH LO Retune FH modes.
RD          R0 ADDR_SPI_TX2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_10
LD          R1 02
AND         R0 R1
CONDCALL    3B
RETURN


# TX Enable Fall
STREAM      9
# Assert SPI GPIO Bit 1 High
#WRMASK     ADDR_SPI_CORE_GPIO_1P8V_CONTROL_GPIO_1P8V_SPI_SOURCE_BYTE0 02 02
# Bypass stream 01 in Frequency Hopping mode
RD          R0 ADDR_SPI_TX2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_13
LD          R1 01
XOR         R0 R1
CONDCALL    01              # Set INT_TX_ENABLE bit low
RETURN


# TX ENABLE FALL DURING HOP MODE
STREAM      0A
# SOFTWARE_SPARE_10: =0 in LO Mux FH modes (1 frame delay), =2 or 3 in LO Retune FH modes (0 frame delay).
# We can use bit 1 to indentify LO Mux FH mode (0) or LO Retune FH mode (1).
# Run this stream ONLY in FH LO Mux FH modes.
RD          R0 ADDR_SPI_TX2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_10
LD          R1 02
AND         R0 R1
XOR         R0 R1
CONDCALL    3A
RETURN


# ORX ENABLE RISE
STREAM      0B
RETURN


# TX GAIN CHANGE RISE
STREAM      0C
RETURN


# TX GAIN RAMP UP RISE
STREAM      0D
RETURN


# DDC LO SYNC RISE
STREAM      0E
RETURN


# NCO LO SYNC 0 RISE
STREAM      0F
TIMEOUT     FFFF
# Wait on semaphore from ARM to update resources in LO Retune FH modes if it's TX frame
RD          R0 ADDR_SPI_TX2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_7
CONDCALL    39

# TX Hop Edge in LO MUX FH mode
CALL        35

# Reset semaphore from ARM to update resources in LO Retune FH modes
WR          ADDR_SPI_TX2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_10  03
RETURN


# NCO LO SYNC 1 RISE
STREAM      10
RETURN


# NCO LO SYNC 2 RISE
STREAM      11
RETURN


# ORX ENABLE FALL
STREAM      12
RETURN


# TX GAIN CHANGE FALL
STREAM      13
RETURN


# TX GAIN RAMPUP FALL
STREAM      14
RETURN


# INT_TX_DELAYED_ENABLE RISE (Enable TX digital, Power up LDO, PLL if Power Savings Mode > 0)
STREAM      15
TIMEOUT     FFFF
# Only set delay enables when not in FH mode
# Bypass stream 03 in Frequency Hopping mode
RD          R0 ADDR_SPI_TX2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_13
LD          R1 01
XOR         R0 R1
CONDCALL    20
# Trigger StreamProc1Int3_Handler() in ARM
#INTERRUPT   08
############# Power on LVDS pads ############
RD          R0 ADDR_SPI_TX2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_11
LD          R1 01
AND         R0 R1
CONDCALL    2E
#############################################
# Enable datapath clocks
WR          ADDR_SPI_TX2_CORE_TX_DATAPATH_CONFIG_ALL_TX_ENABLE 01
# Unmask interface to datapath
WR          ADDR_SPI_TX2_CORE_TX_SSI_CONFIG_REGISTERS_TXDP_INTF_CONTROL C0
# Enable TX Pfir based on device profile
RD 	    R0 ADDR_SPI_TX2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_0
CONDCALL    3C
RD          R0 ADDR_SPI_TX2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_4
CONDCALL    30                      # Call LDO Power Up stream
RD          R0 ADDR_SPI_TX2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_5
CONDCALL    31                      # Call PLL Power Up stream
$IfNoTx2FMDM$ RD        R0 ADDR_SPI_TX2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_5
$IfNoTx2FMDM$ CONDCALL  1D          # Call TX DAC Bias power up txPathConfig_Powerup
$IfTx2IntLo$  RD        R0 ADDR_SPI_TX2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_6
$IfTx2IntLo$  CONDCALL  02          # Call PLL retune Pre VCO cal stream
RETURN


# INT_DELAYED_0_ENABLE RISE (Power up TX analog)
STREAM      16
TIMEOUT     FFFF
$IfTx2IntLo$ RD         R0 ADDR_SPI_TX2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_1
$IfTx2IntLo$ CONDCALL   34          # Call PLL retune Pre VCO cal stream
CALL        03                      # Call PLL Post VCO cal stream, LO mux, LO gen, LO path power up
$IfTx2IntLo$  RD        R0 ADDR_SPI_TX2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_1
$IfTx2IntLo$  LD        R1 01
$IfTx2IntLo$  AND       R0 R1
$IfTx2IntLo$  CONDCALL  28          # Handle PLL phase sync
$IfNoTx2FMDM$ CALL      1B          # TX IQ power up substreams
$IfTx2FMDM$   CALL      1C          # TX FMDM power up substream
CALL        1E
# Set GPIO to high for debug if feature is enabled
RD          R0 ADDR_SPI_CORE_1_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_2
CONDCALL    2C
RETURN


# INT_DELAYED_1_ENABLE RISE (Set TX antenna switch)
STREAM      17
RD          R0 ADDR_SPI_TX2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_8
LD          R1 01
AND         R0 R1
CONDCALL    33
RETURN


# INT_TX_DELAYED_ENABLE FALL (Disable tracking calibration, TX digital datapath, interface)
STREAM      18
# Reset int_delay_0_enable bit attached to delay enable with txEnableFallToOffDelay - txEnableHoldDelay + 1
# Reset int_delay_1_enable bit attached to delay enable with txEnableFallToOffDelay - txEnableHoldDelay
WR          ADDR_SPI_TX2_CORE_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_TX_INT_DELAY_ENABLE 00 
# Disable TX Calibrations (DPD, QEC/LOL, CLGC RSSI/CC, GAN RSSI/CC)
WR          ADDR_SPI_TX2_CORE_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_TX_HW_DELAY_ENABLE 00
# Disable RX calibrations
#WR         ADDR_SPI_RX2_CORE_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_HW_DELAY_ENABLE_0 00
#WR         ADDR_SPI_RX2_CORE_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_HW_DELAY_ENABLE_1 00
# Mask interface from datapath
WRMASK      ADDR_SPI_TX2_CORE_TX_SSI_CONFIG_REGISTERS_TXDP_INTF_CONTROL 30 30
# Disable TX Pfir based on device profile
RD 	    R0 ADDR_SPI_TX2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_0
CONDCALL    3D
RETURN


# INT_DELAYED_0_ENABLE FALL (Power down TX analog) (ported from ARM txPathConfig_StreamPowerDown())
STREAM      19
TIMEOUT     FFFF
# Mask datapath from analog
WRMASK      ADDR_SPI_TX2_CORE_TX_SSI_CONFIG_REGISTERS_TXDP_INTF_CONTROL F0 F0
# Bypass stream 1F in Frequency Hopping mode
RD          R0 ADDR_SPI_TX2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_13
LD          R1 01
XOR         R0 R1
CONDCALL    1F              # Save TX attenuation/mode, change to SPI mode, ramp down
# Restore saved TX attenuation (NOTE: Must write the MSB first. Otherwise, the value won't latch)
RD          R0  ADDR_SPI_TX2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_3
WRA         R0  ADDR_SPI_TX2_CORE_TX_POWER_CONTROL_ATTENUATION_REGISTERS_TX_ATTENUATION_SPI_MODE_1
RD          R0  ADDR_SPI_TX2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_2
WRA         R0  ADDR_SPI_TX2_CORE_TX_POWER_CONTROL_ATTENUATION_REGISTERS_TX_ATTENUATION_SPI_MODE_0
# Power down pre-distorter, LO delay block ( buffer) and LO delay block (DAC)
WR          ADDR_SPI_TX2_ANA_POWER_DOWN_REGISTERS_TX_PD 76
# Power down upconverter
WR          ADDR_SPI_TX2_ANA_POWER_DOWN_REGISTERS_TX_PD 7E
# Power down the TXBBAF
WR          ADDR_SPI_TX2_ANA_POWER_DOWN_REGISTERS_TX_PD 7F
# Wait for 80ns
WAIT        $Delay_80ns$
# Wait for 80ns
WAIT        $Delay_80ns$
# Disable TX LO mux buf (removed because it's handled in DMA)
#WRMASK     ADDR_SPI_CORE_1_ANALOG_REGISTERS_TX2_LO_REG 04 04
#WR         ADDR_SPI_CORE_1_ANALOG_REGISTERS_TX2_LO_REG 07
# Disable TX LO Line recv buf
WRMASK      ADDR_SPI_TX2_ANA_POWER_DOWN_REGISTERS_LO_LINE_TERMINATION_CONTROL 04 04
#WR         ADDR_SPI_TX2_ANA_POWER_DOWN_REGISTERS_LO_LINE_TERMINATION_CONTROL 0C
# Wait for 80ns
WAIT        $Delay_80ns$
# Disable TX DAC top level clock
WR          ADDR_SPI_TX2_CORE_CLOCK_CONTROL_REGISTERS_CLOCK_CONTROL_4 00
# Toggle Datapath Reset
WRMASK      ADDR_SPI_TX2_CORE_TX_DATAPATH_CONFIG_TX_DP_RESET 01 01
WRMASK      ADDR_SPI_TX2_CORE_TX_DATAPATH_CONFIG_TX_DP_RESET 00 01
# Disable datapath clocks
WR          ADDR_SPI_TX2_CORE_TX_DATAPATH_CONFIG_ALL_TX_ENABLE 00
CALL        04                  # Power down PLL path
############ Power off LVDS pads ############
RD          R0 ADDR_SPI_TX2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_11
LD          R1 01
AND         R0 R1
CONDCALL    2D
#############################################
# Interrupt ARM: streamProc_tx2EnableFallHandler()
INTERRUPT   02
# Set GPIO to low for debug if feature is enabled
RD          R0 ADDR_SPI_CORE_1_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_2
CONDCALL    2B
RETURN


# INT_DELAYED_1_ENABLE FALL (Reset TX antenna switch)
STREAM      1A
RD          R0 ADDR_SPI_TX2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_8
LD          R1 01
AND         R0 R1
CONDCALL    32
RETURN


# TX Power Up IQ mode (ported from ARM txPathConfig_StreamPowerUp())
STREAM      1B
TIMEOUT     FFFF
# Power up the DAC ( excluding DAC Bias)
#WR         ADDR_SPI_TX2_DAC_TX_DAC_POWERDOWN_TXDAC_PWRDOWN_1 00
# Power Up the TXBBAF and upconverter
WR          ADDR_SPI_TX2_ANA_POWER_DOWN_REGISTERS_TX_PD 76
# Wait for 80 ns
WAIT        $Delay_80ns$
# Enable Top DAC clks
WR          ADDR_SPI_TX2_CORE_CLOCK_CONTROL_REGISTERS_CLOCK_CONTROL_4 80
# Wait for 80 ns
WAIT        $Delay_80ns$
# Enable TX LO Line recv buf
WRMASK      ADDR_SPI_TX2_ANA_POWER_DOWN_REGISTERS_LO_LINE_TERMINATION_CONTROL 00 04
#WR         ADDR_SPI_TX2_ANA_POWER_DOWN_REGISTERS_LO_LINE_TERMINATION_CONTROL 08
# Enable TX LO mux buf (removed because it's handled in DMA)
#WRMASK     ADDR_SPI_CORE_1_ANALOG_REGISTERS_TX2_LO_REG 00 04
#WR         ADDR_SPI_CORE_1_ANALOG_REGISTERS_TX2_LO_REG 02
# Wait for 80ns
WAIT        $Delay_80ns$
# Wait for 80ns
WAIT        $Delay_80ns$
# Power up LO delay block (DAC) and LO delay block (buffer)
WR          ADDR_SPI_TX2_ANA_POWER_DOWN_REGISTERS_TX_PD 16
# Wait for 80ns
WAIT        $Delay_80ns$
# Power up pre-distorter
WR          ADDR_SPI_TX2_ANA_POWER_DOWN_REGISTERS_TX_PD 12
RETURN


# TX Power Up DM Mode (ported from ARM txPredistorter_PowerUpDmMode())
STREAM      1C
TIMEOUT     FFFF
# Power up bias current distribution
WRMASK      ADDR_SPI_TX2_ANA_POWER_DOWN_REGISTERS_IDIST_CONTROL 00 01
# Configure Pre-distorter as a driver
WRMASK      ADDR_SPI_TX2_ANA_POWER_DOWN_REGISTERS_TX_PD2 01 01
# Increase bias current for 9dBm output power
WRMASK      ADDR_SPI_TX2_ANA_TX_UPCONVERTER_REGISTERS_TX_UPCONV_CONFIG0 03 03
# Enable TX LO Line recv buf
WRMASK      ADDR_SPI_TX2_ANA_POWER_DOWN_REGISTERS_LO_LINE_TERMINATION_CONTROL 00 04
# Enable TX LO mux buf (removed because it's handled in DMA)
#WRMASK     ADDR_SPI_CORE_1_ANALOG_REGISTERS_TX2_LO_REG 00 04
# Power up upconverter, lo delay (DAC, buffers), pre-distorter
WR          ADDR_SPI_TX2_ANA_POWER_DOWN_REGISTERS_TX_PD 13
RETURN


# TX Power Up TX DAC in IQ mode (ported from ARM txDac_Powerup())
STREAM      1D
TIMEOUT     FFFF
# Assume TX Attenuator is in ramp down state
# Enable TXDAC top level clock 
WRMASK      ADDR_SPI_TX2_CORE_CLOCK_CONTROL_REGISTERS_CLOCK_CONTROL_4 80 80
# txDac_Powerup
# WRITE_TXDAC_MEM_MAP_TXDAC_THROW_LSB_CTRL(base, 1u);
WRMASK      ADDR_SPI_TX2_DAC_TX_DAC_THROW_CONTROL_TXDAC_THROW_CTRL 01 03
# WRITE_TXDAC_MEM_MAP_TXDAC_THROW_ISB_CTRL(base, 1u);
WRMASK      ADDR_SPI_TX2_DAC_TX_DAC_THROW_CONTROL_TXDAC_THROW_CTRL 04 0C
# Wait for Supply/Clocks Ready
RDWAIT      ADDR_SPI_TX2_DAC_TX_DAC_POWERDOWN_TXDAC_PWRDOWN_3 80 80
# Power up the DACs
WRMASK      ADDR_SPI_TX2_DAC_TX_DAC_POWERDOWN_TXDAC_PWRDOWN_1 00 E0
# Wait for DAC power-up (17-35us),  bit 3 power up state I
RDWAIT      ADDR_SPI_TX2_DAC_TX_DAC_POWERDOWN_TXDAC_PWRDOWN_1 08 08
# bit 1 power up state Q
RDWAIT      ADDR_SPI_TX2_DAC_TX_DAC_POWERDOWN_TXDAC_PWRDOWN_1 02 02
# Increase DAC fullscale range by 2x to give the calibration more range to correct DAC errors
WRMASK      ADDR_SPI_TX2_DAC_TX_DAC_CALIBRATION_TXDAC_CALIBRATION_6 03 03
RETURN


# Ramp Up TX attenuator, restore TX attenuation mode and unmask DAC
STREAM      1E
TIMEOUT     FFFF
# Ramp Up TX attenuator
WR          ADDR_SPI_TX2_CORE_TX_POWER_CONTROL_ATTENUATION_REGISTERS_TDD_RAMP 01
# Wait for ramp up to complete
RDWAIT      ADDR_SPI_TX2_CORE_TX_POWER_CONTROL_ATTENUATION_REGISTERS_TDD_RAMP 00 01
# Restore saved TX attenuation mode
RD          R0  ADDR_SPI_TX2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_9
WRA         R0  ADDR_SPI_TX2_CORE_TX_POWER_CONTROL_ATTENUATION_REGISTERS_TX_TPC_CONFIG
# Unmask DAC
WR          ADDR_SPI_TX2_CORE_TX_SSI_CONFIG_REGISTERS_TXDP_INTF_CONTROL 00
# Interrupt ARM: streamProc_tx2EnableRiseHandler()
INTERRUPT   01
RETURN


# Save TX attenuation/mode, change to SPI mode, ramp down
STREAM      1F
TIMEOUT     FFFF
# Save current TX attenuation
WR          ADDR_SPI_TX2_CORE_TX_ATTENUATION_READ_REGISTERS_TX_ATTENUATION_0_READBACK   00
RD          R0  ADDR_SPI_TX2_CORE_TX_ATTENUATION_READ_REGISTERS_TX_ATTENUATION_0_READBACK
WRA         R0  ADDR_SPI_TX2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_2
RD          R0  ADDR_SPI_TX2_CORE_TX_ATTENUATION_READ_REGISTERS_TX_ATTENUATION_1_READBACK
WRA         R0  ADDR_SPI_TX2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_3
# Save current TX attenuation mode
RD          R0  ADDR_SPI_TX2_CORE_TX_POWER_CONTROL_ATTENUATION_REGISTERS_TX_TPC_CONFIG
LD          R1  F7              # keep fifo_overflow bit to 0
AND         R0  R1
WRA         R0  ADDR_SPI_TX2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_9
# Change current TX attenuation mode to SPI mode
WRMASK      ADDR_SPI_TX2_CORE_TX_POWER_CONTROL_ATTENUATION_REGISTERS_TX_TPC_CONFIG  01  03
# Ramp Down TX attenuator
WR          ADDR_SPI_TX2_CORE_TX_POWER_CONTROL_ATTENUATION_REGISTERS_TDD_RAMP 02
# Wait for ramp down to complete
RDWAIT      ADDR_SPI_TX2_CORE_TX_POWER_CONTROL_ATTENUATION_REGISTERS_TDD_RAMP 00 02
RETURN

# Set INT_DELAY_ENABLE's in normal mode
STREAM      20
# Set int_delay_0_enable bit attached to delay enable with txEnableRiseToAnalogOnDelay
# Set int_delay_1_enable bit attached to delay enable with txEnableRiseToOnDelay
WRMASK      ADDR_SPI_TX2_CORE_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_TX_INT_DELAY_ENABLE 06 06 
RETURN

STREAM      21
RETURN

STREAM      22
RETURN

STREAM      23
RETURN

STREAM      24
RETURN

STREAM      25
RETURN

STREAM      26
RETURN

STREAM      27
RETURN


# Handle PLL phase sync if enabled
STREAM      28
LD          R0 $PllPhaseSyncWait$
CONDCALL    2A
RETURN


STREAM      29
RETURN


# PLL phase sync
STREAM      2A
# Write to LO phase sync control SPI register
RD          R0 ADDR_SPI_CORE_1_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_6
SHIFT       R0 FD       # Right shift 3
LD          R1 01
AND         R0 R1       # R0: 0 (LO1) or 1 (LO2)
LD          R1 200
MUL         R0 R1       # R0: 0x0000 or 0x0200
LD          R1 ADDR_SPI_RF1_PLL_LO_PH_SYNC_REGS_PSCTL0
ADD         R0 R1       # R0: 0x1C4F (LO1) or 0x1E4F (LO2)
WRD         R0 81       # Abort any previous running phase sync
WAIT        $Delay_1us$
WRD         R0 6B       # Write caltyp value to start next phase sync
# Wait for PLL phase sync
WAIT        $PllPhaseSyncWait$
RETURN


# GPIO low observer
STREAM      2B
WAIT        5
# Set SPI GPIO bit 3 low
WRMASK      ADDR_SPI_CORE_GPIO_1P8V_CONTROL_GPIO_1P8V_SPI_SOURCE_BYTE0 00 08
RETURN


# GPIO high observer
STREAM      2C
WAIT        5
# Set SPI GPIO bit 3 high
WRMASK      ADDR_SPI_CORE_GPIO_1P8V_CONTROL_GPIO_1P8V_SPI_SOURCE_BYTE0 08 08
RETURN


# Power off LVDS pads (tx2_clk_lvds_ie, tx2_strobe_lvds_ie, tx2_Idata_lvds_ie, tx2_Qdata_lvds_ie, tx2_refclk_lvds_oe)
STREAM      2D
# Disable TX2 interface - will clear all local flags
WRMASK      ADDR_SPI_TX2_CORE_TX_SSI_CONFIG_REGISTERS_LSSI_TX_CONTROL 00 07
# Disable clock/strobe/idata/qdata
WRMASK      ADDR_SPI_CORE_LVDS_CMOS_CONFIG_REGISTERS_TX2_STROBE_LVDS_MODE_DELAY 00 01
WRMASK      ADDR_SPI_CORE_LVDS_CMOS_CONFIG_REGISTERS_TX2_CLK_LVDS_MODE_DELAY    00 01
WRMASK      ADDR_SPI_CORE_LVDS_CMOS_CONFIG_REGISTERS_TX2_IDATA_LVDS_MODE_DELAY  00 01
WRMASK      ADDR_SPI_CORE_LVDS_CMOS_CONFIG_REGISTERS_TX2_QDATA_LVDS_MODE_DELAY  00 01
# Enable TX REFCLK if SPARE_REGISTERS_11 bit 1 is 1
RD          R0 ADDR_SPI_TX2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_11
LD          R1 02
AND         R0 R1
SHIFT       R0 FF       # Right shift 1
R2          = R0
RD          R0 ADDR_SPI_CORE_LVDS_CMOS_CONFIG_REGISTERS_TX2_REFCLK_LVDS_MODE_DELAY
LD          R1 FE
AND         R0 R1
OR          R0 R2
WRA         R0 ADDR_SPI_CORE_LVDS_CMOS_CONFIG_REGISTERS_TX2_REFCLK_LVDS_MODE_DELAY
RETURN


# Power on LVDS pads (tx2_clk_lvds_ie, tx2_strobe_lvds_ie, tx2_Idata_lvds_ie, tx2_Qdata_lvds_ie, tx2_refclk_lvds_oe)
STREAM      2E
# Clear TX LVDS FIFO (self clear bit)
# WRMASK      ADDR_SPI_TX2_CORE_TX_SSI_CONFIG_REGISTERS_LSSI_TX_CONTROL           08 08
# Enable the TX2 FIFO interface and Reset TX2 FIFO pointers
WRMASK      ADDR_SPI_TX2_CORE_TX_SSI_CONFIG_REGISTERS_LSSI_TX_CONTROL           06 06
WRMASK      ADDR_SPI_TX2_CORE_TX_SSI_CONFIG_REGISTERS_LSSI_TX_FIFO_CONTROL_RESET 03 03
# Enable TX2 LSSI interface pads
# Enable REFCLK if SPARE_REGISTERS_11 bit 5 is 1 (Tx Ref clock enabled)
RD          R0 ADDR_SPI_TX2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_11
LD          R1 20
AND         R0 R1
SHIFT       R0 FB       # Right shift 5
R2          = R0
RD          R0 ADDR_SPI_CORE_LVDS_CMOS_CONFIG_REGISTERS_TX2_REFCLK_LVDS_MODE_DELAY
LD          R1 FE
AND         R0 R1
OR          R0 R2
WRA         R0 ADDR_SPI_CORE_LVDS_CMOS_CONFIG_REGISTERS_TX2_REFCLK_LVDS_MODE_DELAY
WRMASK      ADDR_SPI_CORE_LVDS_CMOS_CONFIG_REGISTERS_TX2_IDATA_LVDS_MODE_DELAY  01 01
# Enable QDATA if SPARE_REGISTERS_11 bit 4 is 1 (2 lane LVDS)
RD          R0 ADDR_SPI_TX2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_11
LD          R1 10
AND         R0 R1
SHIFT       R0 FC       # Right shift 4
R2          = R0
RD          R0 ADDR_SPI_CORE_LVDS_CMOS_CONFIG_REGISTERS_TX2_QDATA_LVDS_MODE_DELAY
LD          R1 FE
AND         R0 R1
OR          R0 R2
WRA         R0 ADDR_SPI_CORE_LVDS_CMOS_CONFIG_REGISTERS_TX2_QDATA_LVDS_MODE_DELAY
WRMASK      ADDR_SPI_CORE_LVDS_CMOS_CONFIG_REGISTERS_TX2_CLK_LVDS_MODE_DELAY    01 01
WRMASK      ADDR_SPI_CORE_LVDS_CMOS_CONFIG_REGISTERS_TX2_STROBE_LVDS_MODE_DELAY 01 01
# start TX2 interface -> will start monitoring Strobe to set early/late flag
WRMASK      ADDR_SPI_TX2_CORE_TX_SSI_CONFIG_REGISTERS_LSSI_TX_CONTROL           01 01
# Release TX2 FIFO
WRMASK      ADDR_SPI_TX2_CORE_TX_SSI_CONFIG_REGISTERS_LSSI_TX_FIFO_CONTROL_RESET 00 03
RETURN


# To be called by TX Hop Edge Stream 5
STREAM      2F
# Retune PLL if required
$IfTx2IntLo$ RD         R0 ADDR_SPI_TX2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_1
$IfTx2IntLo$ CONDCALL   34          # Call PLL retune Pre VCO cal stream
# Ensure Config B DMA tables have been processed
RDWAIT      ADDR_SPI_TX2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_18 01 01
WR          ADDR_SPI_TX2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_18 00
# DMA Power up Config B (Post-VCO Cal and PLL Path Config and Power Up)
CALL        03
# Handle PLL phase sync
CALL        28
# Ramp up tx attenuator and interrupt ARM
CALL        1E
RETURN


# DMA Power up Config C (LDO Power Up)
STREAM      30
# Reset status register
WR          ADDR_SPI_TX2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_17 00
# Write Byte 0 of starting Address
WR          ADDR_SPI_CORE_1_GENERAL_DMA_1_REGISTERS_GENERAL_DMA_1_START_TABLE_ADDR_BYTE0 F8
# Enable DMA
WR          ADDR_SPI_CORE_1_GENERAL_DMA_1_REGISTERS_GENERAL_DMA_1_CONTROL0 01
# Write Next_TX bit
WRMASK      ADDR_SPI_CORE_1_GENERAL_DMA_1_REGISTERS_GENERAL_DMA_1_CONTROL1 01 01
# Wait for Completion
RDWAIT      ADDR_SPI_TX2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_17 07 07
# Disable DMA
WRMASK      ADDR_SPI_CORE_1_GENERAL_DMA_1_REGISTERS_GENERAL_DMA_1_CONTROL0 00 01
# Wait for LDO power up
WAIT        $LdoPowerUpWait$
RETURN


# DMA Power up Config D (PLL Power Up)  
STREAM      31
# Reset status register
WR          ADDR_SPI_TX2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_17 00
# Write Byte 0 of starting Address
WR          ADDR_SPI_CORE_1_GENERAL_DMA_1_REGISTERS_GENERAL_DMA_1_START_TABLE_ADDR_BYTE0 FC
# Enable DMA
WR          ADDR_SPI_CORE_1_GENERAL_DMA_1_REGISTERS_GENERAL_DMA_1_CONTROL0 01
# Write Next_TX bit
WRMASK      ADDR_SPI_CORE_1_GENERAL_DMA_1_REGISTERS_GENERAL_DMA_1_CONTROL1 01 01
# Wait for Completion
RDWAIT      ADDR_SPI_TX2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_17 07 07
# Disable DMA
WRMASK      ADDR_SPI_CORE_1_GENERAL_DMA_1_REGISTERS_GENERAL_DMA_1_CONTROL0 00 01  
RETURN


# Reset TX antenna switch (AGPIO bit 8 low)
STREAM      32
WRMASK      ADDR_SPI_CORE_1_GPIO_ANALOG_CONTROL_GPIO_ANALOG_SPI_SOURCE_11_8  00  01
RETURN


# Set TX antenna switch (AGPIO bit 8 high)
STREAM      33
WRMASK      ADDR_SPI_CORE_1_GPIO_ANALOG_CONTROL_GPIO_ANALOG_SPI_SOURCE_11_8  01  01
RETURN


# PLL retune Pre VCO cal or only wait for PLL lock (R0: SOFTWARE_SPARE_1)
STREAM      34
R2          = R0
LD          R1 01
AND         R0 R1
CONDCALL    02        # Call PLL retune Pre VCO cal stream
R0          = R2
LD          R1 02
AND         R0 R1
CONDCALL    37        # Wait for PLL lock by another stream without retuning LO
RETURN


# TX Hop Edge in LO MUX FH mode
STREAM      35
# Read status of SPARE_12 to register and then clear it. 
# FW will reset if required.
# NOTE: This may be looked at for day 15.
RD          R4 ADDR_SPI_TX2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_12
WR          ADDR_SPI_TX2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_12 00

#################### Check Tx status #####################
# Check to see if partial power up (tx atten ramp, lo mux, etc) is required
# or full power up
RD          R0 ADDR_SPI_TX2_CORE_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_TX_INT_DELAY_ENABLE
LD          R1 06
AND         R0 R1
# R0 (SOFTWARE_SPARE_12) is either 0x0 or 0x7, and R4 can be 0x1, 0x3, or 0x7
# Since we just need to know if all bits in INT_DELAY_ENABLE are set, we just AND with R0
AND         R0 R4
CONDCALL    2F
##########################################################

################## Set Tx power down #####################
CALL        3A
##########################################################

##################### AFE Power up  ######################
# Set int_delay_0_enable bit attached to delay enable with txEnableRiseToAnalogOnDelay
# Set int_delay_1_enable bit attached to delay enable with txEnableRiseToOnDelay
# If this is the first hop edge, INT_TX_ENABLE will already have been set,
# and therefore we will only be powering up AFE here.
# If this is end of frame, the call to 3A above will have already powered down digital and AFE.
# TODO: We might be able to remove the call to 3A and replace it with this
# If this 'just another ol' tx frame', the bits in the delay enable will already be set
# (depending on INT_TX_ENABLE priority) 
RD          R0 ADDR_SPI_TX2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_7
OR          R0 R4
WRA         R0 ADDR_SPI_TX2_CORE_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_TX_INT_DELAY_ENABLE
##########################################################
RETURN


STREAM      36
RETURN


# Wait for PLL lock
STREAM      37
WAIT        $Pll1LockWait$
RETURN


# Trigger stream 0F "NCO LO SYNC 0 RISE"
STREAM      38
WRMASK      ADDR_SPI_CORE_2_BBIC_INTERFACE_REGISTERS_BBIC_TX2_BYTE2  00  01
WRMASK      ADDR_SPI_CORE_2_BBIC_INTERFACE_REGISTERS_BBIC_TX2_BYTE2  01  01
RETURN


# Wait on semaphore from ARM to update resources in LO Retune FH modes
STREAM      39
RDWAIT      ADDR_SPI_TX2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_10  02  03
RETURN


# Set INT_TX_ENABLE bit according to SOFTWARE_SPARE_7 attached to delay enable with zero delay (LO mux FH mode)
STREAM      3A
RD          R0 ADDR_SPI_TX2_CORE_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_TX_INT_DELAY_ENABLE
LD          R1 FE
AND         R0 R1
RD          R1 ADDR_SPI_TX2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_7
OR          R0 R1
WRA         R0 ADDR_SPI_TX2_CORE_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_TX_INT_DELAY_ENABLE
RETURN


# Set INT_TX_ENABLE bit to 1 attached to delay enable with zero delay (LO retune FH mode)
STREAM      3B
RD          R0 ADDR_SPI_TX2_CORE_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_TX_INT_DELAY_ENABLE
LD          R1 FE
AND         R0 R1
LD          R1 01
OR          R0 R1
WRA         R0 ADDR_SPI_TX2_CORE_PROGRAMMABLE_DELAYED_ENABLE_REGISTERS_TX_INT_DELAY_ENABLE
RETURN

# Enalbe TX Pfir dynamically
STREAM      3C
RD          R0 ADDR_SPI_TX2_CORE_SOFTWARE_SPARE_REGISTERS_SOFTWARE_SPARE_0
WRA         R0 ADDR_SPI_TX2_CORE_TX_DATAPATH_CONFIG_TX_PFIR_ENABLE
RETURN

# Disable TX Pfir
STREAM      3D
WR          ADDR_SPI_TX2_CORE_TX_DATAPATH_CONFIG_TX_PFIR_ENABLE 00
RETURN

STREAM      3E
RETURN

STREAM      3F
RETURN
